RE: [oc] Re: How to create such signal wave using VHDL?

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Hanzy,

I make no warranty about the useful of my advice or my sanity.

As I understand it you wish to have a signal hi for 1024 clocks then low forever?
Can tell you how to do it on a Xilinx chip but not guaranteed for Alteras or ASICs.
Xilinx have a component for either Spartan2, Virtex or XC4000 units.

Heres the Spartan2 code cut from Webpack

 
-- Instantiating STARTUP in SPARTAN2 
--    MY_GSR: in std_logic;
 
--**Insert the following between the 'architecture' and
---'begin' keywords**
 
   component STARTUP_SPARTAN2 
   port (GSR: in std_logic);
   end component;
 
--**Insert the following after the 'begin' keyword**
 
   U1: STARTUP_SPARTAN2 port map (GSR=>MY_GSR);


then try this code in

process(MY_GSR)
begin

if rising_edge (MY_GSR) then		-- looks better than instead of the older MY_GSR'event and MY_GSR='1'" 

	counter = 0 ;

	your_signal <= '1' ;

end if ;


end process ;

process(clk)
begin
	counter = counter + 1 ;

	if counter = 1024 and signal = '0' then
		signal <= '1' ;
	end if ;
end process ;


Hopefully that will work, none of my VHDL programs in Webpack never worked properly
whereas all my Verilog ones work perfectly so you might be luckier than me.

Paul

> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On Behalf Of zeyaohan
> Sent: 13 December 2001 07:53
> To: cores@opencores.org
> Subject: [oc] Re: How to creat such signal wave using VHDL?
> 
> 
> I meet such problem in using VHDL to creat such signal wave:
> 
> such as the following wave:
> firstly I think it's a easy problem, but I find that in IF centence, after some event it can not exit, do i need to use 
> Loop centence then use exit syntax?
> 
> 
> ----------------------\
> 					   \----------------------------------------------------
> |<---1024 CLK-------->| |<----------------Infinitely Long-------------------
> 
> my process is the following:
> 
> process(clk)
> begin
> 	if clk'event and clk='1' then
> ............
> ............
> ............
> 	end if;
> end process;
> 
> 
> B.R
> 		hanzy
> 
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