RE: [oc] New 64bit instructions for 32bit processor cores analogy

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Dani,

Wouldn't matter much on my PC, disk access is so slow I sometimes wonder
whether I'm accessing the floppy or not. Gotta love Win98, when I dual
boot to Win2K the same performance program rates the same drives at
5x faster. Good old Microsoft, now where did I leave my voodoo doll?

Yes a variable length instruction is possible and available commercially.
www.motorola.com/coldfire products use it. They call it VL-RISC which
presumably stands for Variable Length RISC. Looked at using their CPUs
in some projects briefly before I discovered FPGAs. They are aimed at
SoC type areas hence the processors have everything up to and including
Ethernet/USB ports on them. Harvard memory architecture, built-in DRAM 
controllers (except the lower 2 models) and other things. It might have
even have a 10 stage pipeline, 10 blocks in the diagram anyway ;-)

Still working on the computer with a CPU core for the Linux project so
maybe crack that one when I can devote some time to it. :)

Paul

-----Original Message-----
From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
Behalf Of Daniel Haensse
Sent: 11 December 2001 12:38
To: cores@opencores.org
Subject: Re: [oc] New 64bit instructions for 32bit processor cores
analogy


Paul,

the problem will be that your harddisk will swap 4x as much and read/write 
larger data or code from the harddisk. What do you think about a variable 
instruction length, instead of a fixed 64 bit length? Is this possible?

Dani


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