[oc] A 'core server' ?

[John Dalton <john.dalton@bigfoot.com>]

Hi all,

In writing an FFT core for opencores,
I have been confronted by a couple
of dilemmas.  These are:

1) How can I write a core in a language
   independent way?  It should be able to
   support both VHDL and Verilog as a
   minimum.

2) How can a write a core with complex
   parameterisation?  For example, depending
   on the width of the FFT, the precision of
   calculation to generate the twiddle factors
   should be varied.  This does not seem to
   be easy in VHDL or Verilog.

So far, the best solution I have thought of
is to write my core in a high level, generic,
language and automatically translate it to
either Verilog or VHDL.  I am leaning towards
picking Scheme (similar to LISP), or THUD
(Scheme with HDL extensions) as my generic
language.  Scheme has the advantages of trivial
parsing and extensibility.  Also, a Scheme
generator can be easily written in Scheme.

Eventually, this could even turn into a 'core server'
(or library?). This server would be a program which
runs in the background and serves up cores in the
language of choice to a client.  The client may be
a GUI, a simulator, a synthesiser or whatever you want.
Existing VHDL and Verilog analysers could be adapted
to translate existing opencores to Scheme, allowing
them to be served up by the server (in any language).

(By the by, it would be really neat to implement this
as a HURD translator.)

Before I embark on this non-trivial project, does
anyone have a better solution, or know of an
existing GPLed product which is similar?

Best wishes
John
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