Re: [oc] synthesis problem with uart16550

[Jacob Gorban <jacob.gorban@flextronicsdesign.co.il>]

Matthias Fuchs wrote:

> Hi,
> 
> during the synthesis of the uart16550 verilog code with xilinx xst
> synthesis tool(included in the webpak software suite)
> I got this warning that later results in an error:
> 
> WARNING : (FCT__0306). Multi-source on signal <shift_out<0>> not
> replaced by logic
> 
> I get this warning for every bit of the shift_out register.
> 
> I think it is not an error in the design. The diffenret assignments are
> made by different cases in a state maschine.
> So what could be my problem ? Any idea ?
> 
> Matthias
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> 

My guess is that you hava a VERY old version of the uart16550 core.
Download the latest version from the CVS. It is synthesizable (tested).


-- 
Jacob Gorban
Flextronics Semiconductor
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F: +972-8-9275552
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Israel

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