Re: [oc] logic for 128bit hdlc

[Allan Herriman <allan_herriman.hates.spam@agilent.com>]

naveena.padmaraju@wirpo.com wrote:
> we are designing HDLC core of 64bit interface in physical & network side. but internal to hdlc is 128bit parallel processing.
> i want logic for bytestuffing and how effectively i can allign bytes and send it to 64bit at time to physical side. with out using any FIFO inside.

Hi Naveena,

I designed one of these last year for operation at 10Gbps.

This is very difficult to design without FIFOs because the byte stuffing
increases the "bandwidth" of the signal in an unpredictable manner as it
passes through the encoder.  
Obviously this isn't going to work at all if you have a fixed bit rate
for the source and sink of the data.
Since the network side (the sink for the encoded data) has a fixed bit
rate, you need somehow to control the bit rate of the data source. 
Since your data source will respond to the hold-off signal from the
encoder with a finite latency, your encoder needs to be able to store
the excess bits for a while.  Hence the need for a FIFO.

Regards,
Allan.
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