RE: [oc] UART16550 core

["Igor Mohor (uni-mb)" <igor.mohor@uni-mb.si>]

Hi, Carl,

can you put things regarding UART to the cvs or mail them to me. I would
like to write a good testbench and don't want to debug a design that you
already debuged.

Regards,
	Igor

> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> Behalf Of Carl van Schaik
> Sent: 04. avgust 2001 14:47
> To: cores@opencores.org
> Subject: Re: [oc] UART16550 core
>
>
> > Great.
> >
> > Is the host interface wishbone compatible?
> I hope so :-)
>
> > If I understood correctly you took the UART16650 from the opencores when
> you
> > started, and chenged it a bit, right? Do you have any
> testbenches already
> > avaliable?
> Original ideas taken from the UART16550 but a lot is different too.
>
> I don't have access to Model Sim, hopefully we will get a license soon.
> I only have some vector tests that I made with the Xilinx Timing analyser.
>
> regards
> Carl van Schaik
>
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