Re: [oc] Pulse width discriminator

["Carl van Schaik" <carl@openfuel.com>]

Hi

> I am almost a new user of opencore,and also I am a newly gradauted girl.
>
> I have to do a project on my job which I will be very grateful if someone
> help me.
>
> First of all the title of project is "Pulse width discriminator"
> We have a bit stream as an input and an other one as an output.
> This core has to discriminate pulses with special widths(Range:0.1us~6us)
> and filter it and show it on output stream.As it is a causal system ,its
> output can be exactly after every pulse or after a deterministic
> delay.Features of desired pulses and this delay and also the resolution
> which its minimum is 0.05us will be user defined and a program unit do
this
> task.
>
> For implementing this core the first thing which I thought was sth like a
> Logic Analyzer.We have a clock which samples from a stream and then a unit
> which show it at output.But because I am beginner I have no idea about the
> timing of FPGAs.I will be very thankful if someone tell me what is the
> highest practical clock for example for a FLEX10K10 or for other ones.
>
> Thank you in advance,
>
>   Golnaz Vahedi

The FLEX FPGA should easily handle around 50Mhz.which is 20ns (0.02us) so
the timing
problems should not be too difficult. Input to Clock to Ouput delay will
probably be
about 10-15ns.
Other new FPGA's will do much high clock frequencies, you will probably
start to need to use the DLL's and clock multiplication.

regards
Carl van Schaik
--
OpenFuel Pty Ltd.

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