Re: [oc] Testing Implemented Design in FPGA

["Jim W" <johnsonw10@hotmail.com>]

The paragraph below is taken from Xilinx web site and explains how the 
Chipscope works.

    "The ChipScope ILA Flow
    The ILA and Control cores are generated through the Web using a Java
    application. The cores are inserted into the design HDL code and 
connected to
    the internal busses and signals to be extracted. Then the design is
    synthesized and placed and routed using Xilinx' Foundation or Alliance 
series
    tools. The bitstream is downloaded and can be analyzed through the 
ChipScope
    software."

I haven't used the Chipscope, so I don't know if the cores have Xilinx 
macros. ( but from a business standpoint, it would make more sense to Xilinx 
to make the cores Xilinx-specific.) One thing is sure is that the probes are 
not inserted after PAR. By the way, Xilinx sells the cores for $495 and $895 
with MultiLINX cable.

Jim



>From: Victor the Cleaner <jonathan@canuck.com>
>Reply-To: cores@opencores.org
>To: cores@opencores.org
>Subject: Re: [oc] Testing Implemented Design in FPGA
>Date: Tue, 5 Jun 2001 20:21:11 -0600
>
>On Wed, Jun 06, 2001 at 09:23:32AM +0800, ZhangMutong wrote:
> > Hi,
> > Why not go and find a LA --- logic analyzer? Cute enough. I love it.
> > Furthermore, anyone has idea about Xilinx's ChipScope? I know it is a 
>set
> > of cores and host applications. You can embeded the core into your own
> > FPGA implementation, and use the host application to debug your logic. 
>Am
>
>I should note that I haven't played with it myself, but I was pretty
>thrilled with the idea when I first saw it discussed at a Xilinx seminar
>about a year ago.  I should get off my ass and get it...
>
> > I right? Anyone will give us some more imformation? Where can I get a 
>free
> > copy? :)
>
>From what I recall, they were pretty much giving the core away - it was
>something like $100 when you bought the Multilinx cable, which is needed
>to use it.  Still, though, even after you spend $500 or whatever the
>Multilinx cable costs, it's a damn good deal.
>
> > 	Or, anybody has interesting in building a similar product and send it
> > to OpenCore? That will be a good thing. Bow!
>
>It'd need a fundamentally different approach than that taken by Xilinx,
>I think.  If it's anything like "probing" using Foundation's FPGA Editor,
>the nets are specified and probed *after* PAR, making it a technology-
>specific thing.
>
>It would certainly be a win to move it "upwards" in the design so that
>it's easier port to different manufacturers.  More information is needed -
>has anyone on-list used it?  Are any of the other vendors doing anything
>similar?
>
>Jonathan
>

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