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Re: [oc] WISHBONE DMA/Bridge

I think in VHDL would be better,because I only understand VHDL, hehe
----- Original Message ----- 
From: "Rudolf Usselmann" <rudi@asics.ws>
To: "OPENCORES" <cores@opencores.org>
Sent: Monday, March 19, 2001 9:25 PM
Subject: [oc] WISHBONE DMA/Bridge


> 
> I have finished the WISHBONE DMA/Bridge IP core and
> checked in the Verilog Source code.
> 
> Please see the "WISHBONE DMA" page for more info.
> 
> http://www.opencores.org/cores/wb_dma
> 
> Cheers !
> -- 
> rudi
> 
>