Re: [oc] Internal IP Bus (was ATA-3 (EIDE) Opencore)

["Winefred Washington" <wwashington@austin.rr.com>]

Rudi,

Thanks for the email. I looked at the spec briefly and it looks good. What
are the outstanding issues on the internal IP bus?

I've emailed Damjan, but I haven't heard anything back from him yet.

WW

----- Original Message -----
From: "Rudolf Usselmann" <rudi@asics.ws>
To: <cores@opencores.org>
Sent: Friday, December 29, 2000 6:22 PM
Subject: Re: [oc] ATA-3 (EIDE) Opencore


>
> Winefred,
>
> I'm not sure about the status of the IDE core, may be Damjan can fill
> that in.
>
> For the internal IP bus, we are leaning towards Wishbone. The decision is
> not final yet, but I think there are no alternatives. All other either
> require a license or fees.
>
> Wishbone can be found at:
> http://www.silicore.net/pdfiles/wishbone.pdf
>
> Best Regards,
> rudi
>
> on 12/29/00 22:25, Winefred Washington at wwashington@austin.rr.com wrote:
> > Hello,
> >
> > If the design in still open, I'd like to develop the IDE core. I'm an EE
> > with Verilog experience. I also have several years of experience with
Xilinx
> > Virtex FPGAs. I don't have much experience with CVS, but I do have a
book.
> >
> > Is there a specification for an internal IP bus to connect various cores
> > together?
> >
> > Thanks in advance,
> > WW
> >
> >
> >
> >
>