Re: [oc] miniUART VHDL errors in XIlinx Foundation series

[fila314@21CN.COM]

Hi,when I first  use Xilinx Foundation,I have also met this problem ,it have confused me a long  time .At last I knew  the reason is that "initial ,time....."can not be synthesized ,so when you code HDL ,you should avoid use "initial ,time.....".(I am using Verilog)

But I still have a big question ,"initial ,time....."can be used in testbench
(simulate) code ,in Xilinx Foundation I can not find where can I code the testbench code? 
(though in language assitant you can find the example ofusing "initial...")Now ,I can only use waveorm to simulate the code.

So, if you know,can you tell me?

Regards
fila314


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