RE: [oc] New License update

["Joe Zott" <jaz@itvc.com>]

>Lets adopt GPL !

But I don't know what the GPL means in the context of chips.

For example, what does the term "link" mean when you apply GPL to a chip
design? Do you want it to mean tightly bound integration like in the
software sense?

If so then you can't use commercial cell libraries. The Verilog/VHDL designs
that you see represent the instructions on how to select and arrange cells.

There are few non-commercial cell libraries (e.g., MOSIS SCMOS) and none
that are available for the kinds of designs that I have seen being proposed
(e.g., to use the SCMOS library in a synthesis design you need a synthesis
library - the only one that I know of for SCMOS is Tanner's commercial
version).

Those people wishing to create their own cell libraries will probably have
to sign a non-disclosure agreement with the fab(s) that they choose to
target.

Does "link" only mean integration at the RTL level? Since synthesizers often
"link" in low level RTL (e.g., Synopsys DesignWare) during synthesis does
this mean that such techniques couldn't be used in and "open" design flow?

I praise and encourage anyone who attempts to write an open license
agreement suitable for chips. Having an accepted license is, I believe,
essential to having a viable open chip environment.