Re: [fpu] fdiv

[Jamil Khatib <jamilkhatib75@yahoo.com>]

> > 
> > I think we discussed about the post and pre
> > normalization long time ago. I suggest to make the
> > post normalization a configurable feature in the
> core.
> 
> Hmm, I believe post normalization should be done by
> the individual
> cores. May be we can combine it later.
> 

But do not you think that some numbers should be left
denormalized? you can refere to
http://www.geocities.com/SiliconValley/Pines/6639/docs/fp_summary.html

Anyhow if we do normalization after each operation
where the denormalized numbers are going to come from?

(fdiv takes the denormalized numbers)

> > About rounding I thought that there should be a
> > seperate block to perform the rounding unless you
> mean
> > teh conversion from the extended format to the
> single
> > one?
> 
> I do mean rounding. When you divide 1 by 3 for
> example,
> you need to round properly.
> This could probably be a separate block, except then
> each
> core (add/sub, mul, div) will have to provide some
> additional
> bits of the fraction. I think it would be easier for
> now
> to include that function in tot the individual cores
> as well.
> We can always later optimize and combine features.
> 
> 

1/3 = 0.333333333..... until all bits are used. in
this case no rounding is needed because you consumed
all bits but when you downconvert the extended format
(higher no. of bits) to the single format you need to
decided how to remove the extra bits (rounding) thats
why I think the rounding is done only when you convert
from higher bits to lower one. every thing else should
be done by the arithmetic operation itself
(div,mul....)


> >> 
> >> always @(posedge clk)
> >> Q <= #1 D;
> > 
> > In fact this is the most difficult part of verilog
> I
> > leanred, still I do not know what are the
> differences
> > between #1, = , and <= operators, I think they are
> > like signals and variable assignments in VHDL.
> 
> 
> You are welcome to attend my Verilog class mid
> October in Bangkok !
> 
Thanks for your explaination and invitation but could
you please tell me what is the difference from
synthesis point of view?

> >> There is no need for a reset.
> >> 

why ?

> 
> oops, forgot:
> input [1:0]        round_mode;
> 

Depends if we are going to round in the fdiv itself or
a seperate core because you duplicate it for each
execution unit in the FPU.


> > what about teh extended format you used?, in my
> code I
> > am using 32 bit for fraction and 11 bit for
> exponent
> 
> Ahm, there is no extended format. We only do single
> precision
> floating point.

I mean internal representation of the numbers

> 
> > Sorry for the VHDL like code I am still a beginner
> 
> No problem !  Look at my fmul, it's very close to
> div. It's
> also not complete, but will give you a good idea on
> to code
> in verilog.
> 
will you be updating the fmul soon?


Thanks for your help
Jamil Khatib


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