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[oc] Fw: Frequent Viewer Alert (239)



For those interested. I have no posibilities for it ! :-(

regards,  Ovidiu
-----Original Message-----
From: NetSeminar <netseminar@mail.enen.com>
To: ovilup@mail.dnttm.ro <ovilup@mail.dnttm.ro>
Date: 03 martie 2000 09:05
Subject: Frequent Viewer Alert (239)


>Dear NetSeminar Frequent Viewer,
>
>ENEN.com's Frequent Viewer Events Update is delivered to you FREE as a
registered member of the NetSeminar Frequent Viewer Network.  The Frequent
Viewer Events Update is the shortest distance between you and the
information you need to excel in the workplace.  For more information any
time, please visit our website at http://www.netseminar.com, or simply click
on one of the links below to register for that event.  Also, you can peruse
archived versions of previous events by going to http://www.netseminar.com
and clicking on the Archive button.
>
>***************************************************************************
***********************************
>HEADLINING THIS MONTH:
>
>03/08/2000, Xilinx/Synopsys NetSeminar, 9:00 AM - 10:00 AM, PST
>*TITLE:  ASIC Designers' Guide to FPGAs
>*DESCRIPTION: The advancement in capacity and speed of Xilinx FPGAs has
made them increasingly attractive to ASIC designers. As designers
investigate the feasibility of using FPGAs, a natural requirement is the
compatibility with existing design tools, such as Synopsys' Design Compiler.
Our goal is to illustrate how ASIC designers can target Xilinx Virtex-E
devices using Synopsys' FPGA Compiler II.
>*DRAWING GIVEAWAY:  Palm Pilot V
>*CLICK TO REGISTER: http://www.netseminar.com/index.cgi?sem_num=230
>
>03/14/2000, RadiSys NetSeminar, 9:00 AM - 10:00 AM, PST
>*TITLE:  Evolving VoIP Protocol Standards:  Debates from the center to the
edge of the IP network.
>*DESCRIPTION:  The adoption of IP Telephony continues to be hindered by the
lack of unified standards.  Unified standards provide interoperability
between IP Telephony components ensuring end to end operability for end
users.   As long as new standards keep evolving, fueled by the debates from
different camps, most of the IP Telephony network currently in place will be
viewed as isolated islands.   This seminar will discuss the pro's and con's
of two of these disputes, SIP vs. H.323 & MGCP vs. MEGACO.
>*DRAWING GIVEAWAY:  Palm Pilot
>*CLICK TO REGISTER: http://www.netseminar.com/index.cgi?sem_num=231
>
>03/15/2000, Synopsys NetSeminar, 10:00 AM - 11:00 AM, PST
>*TITLE:  Linux and Synopsys:  How to Solve Complex Electronic Design
Verification Challenges
>*DESCRIPTION:  With the ever increasing use of electronics in our world --
from handheld Internet devices, mobile phones, networking gear -- the effort
to address the question "will it work" is a key concern to many companies.
Design verification is the largest expense in the development cycle for new
electronic products.  Synopsys shows how its cutting edge verification
technology and Linux can be harnessed to accelerate products to market.
>*CLICK TO REGISTER: http://www.netseminar.com/index.cgi?sem_num=234
>
>03/16/2000, Cadence Design Systems NetSeminar Re-broadcasts, 10:00 AM -
11:30 AM, PST & 6:00 PM - 7:30 PM, PST
>*TITLE:  High-Speed PCB Design Demystified
>*DESCRIPTION:  As design speeds continue to increase, problems associated
with high-speed PCB design are entering the mainstream, causing designers to
seek solutions for managing these signal integrity issues. Back by popular
demand, this seminar, which originally aired on February 22, 2000, will show
you how to easily identify and resolve signal integrity issues, condense
your high-speed development cycle, and get your designs to market.
> What this Seminar Will Cover:
> * Sample front-to-back flow demonstration
> * How to identify, understand and manage signal integrity issues
> * High-speed signal integrity problems caused by switching phenomena
> * Basic techniques used to control these issues
> * Use of simulation tools to predict circuit behavior
> * How to optimize your design
> * How to integrate your physical layout and signal integrity processes
> Who Should Attend:
> * Digital Logic and PCB Designers
> * Engineers
> * Project Leads
> * Engineering Managers
>*CLICK TO REGISTER FOR THE 10:00 AM SESSION:
http://www.netseminar.com/index.cgi?sem_num=236
>*CLICK TO REGISTER FOR THE 6:00 PM SESSION:
http://www.netseminar.com/index.cgi?sem_num=237
>
>03/23/2000, Xicor NetSeminar, 10:00 AM - 11:00 AM, PST
>*CLICK TO REGISTER OR LEARN MORE:
http://www.netseminar.com/index.cgi?sem_num=238
>
>03/28/2000, QuestLink NetSeminar, 10:00 AM - 11:00 AM, PST
>*WATCH http://www.netseminar.com FOR INFORMATION UPDATES
>
>03/29/2000, Agilent NetSeminar, 9:00 AM - 10:00 AM, PST
>*CLICK TO REGISTER OR LEARN MORE:
>http://www.netseminar.com/index.cgi?sem_num=233&source=AGILENT_FVIEWER
>
>03/30/2000, LeCroy NetSeminar, 10:00 AM - 11:00 AM, PST
>*CLICK TO REGISTER OR LEARN MORE:
http://www.netseminar.com/index.cgi?sem_num=235
>
>***************************************************************************
***********************************
>APRIL'S LINE UP:
>
>04/04/2000, GemStone NetSeminar, 10:00 AM - 11:00 AM, PST
>04/25/2000, QuestLink NetSeminar, 10:00 AM - 11:00 AM, PST
>04/26/2000, RadiSys NetSeminar, 9:00 AM - 10:00 AM, PST
>04/27/2000, Agilent NetSeminar, 9:00 AM - 10:00 AM, PST
>
>***************************************************************************
***********************************
>LOOK FOR NETSEMINAR'S FROM THESE COMPANIES IN MAY!
>
>IKOS
>QuestLink
>Agilent
>
>***************************************************************************
***********************************
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