Re: [oc] Rambling thoughts, and an offer of help

["Marko Mlinar" <Marko.Mlinar@campus.fri.uni-lj.si>]

> P.S.: I don't have much time at the moment, but I will soon present my
> latest inovation -
> generalized SMT model. It is more primitive and more general than OO and
> SMT, and
> include some good things from both models.
Ok, the idea is:
SMT runs programs/threads normally and switches between them. If it
encounters
two instructions, that can be executed in parallel, it executes them so,
resources allowing.
But nitkni (it means small threads in Slovene, I will probably change name
if idea succeed)
processor actually creates two threads for two parallel instruction flows.
At first these to concept look pretty much the same, but there are some
differences:
- nitkni needs results from threads before him, this could be done similarly
to register
    renaming, so this shouldn't be a problem.
- nitkni always need only one register, and one/two from some previously
completed
    threads - instructions might be a bit shorter
- number of threads is constantly changing - could this be a problem?
- at jumps we could create two threads, and when result for conditional jump
is known,
    we can keep or kill thread
- visibility - accesibility to previous results 'far' back would be actually
accesing local registers as in
    SMT; so visibility range would be similar number of registers in RISC
arhitecture, except
    a bit effitiently used
- ...
Because execution is more general from processor point of view we don't need
so much
control circuits around ALE. Am I right?

If we also use OO computer idea, as described before, that have several
changing circuits
for basic blocks currently loaded (reprogrammed as threads need them in let
say round robin scheme).
As said earlier - if we have enough candidates for some basic block at a
time, time to execute it
converges to 1 clock cycle. Some applications which often uses same code
would benefit greatly.

Please give some feedback.

> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> SMT is first presented by Compact's WRL.
> After you present that, could you show us your slides or doc?
I'm really bad at abbreviations - what is WRL?
I meant present as present inside this mailing list ;)

> Now, SMT is competing with IA64. Who will win?
IA64 = another abbreviation :) Note that I'm SW student :)

> Another competitor, Transmeta, I think her software optimization
> ability is better than hardware VLIW!!! Maybe Transmeta's methods
> could give us a good future hint.
Software optimization cannot optimize better than compiler for VLIW.
So for x86 is Intel processor still much faster.

Yes, I agree, that probably computers will all be emulators in future,
for lets say Java...

best regards,
    Marko