Re: [bluetooth] Some time

[Puloma Mukherjee <puloma@ece.sunysb.edu>]

Hi,
I understand some one did the CRC module.Iam attaching the following
code.I feel Iam slightly wrong in initializing the registers.There is some
 mistake because of which I have to read the output from the right to
left.Please let me know ASAP.I need this to show my proffessor.
module CRC(clk,Initvalue,bitsample,blockenable,EOP,Din1,Din2,crcmatch,Dout);

input clk;
input [15:0] Initvalue;
input EOP;
input bitsample;
input blockenable;
output crcmatch;
input Din1,Din2;
output [15:0] Dout;
reg [15:0] Initialvalue;
reg [15:0] Dout;
reg temp;
reg inputbit;
integer check;
always@(Initvalue)
begin
check=check+1;
Initialvalue=Initvalue;
$display($time,"Check is %d",check);
$display($time,"Initial Value is %b",Initialvalue);
end

always @(posedge clk)

begin  
  #1;
  inputbit=bitsample;
  $display($time,"bitsample received:%b",inputbit);
  $display($time,"Inside this loop blockenable:%b,EOP=%b,Din1=%b",blockenable,EOP,Din1);
 if (blockenable==1'b1 && EOP==0 && Din1==1'b1)
     
    begin
      temp=Initialvalue[15]^inputbit;
      Initialvalue[15]<=Initialvalue[14];
      Initialvalue[14]<=Initialvalue[13];
      Initialvalue[13]<=Initialvalue[12];
      Initialvalue[12]<=Initialvalue[11]^temp;
      Initialvalue[11]<=Initialvalue[10];
      Initialvalue[10]<=Initialvalue[9];
      Initialvalue[9]<=Initialvalue[8];
      Initialvalue[8]<=Initialvalue[7];
      Initialvalue[7]<=Initialvalue[6];
      Initialvalue[6]<=Initialvalue[5];
      Initialvalue[5]<=Initialvalue[4]^temp;
      Initialvalue[4]<=Initialvalue[3];
      Initialvalue[3]<=Initialvalue[2];
      Initialvalue[2]<=Initialvalue[1];
      Initialvalue[1]<=Initialvalue[0];
      Initialvalue[0]<=temp;
      Dout=Initialvalue;
      $display("In this Iteration are %b ",Dout);
             
     end
end

endmodule


module System_Controller(clk,CRCInitvalue,CRCBlockEnable,CRCBitSample,CRCEOP,CRCDin1,CRCDin2,CRCMatch,CRCDout);

input clk;
input [15:0]CRCDout;
input CRCMatch;
output[15:0] CRCInitvalue;
output CRCBlockEnable;
output CRCBitSample; 
output CRCEOP;
output CRCDin1;
output CRCDin2;

reg CRCBlockEnable;
reg CRCBitSample;
reg CRCEOP;
reg CRCDin1;
reg CRCDin2;
reg [79:0]CRCinputdata;
reg [15:0] CRCfinaloutput;
reg [15:0] CRCInitvalue;
integer CRCcount;

initial
begin
 
  CRCfinaloutput[15:0]=16'b0000000000000000;
  CRCinputdata=80'b00001001000010000000011100000110000001010000010000000011000000100000000101001110;
  CRCInitvalue[15:0]=16'b0000000001000111;
  $display ($time,"Initial Value:%b",CRCInitvalue);
  CRCDin1=1'b1;
  CRCDin2=0;
  CRCBlockEnable=1'b1;
  CRCEOP=1'b0;
  CRCcount<=0;
end

always@(posedge clk)

begin

if (CRCcount>80)
begin
CRCEOP=1;
CRCfinaloutput=CRCDout;
$display ($time,"Output data = %b\n",CRCfinaloutput);
$finish;
end 

else

begin

CRCBitSample=CRCinputdata[CRCcount];
$display($time,"CRCBit Sample is  %b",CRCBitSample);
CRCcount=CRCcount+1; 

end

end


//initial

// begin
// $monitor($time,"Output data = %b\n",finaloutput);
// end


endmodule



module Baseband_Controller;

wire CRCbitsamplew,CRCblockenablew,CRCEOPw,CRCDin1w,CRCDin2w,crcmatchw;
wire [15:0] CRC_INITIAL_VALUEw,CRCDoutw;
reg clk;

CRC crclf (clk,CRC_INITIAL_VALUEw,CRCbitsamplew,CRCblockenablew,CRCEOPw,CRCDin1w,CRCDin2w,crcmatchw,CRCDoutw);
System_Controller sys_ctrl (clk,CRC_INITIAL_VALUEw,CRCblockenablew,CRCbitsamplew,CRCEOPw,CRCDin1w,CRCDin2w,crcmatchw,CRCDoutw);

initial
begin
clk=1'b0;
end

always
begin
#2 clk = ~clk;
$display("Clk is %b",clk);
end

//initial

//begin
//#100;
//$finish;
//end


endmodule