head 1.1; branch 1.1.1; access; symbols arelease:1.1.1.1 avendor:1.1.1; locks; strict; comment @# @; 1.1 date 2005.04.23.00.39.07; author tak.sugawara; state Exp; branches 1.1.1.1; next ; commitid 1113426998c94567; 1.1.1.1 date 2005.04.23.00.39.07; author tak.sugawara; state Exp; branches; next ; commitid 1113426998c94567; desc @@ 1.1 log @Initial revision @ text @

1.Overview

2 Deisgn
2.1 Pipeline Consideration
2.2 Component Design
2.3 Supported Instructions

3 Logic Synthesis

Benchmark Test

Analysis of Design

Post-Layout Delay Simulation

Examples of C compilation

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