head	1.1;
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comment	@# @;


1.1
date	2006.06.01.01.12.05;	author nachumk;	state Exp;
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commitid	5b5f447e3e8f4567;


desc
@@


1.1
log
@1st version.
View readme.txt to see available features and current limitations.
@
text
@#set automatic transmit and receive for uart 0
WRITE 00010000 00000011
#unmask transmit ready and receive data for uart 0
WRITE 00010100 11111100
#set automatic transmit and receive for uart 1
WRITE 00011000 00000011
#unmask transmit ready and receive data for uart 1
WRITE 00011100 11111100
#clear global 0 for interrupts for uart 0
int0shadow = 00000000
#clear global 1 for interrupts for uart 1
int1shadow = 00000000
vector8 intshadow = 00000000

WAIT 2 us

WHILE
	WAIT_INTERRUPT4
	#read interrupt reg uart 0
	READ 00010101 intshadow
	IF intshadow & 11111111
		WRITE 00010101 intshadow
	IF_END
	int0shadow |= intshadow
	#read interrupt reg uart 1
	READ 00011101 intshadow
	IF intshadow & 11111111
		WRITE 00011101 intshadow
	IF_END
	int1shadow |= intshadow
WHILE_END
@