Single-port RAM


The Single-port RAM is a small, fast, on-chip RAM implementation utilizing the embedded RAM blocks available in many FPGA architectures. Although it can be paramerized to arbitrary size and width it won't fit into a physical device if larger than a few K-bits. If you need larger memories for your design consider using an external memory chip and interfacing it to the Wishbone bus with one of the many interface circuits available. Also you can consider using another Wishbone-compatible single- and dual-ported RAM implementation by Jamil Khatib which you can find here. The core is 100% Wishbone compatible with the WishboneTK extensions. The core allows zero-wait-state operation.

Wishbone datasheet

General Description Single-port RAM
Supported cycles Slave read/write
Slave block read/write
Slave rmw
Data port size variable
Data port granularity same as port size
Data port maximum operand size same as data port size
Data transfer ordering n/a
Data transfer sequencing n/a
Supported signal list and cross reference to equivalent Wishbone signals
Signal nameWishbone equiv.
ADR_I(..) ADR_I()
DAT_I(..) DAT_I()
DAT_O(..) DAT_O()

Parameter description

Parameter nameDescription
data_widthData bus width
addr_widthAddress bus width

Signal description

Signal nameDescription
CLK_I Wishbone clock signal
CYC_I Wishbone active cycle indication signal. High value indicates an active Wishbone cycle on the bus
STB_I Wishbone strobe signal. High value indicates cycle to this particular device
WE_I Wishbone write enable signal. High indicates data flowing from master to slave
ACK_O Wishbone acknowledge signal. High indicates that slave finished operation sucessfully
ACK_OI WhisboneTK acknowledge chain input signal
ADR_I(addr_width-1..0) Wishbone address bus signals
DAT_I(data_width-1..0) Wishbone data bus input (to slave direction) signals
DAT_O(data_width-1..0) Wishbone data bus output (to master direction) signals
DAT_OI(data_width-1..0) WhisboneTK data bus chain input signal

Author & Maintainer

Andras Tantos