Asyncronous slave interface


Asyncronous (SRAM-like) slave interface is a simple parametrized bus converter. It acts as a slave device for a Wishbone bus master device and converts cycles on the wishbone bus to asyncronous access cycles, very similar to SRAM access cycles. That type of bus interface is very common between slow to middle speed peripherial chips available on the market. With this core it is possible to use those peripherials from a Wishbone master device. It is also possible to drive high-speed SRAM devices and use them as off-core memory. The core is 100% Wishbone compatible with the WishboneTK extensions. The address and data bus-width can be configured through compile-time parameters. The speed of the external device can be set using input signals. A deactivation cycle is inserted after each access to the core thus the maximum access speed is half of the speed of the Whisbone bus. Becouse deactivation cycle is completed after the finish of the access cycle if the next access on the Whisbone bus is to another device zero wait-state operation can be achieved.

Wishbone datasheet

General Description Asyncronous (SRAM-like) slave interface
Supported cycles Slave read/write
Slave block read/write
Slave rmw
Data port size variable
Data port granularity 8-bit
Data port maximum operand size same as data port size
Data transfer ordering n/a
Data transfer sequencing n/a
Supported signal list and cross reference to equivalent Wishbone signals
Signal nameWishbone equiv.
SEL_I(..) SEL_I()
ADR_I(..) ADR_I()
DAT_I(..) DAT_I()
DAT_O(..) DAT_O()

Parameter description

Parameter nameDescription
widthData bus width
addr_widthAddress bus width

Signal description

Signal nameDescription
WAIT_STATE(3..0)Number of wait-states to generate. 0 means 1 access and one deactivation cycle, no wait-states.
CLK_I Wishbone clock signal
RST_I Wishbone reset signal
STB_I Wishbone strobe signal. High value indicates cycle to this particular device
WE_I Wishbone write enable signal. High indicates data flowing from master to slave
ACK_O Wishbone acknowledge signal. High indicates that slave finished operation sucessfully
ACK_OI WhisboneTK acknowledge chain input signal
ADR_I(addr_width-1..0) Wishbone address bus signals
DAT_I(width-1..0) Wishbone data bus input (to slave direction) signals
DAT_O(width-1..0) Wishbone data bus output (to master direction) signals
DAT_OI(width-1..0) WhisboneTK data bus chain input signal
SEL_I(addr_width/8-1..0) Wishbone byte-selection signals
Aysncronous interfce signals
A_DATA(width-1..0)Bidirectional data bus signals
A_ADDR(addr_width-1..0)Address bus output signals
A_RDNActive low read signal
A_WRNActive low write signal
A_CENActive low chip-select signal
A_BYEN(addr_width/8-1..0)Active-low byte-enable signals

Author & Maintainer

Andras Tantos