D-Flip Flop structural file generated from D-Flip Flop Behvioural File
-- VHDL structural
description generated from `dffres`
--
date : Thu Dec 7 16:20:50
2000
-- Entity
Declaration
ENTITY dffres IS
PORT (
input : in BIT;
-- input
clk : in BIT;
-- clk
reset : in BIT;
-- reset
output : out BIT; --
output
vdd : in BIT;
-- vdd
vss : in BIT
-- vss
);
END dffres;
-- Architecture
Declaration
ARCHITECTURE VST OF
dffres IS
COMPONENT ndrvp_y
port (
i : in BIT;
-- i
f : out BIT;
-- f
vdd : in BIT;
-- vdd
vss : in BIT
-- vss
);
END COMPONENT;
COMPONENT o2_y
port (
i0 : in BIT;
-- i0
i1 : in BIT;
-- i1
t : out BIT;
-- t
vdd : in BIT;
-- vdd
vss : in BIT
-- vss
);
END COMPONENT;
COMPONENT no2_y
port (
i0 : in BIT;
-- i0
i1 : in BIT;
-- i1
f : out BIT;
-- f
vdd : in BIT;
-- vdd
vss : in BIT
-- vss
);
END COMPONENT;
COMPONENT msdp2_y
port (
di : in BIT;
-- di
ck : in BIT;
-- ck
t : out BIT;
-- t
vdd : in BIT;
-- vdd
vss : in BIT
-- vss
);
END COMPONENT;
SIGNAL auxsc3 : BIT;
-- auxsc3
SIGNAL auxsc4 : BIT;
-- auxsc4
SIGNAL auxsc5 : BIT;
-- auxsc5
SIGNAL auxreg1 : BIT;
-- auxreg1
BEGIN
output : ndrvp_y
PORT MAP (
vss => vss,
vdd => vdd,
f => output,
i => auxreg1);
auxsc5 : ndrvp_y
PORT MAP (
vss => vss,
vdd => vdd,
f => auxsc5,
i => clk);
auxsc4 : o2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => auxsc4,
i1 => auxsc3,
i0 => reset);
auxsc3 : no2_y
PORT MAP (
vss => vss,
vdd => vdd,
f => auxsc3,
i1 => input,
i0 => reset);
dffres_reg : msdp2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => auxreg1,
ck => auxsc5,
di => auxsc4);
end VST;