Project Name: FIR Filter core
Specifications
- as much as 256 TAPs in Xilinx Virtex/Spartan2 (per cascade unit)
- low gate count (on expense of lower input sample frequency range) with a single MAC unit per core and sequential calculation of output samples (TAPs don't operate in parallel)
- 2 to 256 TAPs range set by a user
- 16 bit or less input sample width set by a user
- 16 bit or less coefficient width set by a user
- simple design that allows cascading several FIR filter cores (external adder required)
Description
FIR, or Finite Impulse Response, filters have the distinctive trait that their impulse response lasts for a finite duration of time as opposed to IIR, or Infinite Impulse Response, filters whose impulse response is infinite in duration.
Typical block diagram of a TAP unit in typical FIR filters
Currently FIR filter core uses two dual-port memories for accessing input samples (first circular FIFO) and coefficients (second circular FIFO). It takes NUM_TAPS+1 to compute new output sample. Supported DP memory is of Xilinx Virtex/Spartan2 FPGAs. Also a generic DP memory is provided (it synthesizes into flip-flops).
Block diagram of our "sequential" FIR filter core
Synthesis
- Synthesized with Xilinx Foundation 2.1i (Synopsys Express FPGA compiler, Xilinx P&R tools) for Xilinx Virtex -6 FPGA design takes 229 Virtex slices and 2 BlockRAMs and operates at 55MHz (12 TAPs, 16 bit coefficients and input samples, +-2.29 input sample frequency).
Current Status:
- design is available in VHDL from OpenCores CVS via
cvsweb or via
cvsget (use fir for module name)
- documentation will be written if enough interest (or if there will be
a volunteer to do this)
- also see TO DO list in design's VHDL sources
Author & Maintainer:
Mailing list: