Description
Different encryption algorithms (such as RSA) require the modular exponentiation calculation. Large word sizes are applied (word sizes could reach 1024 or 2048 bits for more security). Many algorithms have been used to implement a hardware block that can calculate modular exponentiation. One of the best is Montgomery’s modular exponentiation algorithm. The algorithm is particularly suitable for implementation on general-purpose computers (DSPs or microprocessors), that are capable of performing fast arithmetic modulo a power of 2.
Our modular exponentiation core will be released in a parametrizable form, where the user chooses the word processing size. The core is designed to operate at high clock frequencies (on different technologies) for processing large bit-rates. Large word size additions and subtractions delays are reduced by carry save logic. For more information about modular exponentiation please check here
Current Status
We have implemented a 16-bit version of our core with applying carry save logic, the algorithm was functionally verified before and after synthesis. The 16-bit version occupied 8500 to 10000 gates using Xilinx XC4000E family FPGAs (according to different synthesis options; time/area optimization). Timing simulation showed the core operating at a maximum speed of 8 MHz (for 8500 gates) and 15.6 MHz (for 10000 gates). The core could be found at Mentor Graphics Student HDL Contest results (Third Prize) and you can find some similar cores as well.
References
Maintainers and Authors