Specifications

• Should be compatible with Motorola's MC6845 CRT controller

Description

The CRTC6845 Cathode Ray Tube Controller interfaces a microprocessor to a raster scan CRT display. The microprocessor can access 19 registers that in turn work with the CRT Controller control logic to generate:

• display timing signals (HSYNC, VSYNC and DE)
• memory addresses (14-bit refresh Memory Address and 5-bit Row Address)
• a cursor output (a single signal CURSOR)
• light pen strobe input for detecting light pen position (a single signal LPSTBn)

The CRTC6845 is used as a central part of CGA/MGA cards. It can be programmed to drive alphanumeric, semi-graphic, and full bit-mapped graphic displays. Programmable alphanumeric screen formats (80x25, 132x20 or any other custom format). With a combination of 14-bit refresh Memory Address and 5-bit Row Address you can form a 512K bit-mapped graphic system. Controller allows hardware scroll by page, by line or by character.

Currently CRTC6845 does not support interlace mode and it does not extend VSYNC for R5 value (Vertical Total Adjust).

Synthesis

• Synthesized with Xilinx Foundation 2.1i (Synopsys Express FPGA compiler, Xilinx P&R tools) for Xilinx Virtex -6 FPGA design takes 209 Virtex slices and operates at 50MHz character clock (not pixel clock).

Current Status:

• design is available in VHDL from OpenCores CVS via cvsweb or via cvsget (use crtc6845 for module name)
• as design documentation use MC6845 data sheet
• also see TO DO list in design's VHDL sources

Author & Maintainer:

Damjan Lampret

cores@opencores.org_NOSPAM