diff -Nrcpad gcc-4.8.2/ChangeLog gcc-4.8.3/ChangeLog *** gcc-4.8.2/ChangeLog Wed Oct 16 07:18:46 2013 --- gcc-4.8.3/ChangeLog Thu May 22 09:07:11 2014 *************** *** 1,3 **** --- 1,25 ---- + 2014-05-22 Release Manager + + * GCC 4.8.3 released. + + 2014-04-04 Bill Schmidt + + Backport from mainline + 2013-11-15 Ulrich Weigand + + * libtool.m4: Update to mainline version. + * configure: Regenerate. + + 2014-04-04 Bill Schmidt + + Backport from mainline r203071: + + 2013-10-01 Joern Rennecke + + Import from savannah.gnu.org: + * config.guess: Update to 2013-06-10 version. + * config.sub: Update to 2013-10-01 version. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff -Nrcpad gcc-4.8.2/INSTALL/binaries.html gcc-4.8.3/INSTALL/binaries.html *** gcc-4.8.2/INSTALL/binaries.html Wed Oct 16 07:28:04 2013 --- gcc-4.8.3/INSTALL/binaries.html Thu May 22 09:13:50 2014 *************** *** 1,168 **** ! ! ! ! ! ! Installing GCC ! ! ! ! ! ! ! ! ! ! ! ! !

Installing GCC

! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

We are often asked about pre-compiled versions of GCC. While we cannot ! provide these for all platforms, below you’ll find links to binaries for various platforms where creating them by yourself is not easy due to various reasons. !

!

Please note that we did not create these binaries, nor do we support them. If you have any problems installing them, please contact their makers. -

- ! !
!

Return to the GCC Installation page !

! ! ! ! - - --- 1,115 ---- ! ! ! Installing GCC: Binaries ! ! ! ! ! ! ! ! ! !

Installing GCC: Binaries

! ! We are often asked about pre-compiled versions of GCC. While we cannot ! provide these for all platforms, below you'll find links to binaries for various platforms where creating them by yourself is not easy due to various reasons. ! !

Please note that we did not create these binaries, nor do we support them. If you have any problems installing them, please contact their makers. !

+

+

Return to the GCC Installation page + + + + + + diff -Nrcpad gcc-4.8.2/INSTALL/build.html gcc-4.8.3/INSTALL/build.html *** gcc-4.8.2/INSTALL/build.html Wed Oct 16 07:28:03 2013 --- gcc-4.8.3/INSTALL/build.html Thu May 22 09:13:50 2014 *************** *** 1,458 **** ! ! ! ! ! ! Installing GCC ! ! ! ! ! ! ! ! ! ! ! ! !

Installing GCC

! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

Now that GCC is configured, you are ready to build the compiler and runtime libraries. !

!

Some commands executed when making the compiler may fail (return a ! nonzero status) and be ignored by make. These failures, which are often due to files that were not found, are expected, and can safely be ignored. !

!

It is normal to have compiler warnings when compiling certain files. Unless you are a GCC developer, you can generally ignore these warnings unless they cause compilation to fail. Developers should attempt to fix any warnings encountered, however they can temporarily continue past warnings-as-errors by specifying the configure flag ! --disable-werror. !

!

On certain old systems, defining certain environment variables such as ! CC can interfere with the functioning of make. !

!

If you encounter seemingly strange errors when trying to build the compiler in a directory other than the source directory, it could be because you have previously configured the compiler in the source directory. Make sure you have done all the necessary preparations. !

!

If you build GCC on a BSD system using a directory stored in an old System ! V file system, problems may occur in running fixincludes if the ! System V file system doesn’t support symbolic links. These problems result in a failure to fix the declaration of size_t in ! sys/types.h. If you find that size_t is a signed type and that type mismatches occur, this could be the cause. !

!

The solution is not to use such a directory for building GCC. !

!

Similarly, when building from SVN or snapshots, or if you modify ! *.l files, you need the Flex lexical analyzer generator ! installed. If you do not modify *.l files, releases contain the Flex-generated files and you do not need Flex installed to build them. There is still one Flex-based lexical analyzer (part of the build machinery, not of GCC itself) that is used even if you only build the C front end. !

!

When building from SVN or snapshots, or if you modify Texinfo documentation, you need version 4.7 or later of Texinfo installed if you want Info documentation to be regenerated. Releases contain Info documentation pre-built for the unmodified documentation in the release. !

! !

Building a native compiler

For a native build, the default configuration is to perform ! a 3-stage bootstrap of the compiler when ‘make’ is invoked. This will build the entire GCC system and ensure that it compiles ! itself correctly. It can be disabled with the --disable-bootstrap ! parameter to ‘configure’, but bootstrapping is suggested because the compiler will be tested more completely and could also have better performance. -

-

The bootstrapping process will complete the following steps: -

-
    -
  • Build tools necessary to build the compiler. !
  • Perform a 3-stage bootstrap of the compiler. This includes building three times the target tools for use by the compiler such as binutils (bfd, binutils, gas, gprof, ld, and opcodes) if they have been individually linked or moved into the top level GCC source tree before configuring. !
  • Perform a comparison test of the stage2 and stage3 compilers. !
  • Build runtime libraries using the stage3 compiler from the previous step. !
!

If you are short on disk space you might consider ‘make ! bootstrap-lean’ instead. The sequence of compilation is the same described above, but object files from the stage1 and stage2 of the 3-stage bootstrap of the compiler are deleted as soon as they are no longer needed. !

!

If you wish to use non-default GCC flags when compiling the stage2 and stage3 compilers, set BOOT_CFLAGS on the command line when ! doing ‘make’. For example, if you want to save additional space during the bootstrap and in the final installation as well, you can build the compiler binaries without debugging information as in the following example. This will save roughly 40% of disk space both for the bootstrap and the final installation. (Libraries will still contain debugging information.) -

-
- 
make BOOT_CFLAGS='-O' bootstrap
-
!

You can place non-default optimization flags into BOOT_CFLAGS; they ! are less well tested here than the default of ‘-g -O2’, but should still work. In a few cases, you may find that you need to specify special ! flags such as -msoft-float here to complete the bootstrap; or, if the native compiler miscompiles the stage1 compiler, you may need to work around this, by choosing BOOT_CFLAGS to avoid the parts ! of the stage1 compiler that were miscompiled, or by using ‘make ! bootstrap4’ to increase the number of stages of bootstrap. !

!

BOOT_CFLAGS does not apply to bootstrapped target libraries. Since these are always compiled with the compiler currently being bootstrapped, you can use CFLAGS_FOR_TARGET to modify their ! compilation flags, as for non-bootstrapped target libraries. Again, if the native compiler miscompiles the stage1 compiler, you may need to work around this by avoiding non-working parts of the stage1 compiler. Use STAGE1_TFLAGS to this end. !

!

If you used the flag --enable-languages=… to restrict ! the compilers to be built, only those you’ve actually enabled will be built. This will of course only build those runtime libraries, for which the particular compiler has been built. Please note, ! that re-defining LANGUAGES when calling ‘make’ does not work anymore! !

!

If the comparison of stage2 and stage3 fails, this normally indicates that the stage2 compiler has compiled GCC incorrectly, and is therefore a potentially serious bug which you should investigate and report. (On a few systems, meaningful comparison of object files is impossible; they always appear “different”. If you encounter this problem, you will ! need to disable comparison in the Makefile.) !

!

If you do not want to bootstrap your compiler, you can configure with ! --disable-bootstrap. In particular cases, you may want to bootstrap your compiler even if the target system is not the same as the one you are building on: for example, you could build a powerpc-unknown-linux-gnu toolchain on a powerpc64-unknown-linux-gnu host. In this case, pass ! --enable-bootstrap to the configure script. !

!

BUILD_CONFIG can be used to bring in additional customization ! to the build. It can be set to a whitespace-separated list of names. ! For each such NAME, top-level config/NAME.mk will ! be included by the top-level Makefile, bringing in any settings it contains. The default BUILD_CONFIG can be set using the ! configure option --with-build-config=NAME.... Some examples of supported build configurations are: !

!
!
‘bootstrap-O1’
!

Removes any -O-started option from BOOT_CFLAGS, and adds ! -O1 to it. ‘BUILD_CONFIG=bootstrap-O1’ is equivalent to ! ‘BOOT_CFLAGS='-g -O1'’. !

!
!
‘bootstrap-O3’
!

Analogous to bootstrap-O1. !

!
!
‘bootstrap-lto’
!

Enables Link-Time Optimization for host tools during bootstrapping. ! ‘BUILD_CONFIG=bootstrap-lto’ is equivalent to adding ! -flto to ‘BOOT_CFLAGS’. !

!
!
‘bootstrap-debug’
!

Verifies that the compiler generates the same executable code, whether or not it is asked to emit debug information. To this end, this option builds stage2 host programs without debug information, and uses ! contrib/compare-debug to compare them with the stripped stage3 object files. If BOOT_CFLAGS is overridden so as to not enable ! debug information, stage2 will have it, and stage3 won’t. This option is enabled by default when GCC bootstrapping is enabled, if strip can turn object files compiled with and without debug info into identical object files. In addition to better test coverage, this option makes default bootstraps faster and leaner. !

!
!
‘bootstrap-debug-big’
!

Rather than comparing stripped object files, as in bootstrap-debug, this option saves internal compiler dumps during stage2 and stage3 and compares them as well, which helps catch additional potential problems, but at a great cost in terms of disk ! space. It can be specified in addition to ‘bootstrap-debug’. !

!
!
‘bootstrap-debug-lean’
!

This option saves disk space compared with bootstrap-debug-big, but at the expense of some recompilation. Instead of saving the dumps of stage2 and stage3 until the final compare, it uses ! -fcompare-debug to generate, compare and remove the dumps during stage3, repeating the compilation that already took place in stage2, whose dumps were not saved. !

!
!
‘bootstrap-debug-lib’
!

This option tests executable code invariance over debug information generation on target libraries, just like bootstrap-debug-lean tests it on host programs. It builds stage3 libraries with ! -fcompare-debug, and it can be used along with any of the bootstrap-debug options above. !

!

There aren’t -lean or -big counterparts to this option because most libraries are only build in stage3, so bootstrap compares would not get significant coverage. Moreover, the few libraries built ! in stage2 are used in stage3 host programs, so we wouldn’t want to compile stage2 libraries with different options for comparison purposes. !

!
!
‘bootstrap-debug-ckovw’
!

Arranges for error messages to be issued if the compiler built on any ! stage is run without the option -fcompare-debug. This is ! useful to verify the full -fcompare-debug testing coverage. It must be used along with bootstrap-debug-lean and bootstrap-debug-lib. !

!
!
‘bootstrap-time’
!

Arranges for the run time of each program started by the GCC driver, ! built in any stage, to be logged to time.log, in the top level of the build tree. -

-
-
! !

Building a cross compiler

When building a cross compiler, it is not generally possible to do a 3-stage bootstrap of the compiler. This makes for an interesting problem as parts of GCC can only be built with GCC. !

!

To build a cross compiler, we recommend first building and installing a native compiler. You can then use the native GCC compiler to build the cross compiler. The installed native compiler needs to be GCC version 2.95 or later. !

!

If the cross compiler is to be built with support for the Java programming language and the ability to compile .java source files is desired, the installed native compiler used to build the cross compiler needs to be the same GCC version as the cross compiler. In addition the cross compiler needs to be configured with ! --with-ecj-jar=…. !

!

Assuming you have already installed a native copy of GCC and configured ! your cross compiler, issue the command make, which performs the following steps: -

-
    -
  • Build host tools necessary to build the compiler. !
  • Build target tools for use by the compiler such as binutils (bfd, binutils, gas, gprof, ld, and opcodes) if they have been individually linked or moved into the top level GCC source tree before configuring. !
  • Build the compiler (single stage only). !
  • Build runtime libraries using the compiler from the previous step. !
!

Note that if an error occurs in any step the make process will exit. !

!

If you are not building GNU binutils in the same source tree as GCC, you will need a cross-assembler and cross-linker installed before configuring GCC. Put them in the directory ! prefix/target/bin. Here is a table of the tools you should put in this directory: !

!
!
as
!

This should be the cross-assembler. !

!
!
ld
!

This should be the cross-linker. !

!
!
ar
!

This should be the cross-archiver: a program which can manipulate ! archive files (linker libraries) in the target machine’s format. !

!
!
ranlib
!

This should be a program to construct a symbol table in an archive file. !

!

The installation of GCC will find these programs in that directory, and copy or link them to the proper place to for the cross-compiler to find them when run later. !

!

The easiest way to provide these files is to build the Binutils package. ! Configure it with the same --host and --target options that you use for configuring GCC, then build and install them. They install their executables automatically into the proper directory. Alas, they do not support all the targets that GCC supports. !

!

If you are not building a C library in the same source tree as GCC, you should also provide the target libraries and headers before configuring GCC, specifying the directories with ! --with-sysroot or --with-headers and ! --with-libs. Many targets also require “start files” such ! as crt0.o and ! crtn.o which are linked into each executable. There may be several ! alternatives for crt0.o, for use with profiling or other ! compilation options. Check your target’s definition of STARTFILE_SPEC to find out what start files it uses. !

! !

Building in parallel

GNU Make 3.80 and above, which is necessary to build GCC, support ! building in parallel. To activate this, you can use ‘make -j 2’ ! instead of ‘make’. You can also specify a bigger number, and in most cases using a value greater than the number of processors in your machine will result in fewer and shorter I/O latency hits, thus improving overall throughput; this is especially true for slow drives and network filesystems. !

! !

Building the Ada compiler

In order to build GNAT, the Ada compiler, you need a working GNAT ! compiler (GCC version 4.0 or later). ! This includes GNAT tools such as gnatmake and ! gnatlink, since the Ada front end is written in Ada and uses some GNAT-specific extensions. !

!

In order to build a cross compiler, it is suggested to install the new compiler as native first, and then use it to build the cross compiler. !

!

configure does not test whether the GNAT installation works and has a sufficiently recent version; if too old a GNAT version is ! installed, the build will fail unless --enable-languages is used to disable building the Ada front end. !

!

ADA_INCLUDE_PATH and ADA_OBJECT_PATH environment variables must not be set when building the Ada compiler, the Ada tools, or the Ada runtime libraries. You can check that your build environment is clean ! by verifying that ‘gnatls -v’ lists only one explicit path in each section. !

! !

Building with profile feedback

It is possible to use profile feedback to optimize the compiler itself. This should result in a faster compiler binary. Experiments done on x86 using gcc 3.3 showed approximately 7 percent speedup on compiling C programs. To bootstrap the compiler with profile feedback, use make profiledbootstrap. !

!

When ‘make profiledbootstrap’ is run, it will first build a stage1 compiler. This compiler is used to build a stageprofile compiler instrumented to collect execution counts of instruction and branch ! probabilities. Then runtime libraries are compiled with profile collected. Finally a stagefeedback compiler is built using the information collected. !

!

Unlike standard bootstrap, several additional restrictions apply. The ! compiler used to build stage1 needs to support a 64-bit integral type. It is recommended to only use GCC for this. Also parallel make is currently not supported since collisions in profile collecting may occur. -

-
-

Return to the GCC Installation page -

- - - - - - - -
- - --- 1,378 ---- ! ! ! Installing GCC: Building ! ! ! ! ! ! ! ! ! !

Installing GCC: Building

! ! Now that GCC is configured, you are ready to build the compiler and runtime libraries. ! !

Some commands executed when making the compiler may fail (return a ! nonzero status) and be ignored by make. These failures, which are often due to files that were not found, are expected, and can safely be ignored. ! !

It is normal to have compiler warnings when compiling certain files. Unless you are a GCC developer, you can generally ignore these warnings unless they cause compilation to fail. Developers should attempt to fix any warnings encountered, however they can temporarily continue past warnings-as-errors by specifying the configure flag ! --disable-werror. ! !

On certain old systems, defining certain environment variables such as ! CC can interfere with the functioning of make. ! !

If you encounter seemingly strange errors when trying to build the compiler in a directory other than the source directory, it could be because you have previously configured the compiler in the source directory. Make sure you have done all the necessary preparations. ! !

If you build GCC on a BSD system using a directory stored in an old System ! V file system, problems may occur in running fixincludes if the ! System V file system doesn't support symbolic links. These problems result in a failure to fix the declaration of size_t in ! sys/types.h. If you find that size_t is a signed type and that type mismatches occur, this could be the cause. ! !

The solution is not to use such a directory for building GCC. ! !

Similarly, when building from SVN or snapshots, or if you modify ! *.l files, you need the Flex lexical analyzer generator ! installed. If you do not modify *.l files, releases contain the Flex-generated files and you do not need Flex installed to build them. There is still one Flex-based lexical analyzer (part of the build machinery, not of GCC itself) that is used even if you only build the C front end. ! !

When building from SVN or snapshots, or if you modify Texinfo documentation, you need version 4.7 or later of Texinfo installed if you want Info documentation to be regenerated. Releases contain Info documentation pre-built for the unmodified documentation in the release. ! !

Building a native compiler

For a native build, the default configuration is to perform ! a 3-stage bootstrap of the compiler when ‘make’ is invoked. This will build the entire GCC system and ensure that it compiles ! itself correctly. It can be disabled with the --disable-bootstrap ! parameter to ‘configure’, but bootstrapping is suggested because the compiler will be tested more completely and could also have better performance. !

The bootstrapping process will complete the following steps: ! !

    !
  • Build tools necessary to build the compiler. ! !
  • Perform a 3-stage bootstrap of the compiler. This includes building three times the target tools for use by the compiler such as binutils (bfd, binutils, gas, gprof, ld, and opcodes) if they have been individually linked or moved into the top level GCC source tree before configuring. !
  • Perform a comparison test of the stage2 and stage3 compilers. !
  • Build runtime libraries using the stage3 compiler from the previous step. !
!

If you are short on disk space you might consider ‘make ! bootstrap-lean’ instead. The sequence of compilation is the same described above, but object files from the stage1 and stage2 of the 3-stage bootstrap of the compiler are deleted as soon as they are no longer needed. ! !

If you wish to use non-default GCC flags when compiling the stage2 and stage3 compilers, set BOOT_CFLAGS on the command line when ! doing ‘make’. For example, if you want to save additional space during the bootstrap and in the final installation as well, you can build the compiler binaries without debugging information as in the following example. This will save roughly 40% of disk space both for the bootstrap and the final installation. (Libraries will still contain debugging information.) ! 

     make BOOT_CFLAGS='-O' bootstrap
!
!

You can place non-default optimization flags into BOOT_CFLAGS; they ! are less well tested here than the default of ‘-g -O2’, but should still work. In a few cases, you may find that you need to specify special ! flags such as -msoft-float here to complete the bootstrap; or, if the native compiler miscompiles the stage1 compiler, you may need to work around this, by choosing BOOT_CFLAGS to avoid the parts ! of the stage1 compiler that were miscompiled, or by using ‘make ! bootstrap4’ to increase the number of stages of bootstrap. ! !

BOOT_CFLAGS does not apply to bootstrapped target libraries. Since these are always compiled with the compiler currently being bootstrapped, you can use CFLAGS_FOR_TARGET to modify their ! compilation flags, as for non-bootstrapped target libraries. Again, if the native compiler miscompiles the stage1 compiler, you may need to work around this by avoiding non-working parts of the stage1 compiler. Use STAGE1_TFLAGS to this end. ! !

If you used the flag --enable-languages=... to restrict ! the compilers to be built, only those you've actually enabled will be built. This will of course only build those runtime libraries, for which the particular compiler has been built. Please note, ! that re-defining LANGUAGES when calling ‘make’ does not work anymore! ! !

If the comparison of stage2 and stage3 fails, this normally indicates that the stage2 compiler has compiled GCC incorrectly, and is therefore a potentially serious bug which you should investigate and report. (On a few systems, meaningful comparison of object files is impossible; they always appear “different”. If you encounter this problem, you will ! need to disable comparison in the Makefile.) ! !

If you do not want to bootstrap your compiler, you can configure with ! --disable-bootstrap. In particular cases, you may want to bootstrap your compiler even if the target system is not the same as the one you are building on: for example, you could build a powerpc-unknown-linux-gnu toolchain on a powerpc64-unknown-linux-gnu host. In this case, pass ! --enable-bootstrap to the configure script. ! !

BUILD_CONFIG can be used to bring in additional customization ! to the build. It can be set to a whitespace-separated list of names. ! For each such NAME, top-level config/NAME.mk will ! be included by the top-level Makefile, bringing in any settings it contains. The default BUILD_CONFIG can be set using the ! configure option --with-build-config=NAME.... Some examples of supported build configurations are: ! !

!
‘bootstrap-O1’
Removes any -O-started option from BOOT_CFLAGS, and adds ! -O1 to it. ‘BUILD_CONFIG=bootstrap-O1’ is equivalent to ! ‘BOOT_CFLAGS='-g -O1'’. ! !
‘bootstrap-O3’
Analogous to bootstrap-O1. ! !
‘bootstrap-lto’
Enables Link-Time Optimization for host tools during bootstrapping. ! ‘BUILD_CONFIG=bootstrap-lto’ is equivalent to adding ! -flto to ‘BOOT_CFLAGS’. ! !
‘bootstrap-debug’
Verifies that the compiler generates the same executable code, whether or not it is asked to emit debug information. To this end, this option builds stage2 host programs without debug information, and uses ! contrib/compare-debug to compare them with the stripped stage3 object files. If BOOT_CFLAGS is overridden so as to not enable ! debug information, stage2 will have it, and stage3 won't. This option is enabled by default when GCC bootstrapping is enabled, if strip can turn object files compiled with and without debug info into identical object files. In addition to better test coverage, this option makes default bootstraps faster and leaner. ! !
‘bootstrap-debug-big’
Rather than comparing stripped object files, as in bootstrap-debug, this option saves internal compiler dumps during stage2 and stage3 and compares them as well, which helps catch additional potential problems, but at a great cost in terms of disk ! space. It can be specified in addition to ‘bootstrap-debug’. ! !
‘bootstrap-debug-lean’
This option saves disk space compared with bootstrap-debug-big, but at the expense of some recompilation. Instead of saving the dumps of stage2 and stage3 until the final compare, it uses ! -fcompare-debug to generate, compare and remove the dumps during stage3, repeating the compilation that already took place in stage2, whose dumps were not saved. ! !
‘bootstrap-debug-lib’
This option tests executable code invariance over debug information generation on target libraries, just like bootstrap-debug-lean tests it on host programs. It builds stage3 libraries with ! -fcompare-debug, and it can be used along with any of the bootstrap-debug options above. ! !

There aren't -lean or -big counterparts to this option because most libraries are only build in stage3, so bootstrap compares would not get significant coverage. Moreover, the few libraries built ! in stage2 are used in stage3 host programs, so we wouldn't want to compile stage2 libraries with different options for comparison purposes. ! !

‘bootstrap-debug-ckovw’
Arranges for error messages to be issued if the compiler built on any ! stage is run without the option -fcompare-debug. This is ! useful to verify the full -fcompare-debug testing coverage. It must be used along with bootstrap-debug-lean and bootstrap-debug-lib. ! !
‘bootstrap-time’
Arranges for the run time of each program started by the GCC driver, ! built in any stage, to be logged to time.log, in the top level of the build tree. !
! !

Building a cross compiler

When building a cross compiler, it is not generally possible to do a 3-stage bootstrap of the compiler. This makes for an interesting problem as parts of GCC can only be built with GCC. ! !

To build a cross compiler, we recommend first building and installing a native compiler. You can then use the native GCC compiler to build the cross compiler. The installed native compiler needs to be GCC version 2.95 or later. ! !

If the cross compiler is to be built with support for the Java programming language and the ability to compile .java source files is desired, the installed native compiler used to build the cross compiler needs to be the same GCC version as the cross compiler. In addition the cross compiler needs to be configured with ! --with-ecj-jar=.... ! !

Assuming you have already installed a native copy of GCC and configured ! your cross compiler, issue the command make, which performs the following steps: !

    !
  • Build host tools necessary to build the compiler. ! !
  • Build target tools for use by the compiler such as binutils (bfd, binutils, gas, gprof, ld, and opcodes) if they have been individually linked or moved into the top level GCC source tree before configuring. !
  • Build the compiler (single stage only). !
  • Build runtime libraries using the compiler from the previous step. !
!

Note that if an error occurs in any step the make process will exit. ! !

If you are not building GNU binutils in the same source tree as GCC, you will need a cross-assembler and cross-linker installed before configuring GCC. Put them in the directory ! prefix/target/bin. Here is a table of the tools you should put in this directory: ! !

!
as
This should be the cross-assembler. ! !
ld
This should be the cross-linker. ! !
ar
This should be the cross-archiver: a program which can manipulate ! archive files (linker libraries) in the target machine's format. ! !
ranlib
This should be a program to construct a symbol table in an archive file.
!

The installation of GCC will find these programs in that directory, and copy or link them to the proper place to for the cross-compiler to find them when run later. ! !

The easiest way to provide these files is to build the Binutils package. ! Configure it with the same --host and --target options that you use for configuring GCC, then build and install them. They install their executables automatically into the proper directory. Alas, they do not support all the targets that GCC supports. ! !

If you are not building a C library in the same source tree as GCC, you should also provide the target libraries and headers before configuring GCC, specifying the directories with ! --with-sysroot or --with-headers and ! --with-libs. Many targets also require “start files” such ! as crt0.o and ! crtn.o which are linked into each executable. There may be several ! alternatives for crt0.o, for use with profiling or other ! compilation options. Check your target's definition of STARTFILE_SPEC to find out what start files it uses. ! !

Building in parallel

GNU Make 3.80 and above, which is necessary to build GCC, support ! building in parallel. To activate this, you can use ‘make -j 2’ ! instead of ‘make’. You can also specify a bigger number, and in most cases using a value greater than the number of processors in your machine will result in fewer and shorter I/O latency hits, thus improving overall throughput; this is especially true for slow drives and network filesystems. ! !

Building the Ada compiler

In order to build GNAT, the Ada compiler, you need a working GNAT ! compiler (GCC version 4.0 or later). ! This includes GNAT tools such as gnatmake and ! gnatlink, since the Ada front end is written in Ada and uses some GNAT-specific extensions. ! !

In order to build a cross compiler, it is suggested to install the new compiler as native first, and then use it to build the cross compiler. ! !

configure does not test whether the GNAT installation works and has a sufficiently recent version; if too old a GNAT version is ! installed, the build will fail unless --enable-languages is used to disable building the Ada front end. ! !

ADA_INCLUDE_PATH and ADA_OBJECT_PATH environment variables must not be set when building the Ada compiler, the Ada tools, or the Ada runtime libraries. You can check that your build environment is clean ! by verifying that ‘gnatls -v’ lists only one explicit path in each section. ! !

Building with profile feedback

It is possible to use profile feedback to optimize the compiler itself. This should result in a faster compiler binary. Experiments done on x86 using gcc 3.3 showed approximately 7 percent speedup on compiling C programs. To bootstrap the compiler with profile feedback, use make profiledbootstrap. ! !

When ‘make profiledbootstrap’ is run, it will first build a stage1 compiler. This compiler is used to build a stageprofile compiler instrumented to collect execution counts of instruction and branch ! probabilities. Then runtime libraries are compiled with profile collected. Finally a stagefeedback compiler is built using the information collected. ! !

Unlike standard bootstrap, several additional restrictions apply. The ! compiler used to build stage1 needs to support a 64-bit integral type. It is recommended to only use GCC for this. Also parallel make is currently not supported since collisions in profile collecting may occur. +

+

Return to the GCC Installation page + + + + + + + + + diff -Nrcpad gcc-4.8.2/INSTALL/configure.html gcc-4.8.3/INSTALL/configure.html *** gcc-4.8.2/INSTALL/configure.html Wed Oct 16 07:28:02 2013 --- gcc-4.8.3/INSTALL/configure.html Thu May 22 09:13:50 2014 *************** *** 1,1759 **** ! ! ! ! ! ! Installing GCC ! ! ! ! ! ! ! ! ! ! ! ! !

Installing GCC

! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

Like most GNU software, GCC must be configured before it can be built. This document describes the recommended configuration procedure for both native and cross targets. !

!

We use srcdir to refer to the toplevel source directory for GCC; we use objdir to refer to the toplevel build/object directory. !

!

If you obtained the sources via SVN, srcdir must refer to the top ! gcc directory, the one where the MAINTAINERS file can be ! found, and not its gcc subdirectory, otherwise the build will fail. !

!

If either srcdir or objdir is located on an automounted NFS ! file system, the shell’s built-in pwd command will return temporary pathnames. Using these can lead to various sorts of build ! problems. To avoid this issue, set the PWDCMD environment ! variable to an automounter-aware pwd command, e.g., ! pawd or ‘amq -w’, during the configuration and build phases. !

!

First, we highly recommend that GCC be built into a separate directory from the sources which does not reside within the source tree. This is how we generally build GCC; building ! where srcdir == objdir should still work, but doesn’t get extensive testing; building where objdir is a subdirectory of srcdir is unsupported. !

!

If you have previously built GCC in the same directory for a ! different target machine, do ‘make distclean’ to delete all files ! that might be invalid. One of the files this deletes is Makefile; ! if ‘make distclean’ complains that Makefile does not exist ! or issues a message like “don’t know how to make distclean” it probably means that the directory is already suitably clean. However, with the recommended method of building in a separate objdir, you should simply use a different objdir for each target. !

!

Second, when configuring a native system, either cc or ! gcc must be in your path or you must set CC in your environment before running configure. Otherwise the configuration scripts may fail. -

!

To configure GCC: !

!
! 
% mkdir objdir
! % cd objdir
! % srcdir/configure [options] [target]
!
! !

Distributor options

If you will be distributing binary versions of GCC, with modifications to the source code, you should use the options described in this section to make clear that your version contains modifications. !

!
!
--with-pkgversion=version
!

Specify a string that identifies your package. You may wish to include a build number or build date. This version string will be ! included in the output of gcc --version. This suffix does ! not replace the default version string, only the ‘GCC’ part. !

!

The default value is ‘GCC’. !

!
!
--with-bugurl=url
!

Specify the URL that users should visit if they wish to report a bug. You are of course welcome to forward bugs reported to you to the FSF, if you determine that they are not bugs in your modifications. -

-

The default value refers to the FSF’s GCC bug tracker. -

-
-
! !

Target specification

!
    !
  • GCC has code to correctly determine the correct value for target for nearly all native systems. Therefore, we highly recommend you do not provide a configure target when configuring a native compiler. !
  • target must be specified as --target=target when configuring a cross compiler; examples of valid targets would be m68k-elf, sh-elf, etc. !
  • Specifying just target instead of --target=target ! implies that the host defaults to target. !
! ! !

Options specification

Use options to override several configure time options for ! GCC. A list of supported options follows; ‘configure ! --help’ may list other options, but those not listed below may not work and should not normally be used. !

!

Note that each --enable option has a corresponding ! --disable option and that each --with option has a ! corresponding --without option. !

!
!
--prefix=dirname
!

Specify the toplevel installation directory. This is the recommended way to install the tools into a directory other than the default. The toplevel installation directory defaults to ! /usr/local. !

!

We highly recommend against dirname being the same or a subdirectory of objdir or vice versa. If specifying a directory ! beneath a user’s home directory tree, some shells will not expand ! dirname correctly if it contains the ‘~’ metacharacter; use ! $HOME instead. !

!

The following standard autoconf options are supported. Normally you should not need to use these options. !

!
--exec-prefix=dirname
!

Specify the toplevel installation directory for architecture-dependent files. The default is prefix. !

!
!
--bindir=dirname
!

Specify the installation directory for the executables called by users ! (such as gcc and g++). The default is ! exec-prefix/bin. !

!
!
--libdir=dirname
!

Specify the installation directory for object code libraries and ! internal data files of GCC. The default is exec-prefix/lib. !

!
!
--libexecdir=dirname
!

Specify the installation directory for internal executables of GCC. ! The default is exec-prefix/libexec. !

!
!
--with-slibdir=dirname
!

Specify the installation directory for the shared libgcc library. The default is libdir. !

!
!
--datarootdir=dirname
!

Specify the root of the directory tree for read-only architecture-independent ! data files referenced by GCC. The default is prefix/share. !

!
!
--infodir=dirname
!

Specify the installation directory for documentation in info format. ! The default is datarootdir/info. !

!
!
--datadir=dirname
!

Specify the installation directory for some architecture-independent data files referenced by GCC. The default is datarootdir. !

!
!
--docdir=dirname
!

Specify the installation directory for documentation files (other ! than Info) for GCC. The default is datarootdir/doc. !

!
!
--htmldir=dirname
!

Specify the installation directory for HTML documentation files. The default is docdir. !

!
!
--pdfdir=dirname
!

Specify the installation directory for PDF documentation files. The default is docdir. !

!
!
--mandir=dirname
!

Specify the installation directory for manual pages. The default is ! datarootdir/man. (Note that the manual pages are only extracts from the full GCC manuals, which are provided in Texinfo format. The manpages are derived by an automatic conversion process from parts of the full manual.) !

!
!
--with-gxx-include-dir=dirname
!

Specify the installation directory for G++ header files. The default depends on other configuration options, and differs between cross and native configurations. !

!
!
--with-specs=specs
!

Specify additional command line driver SPECS. This can be useful if you need to turn on a non-standard feature by ! default without modifying the compiler’s source code, for instance ! --with-specs=%{!fcommon:%{!fno-common:-fno-common}}. See “Spec Files” in the main manual -

-
-
!
!
--program-prefix=prefix
!

GCC supports some transformations of the names of its programs when installing them. This option prepends prefix to the names of programs to install in bindir (see above). For example, specifying ! --program-prefix=foo- would result in ‘gcc’ ! being installed as /usr/local/bin/foo-gcc. !

!
!
--program-suffix=suffix
!

Appends suffix to the names of programs to install in bindir ! (see above). For example, specifying --program-suffix=-3.1 ! would result in ‘gcc’ being installed as ! /usr/local/bin/gcc-3.1. !

!
!
--program-transform-name=pattern
!

Applies the ‘sed’ script pattern to be applied to the names of programs to install in bindir (see above). pattern has to ! consist of one or more basic ‘sed’ editing commands, separated by ! semicolons. For example, if you want the ‘gcc’ program name to be ! transformed to the installed program /usr/local/bin/myowngcc and ! the ‘g++’ program name to be transformed to ! /usr/local/bin/gspecial++ without changing other program names, you could use the pattern ! --program-transform-name='s/^gcc$/myowngcc/; s/^g++$/gspecial++/' to achieve this effect. !

!

All three options can be combined and used together, resulting in more complex conversion patterns. As a basic rule, prefix (and suffix) are prepended (appended) before further transformations can happen with a special transformation script pattern. !

!

As currently implemented, this option only takes effect for native ! builds; cross compiler binaries’ names are not transformed even when a transformation is explicitly asked for by one of these options. !

!

For native builds, some of the installed programs are also installed with the target alias in front of their name, as in ! ‘i686-pc-linux-gnu-gcc’. All of the above transformations happen before the target alias is prepended to the name—so, specifying ! --program-prefix=foo- and program-suffix=-3.1, the resulting binary would be installed as ! /usr/local/bin/i686-pc-linux-gnu-foo-gcc-3.1. !

!

As a last shortcoming, none of the installed Ada programs are transformed yet, which will be fixed in some time. !

!
!
--with-local-prefix=dirname
!

Specify the installation directory for local include files. The default is ! /usr/local. Specify this option if you want the compiler to ! search directory dirname/include for locally installed ! header files instead of /usr/local/include. !

!

You should specify --with-local-prefix only if your ! site has a different convention (not /usr/local) for where to put site-specific files. !

!

The default value for --with-local-prefix is /usr/local ! regardless of the value of --prefix. Specifying ! --prefix has no effect on which directory GCC searches for local header files. This may seem counterintuitive, but actually it is logical. !

!

The purpose of --prefix is to specify where to install ! GCC. The local header files in /usr/local/include—if you put any in that directory—are not part of GCC. They are part of other programs—perhaps many others. (GCC installs its own header files in ! another directory which is based on the --prefix value.) !

!

Both the local-prefix include directory and the GCC-prefix include ! directory are part of GCC’s “system include” directories. Although these two directories are not fixed, they need to be searched in the proper order for the correct processing of the include_next directive. The local-prefix include directory is searched before the GCC-prefix include directory. Another characteristic of system include directories is that pedantic warnings are turned off for headers in these directories. !

!

Some autoconf macros add -I directory options to the compiler command line, to ensure that directories containing installed ! packages’ headers are searched. When directory is one of GCC’s system include directories, GCC will ignore the option so that system directories continue to be processed in the correct order. This may result in a search order different from what was specified but the directory will still be searched. !

!

GCC automatically searches for ordinary libraries using ! GCC_EXEC_PREFIX. Thus, when the same installation prefix is used for both GCC and packages, GCC will automatically search for both headers and libraries. This provides a configuration that is easy to use. GCC behaves in a manner similar to that when it is ! installed as a system compiler in /usr. !

!

Sites that need to install multiple versions of GCC may not want to use the above simple configuration. It is possible to use the ! --program-prefix, --program-suffix and ! --program-transform-name options to install multiple versions into a single directory, but it may be simpler to use different prefixes ! and the --with-local-prefix option to specify the location of the site-specific files for each version. It will then be necessary for users to specify explicitly the location of local site libraries ! (e.g., with LIBRARY_PATH). !

!

The same value can be used for both --with-local-prefix and ! --prefix provided it is not /usr. This can be used ! to avoid the default search of /usr/local/include. !

!

Do not specify /usr as the --with-local-prefix! ! The directory you use for --with-local-prefix must not ! contain any of the system’s standard header files. If it did contain them, certain programs would be miscompiled (including GNU Emacs, on certain targets), because this would override and nullify the header ! file corrections made by the fixincludes script. !

!

Indications are that people who use this option use it based on mistaken ideas of what it is for. People use it as if it specified where to install part of GCC. Perhaps they make this assumption because installing GCC creates the directory. !

!
!
--with-native-system-header-dir=dirname
!

Specifies that dirname is the directory that contains native system ! header files, rather than /usr/include. This option is most useful if you are creating a compiler that should be isolated from the system as much as possible. It is most commonly used with the ! --with-sysroot option and will cause GCC to search dirname inside the system root specified by that option. !

!
!
--enable-shared[=package[,…]]
!

Build shared versions of libraries, if shared libraries are supported on the target platform. Unlike GCC 2.95.x and earlier, shared libraries are enabled by default on all platforms that support shared libraries. !

!

If a list of packages is given as an argument, build shared libraries only for the listed packages. For other packages, only static libraries will be built. Package names currently recognized in the GCC tree are ! ‘libgcc’ (also known as ‘gcc’), ‘libstdc++’ (not ! ‘libstdc++-v3’), ‘libffi’, ‘zlib’, ‘boehm-gc’, ! ‘ada’, ‘libada’, ‘libjava’, ‘libgo’, and ‘libobjc’. ! Note ‘libiberty’ does not support shared libraries at all. !

!

Use --disable-shared to build only static libraries. Note that ! --disable-shared does not accept a list of package names as ! argument, only --enable-shared does. !

!
!
--with-gnu-as
!

Specify that the compiler should assume that the assembler it finds is the GNU assembler. However, this does not modify the rules to find an assembler and will result in confusion if the assembler found is not actually the GNU assembler. (Confusion may also result if the compiler finds the GNU assembler but has not been ! configured with --with-gnu-as.) If you have more than one assembler installed on your system, you may want to use this option in ! connection with --with-as=pathname or ! --with-build-time-tools=pathname. !

!

The following systems are the only ones where it makes a difference whether you use the GNU assembler. On any other system, ! --with-gnu-as has no effect. !

!
    !
  • ‘hppa1.0-any-any’ !
  • ‘hppa1.1-any-any’ !
  • ‘sparc-sun-solaris2.any’ !
  • ‘sparc64-any-solaris2.any’ !
!
!
--with-as=pathname
!

Specify that the compiler should use the assembler pointed to by pathname, rather than the one found by the standard rules to find an assembler, which are: !

    !
  • Unless GCC is being built with a cross compiler, check the ! libexec/gcc/target/version directory. ! libexec defaults to exec-prefix/libexec; exec-prefix defaults to prefix, which ! defaults to /usr/local unless overridden by the ! --prefix=pathname switch described above. target ! is the target system triple, such as ‘sparc-sun-solaris2.7’, and version denotes the GCC version, such as 3.0. !
  • If the target system is the same that you are building on, check ! operating system specific directories (e.g. /usr/ccs/bin on Sun Solaris 2). !
  • Check in the PATH for a tool whose name is prefixed by the target system triple. !
  • Check in the PATH for a tool whose name is not prefixed by the target system triple, if the host and target system triple are the same (in other words, we use a host tool if it can be used for ! the target as well). !
!

You may want to use --with-as if no assembler is installed in the directories listed above, or if you have multiple assemblers installed and want to choose one that is not found by the above rules. !

!
!
--with-gnu-ld
!

Same as --with-gnu-as but for the linker. !

!
!
--with-ld=pathname
!

Same as --with-as but for the linker. !

!
!
--with-stabs
!

Specify that stabs debugging information should be used instead of whatever format the host normally uses. Normally GCC uses the same debug format as the host system. !

!

On MIPS based systems and on Alphas, you must specify whether you want GCC to create the normal ECOFF debugging format, or to use BSD-style stabs passed through the ECOFF symbol table. The normal ECOFF debug format cannot fully handle languages other than C. BSD stabs format can handle other languages, but it only works with the GNU debugger GDB. !

!

Normally, GCC uses the ECOFF debugging format by default; if you ! prefer BSD stabs, specify --with-stabs when you configure GCC. !

!

No matter which default you choose when you configure GCC, the user ! can use the -gcoff and -gstabs+ options to specify explicitly the debug format for a particular compilation. !

!

--with-stabs is meaningful on the ISC system on the 386, also, if ! --with-gas is used. It selects use of stabs debugging information embedded in COFF output. This kind of debugging information supports C++ well; ordinary COFF debugging information does not. !

!

--with-stabs is also meaningful on 386 systems running SVR4. It selects use of stabs debugging information embedded in ELF output. The C++ compiler currently (2.6.0) does not support the DWARF debugging information normally used on 386 SVR4 platforms; stabs provide a workable alternative. This requires gas and gdb, as the normal SVR4 tools can not generate or interpret stabs. !

!
!
--with-tls=dialect
!

Specify the default TLS dialect, for systems were there is a choice. For ARM targets, possible values for dialect are gnu or gnu2, which select between the original GNU dialect and the GNU TLS descriptor-based dialect. !

!
!
--enable-multiarch
!

Specify whether to enable or disable multiarch support. The default is to check for glibc start files in a multiarch location, and enable it if the files are found. The auto detection is enabled for native builds, ! and for cross builds configured with --with-sysroot, and without ! --with-native-system-header-dir. More documentation about multiarch can be found at http://wiki.debian.org/Multiarch. !

!
!
--disable-multilib
!

Specify that multiple target libraries to support different target variants, calling conventions, etc. should not be built. The default is to build a predefined set of them. !

!

Some targets provide finer-grained control over which multilibs are built ! (e.g., --disable-softfloat): !

!
arm-*-*
!

fpu, 26bit, underscore, interwork, biendian, nofmult. !

!
!
m68*-*-*
!

softfloat, m68881, m68000, m68020. !

!
!
mips*-*-*
!

single-float, biendian, softfloat. !

!
!
powerpc*-*-*, rs6000*-*-*
!

aix64, pthread, softfloat, powercpu, powerpccpu, powerpcos, biendian, sysv, aix. -

-
-
!
!
--with-multilib-list=list
!
--without-multilib-list
!

Specify what multilibs to build. Currently only implemented for sh*-*-* and x86-64-*-linux*. !

!
!
sh*-*-*
!

list is a comma separated list of CPU names. These must be of the form sh* or m* (in which case they match the compiler option for that processor). The list should not contain any endian options - ! these are handled by --with-endian. !

!

If list is empty, then there will be no multilibs for extra processors. The multilib for the secondary endian remains enabled. !

!

As a special case, if an entry in the list starts with a ! ! (exclamation point), then it is added to the list of excluded multilibs. ! Entries of this sort should be compatible with ‘MULTILIB_EXCLUDES’ (once the leading ! has been stripped). !

!

If --with-multilib-list is not given, then a default set of ! multilibs is selected based on the value of --target. This is usually the complete set of libraries, but some targets imply a more specialized subset. -

-

Example 1: to configure a compiler for SH4A only, but supporting both - endians, with little endian being the default: -

- 
--with-cpu=sh4a --with-endian=little,big --with-multilib-list=
-
!

Example 2: to configure a compiler for both SH4A and SH4AL-DSP, but with only little endian SH4AL: !

! 
--with-cpu=sh4a --with-endian=little,big \
! --with-multilib-list=sh4al,!mb/m4al
!
! !
!
x86-64-*-linux*
!

list is a comma separated list of m32, m64 and mx32 to enable 32-bit, 64-bit and x32 run-time libraries, respectively. If list is empty, then there will be no multilibs and only the default run-time library will be enabled. !

!

If --with-multilib-list is not given, then only 32-bit and ! 64-bit run-time libraries will be enabled. !

!
!
--with-endian=endians
!

Specify what endians to use. Currently only implemented for sh*-*-*. !

!

endians may be one of the following: !

!
big
!

Use big endian exclusively. !

!
little
!

Use little endian exclusively. !

!
big,little
!

Use big endian by default. Provide a multilib for little endian. !

!
little,big
!

Use little endian by default. Provide a multilib for big endian. !

!
!
--enable-threads
!

Specify that the target supports threads. This affects the Objective-C compiler and runtime ! library, and exception handling for other languages like C++ and Java. On some systems, this is the default. !

!

In general, the best (and, in many cases, the only known) threading model available will be configured for use. Beware that on some systems, GCC has not been taught what threading models are generally ! available for the system. In this case, --enable-threads is an ! alias for --enable-threads=single. !

!
!
--disable-threads
!

Specify that threading support should be disabled for the system. ! This is an alias for --enable-threads=single. !

!
!
--enable-threads=lib
!

Specify that lib is the thread support library. This affects the Objective-C compiler and runtime library, and exception handling for other languages like C++ and Java. The possibilities for lib are: !

!
!
aix
!

AIX thread support. !

!
dce
!

DCE thread support. !

!
lynx
!

LynxOS thread support. !

!
mipssde
!

MIPS SDE thread support. !

!
no
!

This is an alias for ‘single’. !

!
posix
!

Generic POSIX/Unix98 thread support. !

!
rtems
!

RTEMS thread support. !

!
single
!

Disable thread support, should work for all platforms. !

!
tpf
!

TPF thread support. !

!
vxworks
!

VxWorks thread support. !

!
win32
!

Microsoft Win32 API thread support. !

!
!
--enable-tls
!

Specify that the target supports TLS (Thread Local Storage). Usually configure can correctly determine if TLS is supported. In cases where it guesses incorrectly, TLS can be explicitly enabled or disabled with ! --enable-tls or --disable-tls. This can happen if the assembler supports TLS but the C library does not, or if the assumptions made by the configure test are incorrect. !

!
!
--disable-tls
!

Specify that the target does not support TLS. ! This is an alias for --enable-tls=no. !

!
!
--with-cpu=cpu
!
--with-cpu-32=cpu
!
--with-cpu-64=cpu
!

Specify which cpu variant the compiler should generate code for by default. ! cpu will be used as the default value of the -mcpu= switch. This option is only supported on some targets, including ARM, i386, M68k, ! PowerPC, and SPARC. The --with-cpu-32 and ! --with-cpu-64 options specify separate default CPUs for 32-bit and 64-bit modes; these options are only supported for i386, x86-64 and PowerPC. !

!
!
--with-schedule=cpu
!
--with-arch=cpu
!
--with-arch-32=cpu
!
--with-arch-64=cpu
!
--with-tune=cpu
!
--with-tune-32=cpu
!
--with-tune-64=cpu
!
--with-abi=abi
!
--with-fpu=type
!
--with-float=type
!

These configure options provide default values for the -mschedule=, ! -march=, -mtune=, -mabi=, and -mfpu= ! options and for -mhard-float or -msoft-float. As with ! --with-cpu, which switches will be accepted and acceptable values of the arguments depend on the target. !

!
!
--with-mode=mode
!

Specify if the compiler should default to -marm or -mthumb. This option is only supported on ARM targets. !

!
!
--with-stack-offset=num
!

This option sets the default for the -mstack-offset=num option, and will thus generally also control the setting of this option for libraries. This option is only supported on Epiphany targets. !

!
!
--with-fpmath=isa
!

This options sets -mfpmath=sse by default and specifies the default ! ISA for floating-point arithmetics. You can select either ‘sse’ which ! enables -msse2 or ‘avx’ which enables -mavx by default. This option is only supported on i386 and x86-64 targets. !

!
!
--with-divide=type
!

Specify how the compiler should generate code for checking for ! division by zero. This option is only supported on the MIPS target. The possibilities for type are: !

!
traps
!

Division by zero checks use conditional traps (this is the default on ! systems that support conditional traps). !

!
breaks
!

Division by zero checks use the break instruction. !

! !
!
--with-llsc
!

On MIPS targets, make -mllsc the default when no ! -mno-llsc option is passed. This is the default for Linux-based targets, as the kernel will emulate them if the ISA does not provide them. !

!
!
--without-llsc
!

On MIPS targets, make -mno-llsc the default when no ! -mllsc option is passed. !

!
!
--with-synci
!

On MIPS targets, make -msynci the default when no ! -mno-synci option is passed. !

!
!
--without-synci
!

On MIPS targets, make -mno-synci the default when no ! -msynci option is passed. This is the default. !

!
!
--with-mips-plt
!

On MIPS targets, make use of copy relocations and PLTs. These features are extensions to the traditional SVR4-based MIPS ABIs and require support from GNU binutils and the runtime C library. !

!
!
--enable-__cxa_atexit
!

Define if you want to use __cxa_atexit, rather than atexit, to ! register C++ destructors for local statics and global objects. This is essential for fully standards-compliant handling of destructors, but requires __cxa_atexit in libc. This option is currently only available on systems with GNU libc. When enabled, this will cause ! -fuse-cxa-atexit to be passed by default. !

!
!
--enable-gnu-indirect-function
!

Define if you want to enable the ifunc attribute. This option is currently only available on systems with GNU libc on certain targets. !

!
!
--enable-target-optspace
!

Specify that target ! libraries should be optimized for code space instead of code speed. This is the default for the m32r platform. !

!
!
--with-cpp-install-dir=dirname
!

Specify that the user visible cpp program should be installed ! in prefix/dirname/cpp, in addition to bindir. !

!
!
--enable-comdat
!

Enable COMDAT group support. This is primarily used to override the automatically detected value. !

!
!
--enable-initfini-array
!

Force the use of sections .init_array and .fini_array (instead of .init and .fini) for constructors and ! destructors. Option --disable-initfini-array has the opposite effect. If neither option is specified, the configure script will try to guess whether the .init_array and .fini_array sections are supported and, if they are, use them. !

!
!
--enable-maintainer-mode
!

The build rules that regenerate the Autoconf and Automake output files as ! well as the GCC master message catalog gcc.pot are normally disabled. This is because it can only be rebuilt if the complete source tree is present. If you have changed the sources and want to rebuild the ! catalog, configuring with --enable-maintainer-mode will enable this. Note that you need a recent version of the gettext tools to do so. !

!
!
--disable-bootstrap
!

For a native build, the default configuration is to perform ! a 3-stage bootstrap of the compiler when ‘make’ is invoked, testing that GCC can compile itself correctly. If you want to disable ! this process, you can configure with --disable-bootstrap. !

!
!
--enable-bootstrap
!

In special cases, you may want to perform a 3-stage build ! even if the target and host triplets are different. This is possible when the host can run code compiled for ! the target (e.g. host is i686-linux, target is i486-linux). Starting from GCC 4.2, to do this you have to configure explicitly ! with --enable-bootstrap. !

!
!
--enable-generated-files-in-srcdir
!

Neither the .c and .h files that are generated from Bison and flex nor the info manuals and man pages that are built from the .texi files are present in the SVN development tree. When building GCC from that development tree, or from one of our snapshots, those generated files are placed in your build directory, which allows for the source to be in a readonly directory. !

!

If you configure with --enable-generated-files-in-srcdir then those generated files will go into the source directory. This is mainly intended for generating release or prerelease tarballs of the GCC sources, since it is not a requirement that the users of source releases to have flex, Bison, or makeinfo. !

!
!
--enable-version-specific-runtime-libs
!

Specify that runtime libraries should be installed in the compiler specific ! subdirectory (libdir/gcc) rather than the usual places. In ! addition, ‘libstdc++’’s include files will be installed into libdir unless you overruled it by using ! --with-gxx-include-dir=dirname. Using this option is particularly useful if you intend to use several versions of GCC in ! parallel. This is currently supported by ‘libgfortran’, ! ‘libjava’, ‘libmudflap’, ‘libstdc++’, and ‘libobjc’. !

!
!
--enable-languages=lang1,lang2,…
!

Specify that only a particular subset of compilers and their runtime libraries should be built. For a list of valid values for langN you can issue the following command in the ! gcc directory of your GCC source tree:
!

! 
grep language= */config-lang.in
!
!

Currently, you can use any of the following: all, ada, c, c++, fortran, ! go, java, objc, obj-c++. ! Building the Ada compiler has special requirements, see below. If you do not pass this flag, or specify the option all, then all ! default languages available in the gcc sub-tree will be configured. Ada, Go and Objective-C++ are not default languages; the rest are. !

!
!
--enable-stage1-languages=lang1,lang2,…
!

Specify that a particular subset of compilers and their runtime libraries should be built with the system C compiler during stage 1 of the bootstrap process, rather than only in later stages with the bootstrapped C compiler. The list of valid values is the same as for ! --enable-languages, and the option all will select all ! of the languages enabled by --enable-languages. This option is primarily useful for GCC development; for instance, when a development version of the compiler cannot bootstrap due to compiler bugs, or when one is debugging front ends other than the C front end. When this option is used, one can then build the target libraries for the ! specified languages with the stage-1 compiler by using make ! stage1-bubble all-target, or run the testsuite on the stage-1 compiler ! for the specified languages using make stage1-start check-gcc. !

!
!
--disable-libada
!

Specify that the run-time libraries and tools used by GNAT should not be built. This can be useful for debugging, or for compatibility with previous Ada build procedures, when it was required to explicitly ! do a ‘make -C gcc gnatlib_and_tools’. !

!
!
--disable-libssp
!

Specify that the run-time libraries for stack smashing protection should not be built. !

!
!
--disable-libquadmath
!

Specify that the GCC quad-precision math library should not be built. On some systems, the library is required to be linkable when building ! the Fortran front end, unless --disable-libquadmath-support is used. !

!
!
--disable-libquadmath-support
!

Specify that the Fortran front end and libgfortran do not add support for libquadmath on systems supporting it. !

!
!
--disable-libgomp
!

Specify that the run-time libraries used by GOMP should not be built. !

!
!
--with-dwarf2
!

Specify that the compiler should use DWARF 2 debugging information as the default. !

!
!
--enable-targets=all
!
--enable-targets=target_list
!

Some GCC targets, e.g. powerpc64-linux, build bi-arch compilers. These are compilers that are able to generate either 64-bit or 32-bit ! code. Typically, the corresponding 32-bit target, e.g. powerpc-linux for powerpc64-linux, only generates 32-bit code. This option enables the 32-bit target to be a bi-arch compiler, which is useful when you want a bi-arch compiler that defaults to 32-bit, and ! you are building a bi-arch or multi-arch binutils in a combined tree. On mips-linux, this will build a tri-arch compiler (ABI o32/n32/64), ! defaulted to o32. Currently, this option only affects sparc-linux, powerpc-linux, x86-linux, mips-linux and s390-linux. !

!
!
--enable-secureplt
!

This option enables -msecure-plt by default for powerpc-linux. See “RS/6000 and PowerPC Options” in the main manual !

!
!
--enable-cld
!

This option enables -mcld by default for 32-bit x86 targets. See “i386 and x86-64 Options” in the main manual !

!
!
--enable-win32-registry
!
--enable-win32-registry=key
!
--disable-win32-registry
!

The --enable-win32-registry option enables Microsoft Windows-hosted GCC to look up installations paths in the registry using the following key: -

-
- 
HKEY_LOCAL_MACHINE\SOFTWARE\Free Software Foundation\key
-
!

key defaults to GCC version number, and can be overridden by the ! --enable-win32-registry=key option. Vendors and distributors who use custom installers are encouraged to provide a different key, perhaps one comprised of vendor name and GCC version number, to avoid conflict with existing installations. This feature is enabled ! by default, and can be disabled by --disable-win32-registry option. This option has no effect on the other hosts. !

!
!
--nfp
!

Specify that the machine does not have a floating point unit. This ! option only applies to ‘m68k-sun-sunosn’. On any other ! system, --nfp has no effect. !

!
!
--enable-werror
!
--disable-werror
!
--enable-werror=yes
!
--enable-werror=no
!

When you specify this option, it controls whether certain files in the ! compiler are built with -Werror in bootstrap stage2 and later. ! If you don’t specify it, -Werror is turned on for the main development trunk. However it defaults to off for release branches and ! final releases. The specific files which get -Werror are controlled by the Makefiles. !

!
!
--enable-checking
!
--enable-checking=list
!

When you specify this option, the compiler is built to perform internal consistency checks of the requested complexity. This does not change the generated code, but adds error checking within the compiler. This will slow down the compiler and may only work properly if you are building ! the compiler with GCC. This is ‘yes’ by default when building ! from SVN or snapshots, but ‘release’ for releases. The default ! for building the stage1 compiler is ‘yes’. More control over the checks may be had by specifying list. The categories of ! checks available are ‘yes’ (most common checks ! ‘assert,misc,tree,gc,rtlflag,runtime’), ‘no’ (no checks at ! all), ‘all’ (all but ‘valgrind’), ‘release’ (cheapest ! checks ‘assert,runtime’) or ‘none’ (same as ‘no’). ! Individual checks can be enabled with these flags ‘assert’, ! ‘df’, ‘fold’, ‘gc’, ‘gcac’ ‘misc’, ‘rtl’, ! ‘rtlflag’, ‘runtime’, ‘tree’, and ‘valgrind’. !

!

The ‘valgrind’ check requires the external valgrind simulator, available from http://valgrind.org/. The ! ‘df’, ‘rtl’, ‘gcac’ and ‘valgrind’ checks are very expensive. ! To disable all checking, ‘--disable-checking’ or ! ‘--enable-checking=none’ must be explicitly requested. Disabling assertions will make the compiler and runtime slightly faster but increase the risk of undetected internal errors causing wrong code to be generated. !

!
!
--disable-stage1-checking
!
--enable-stage1-checking
!
--enable-stage1-checking=list
!

If no --enable-checking option is specified the stage1 ! compiler will be built with ‘yes’ checking enabled, otherwise the stage1 checking flags are the same as specified by ! --enable-checking. To build the stage1 compiler with ! different checking options use --enable-stage1-checking. ! The list of checking options is the same as for --enable-checking. If your system is too slow or too small to bootstrap a released compiler ! with checking for stage1 enabled, you can use ‘--disable-stage1-checking’ to disable checking for the stage1 compiler. !

!
!
--enable-coverage
!
--enable-coverage=level
!

With this option, the compiler is built to collect self coverage information, every time it is run. This is for internal development purposes, and only works when the compiler is being built with gcc. The level argument controls whether the compiler is built optimized or ! not, values are ‘opt’ and ‘noopt’. For coverage analysis you want to disable optimization, for performance analysis you want to enable optimization. When coverage is enabled, the default level is without optimization. !

!
!
--enable-gather-detailed-mem-stats
!

When this option is specified more detailed information on memory allocation is gathered. This information is printed when using ! -fmem-report. !

!
!
--enable-nls
!
--disable-nls
!

The --enable-nls option enables Native Language Support (NLS), which lets GCC output diagnostics in languages other than American English. Native Language Support is enabled by default if not doing a ! canadian cross build. The --disable-nls option disables NLS. !

!
!
--with-included-gettext
!

If NLS is enabled, the --with-included-gettext option causes the build ! procedure to prefer its copy of GNU gettext. !

!
!
--with-catgets
!

If NLS is enabled, and if the host lacks gettext but has the inferior catgets interface, the GCC build procedure normally ! ignores catgets and instead uses GCC’s copy of the GNU ! gettext library. The --with-catgets option causes the ! build procedure to use the host’s catgets in this situation. !

!
!
--with-libiconv-prefix=dir
!

Search for libiconv header files in dir/include and ! libiconv library files in dir/lib. !

!
!
--enable-obsolete
!

Enable configuration for an obsoleted system. If you attempt to configure GCC for a system (build, host, or target) which has been obsoleted, and you do not specify this flag, configure will halt with an error message. !

!

All support for systems which have been obsoleted in one release of GCC is removed entirely in the next major release, unless someone steps forward to maintain the port. !

!
!
--enable-decimal-float
!
--enable-decimal-float=yes
!
--enable-decimal-float=no
!
--enable-decimal-float=bid
!
--enable-decimal-float=dpd
!
--disable-decimal-float
!

Enable (or disable) support for the C decimal floating point extension that is in the IEEE 754-2008 standard. This is enabled by default only on PowerPC, i386, and x86_64 GNU/Linux systems. Other systems may also support it, but require the user to specifically enable it. You can optionally control which decimal floating point format is used (either ! ‘bid’ or ‘dpd’). The ‘bid’ (binary integer decimal) ! format is default on i386 and x86_64 systems, and the ‘dpd’ (densely packed decimal) format is default on PowerPC systems. !

!
!
--enable-fixed-point
!
--disable-fixed-point
!

Enable (or disable) support for C fixed-point arithmetic. This option is enabled by default for some targets (such as MIPS) which have hardware-support for fixed-point operations. On other targets, you may enable this option manually. !

!
!
--with-long-double-128
!

Specify if long double type should be 128-bit by default on selected GNU/Linux architectures. If using --without-long-double-128, ! long double will be by default 64-bit, the same as double type. When neither of these configure options are used, the default will be 128-bit long double when built against GNU C Library 2.4 and later, 64-bit long double otherwise. !

!
!
--with-gmp=pathname
!
--with-gmp-include=pathname
!
--with-gmp-lib=pathname
!
--with-mpfr=pathname
!
--with-mpfr-include=pathname
!
--with-mpfr-lib=pathname
!
--with-mpc=pathname
!
--with-mpc-include=pathname
!
--with-mpc-lib=pathname
!

If you want to build GCC but do not have the GMP library, the MPFR library and/or the MPC library installed in a standard location and do not have their sources present in the GCC source tree then you can explicitly specify the directory where they are installed ! (‘--with-gmp=gmpinstalldir’, ! ‘--with-mpfr=mpfrinstalldir’, ! ‘--with-mpc=mpcinstalldir’). The ! --with-gmp=gmpinstalldir option is shorthand for ! --with-gmp-lib=gmpinstalldir/lib and ! --with-gmp-include=gmpinstalldir/include. Likewise the ! --with-mpfr=mpfrinstalldir option is shorthand for ! --with-mpfr-lib=mpfrinstalldir/lib and ! --with-mpfr-include=mpfrinstalldir/include, also the ! --with-mpc=mpcinstalldir option is shorthand for ! --with-mpc-lib=mpcinstalldir/lib and ! --with-mpc-include=mpcinstalldir/include. If these shorthand assumptions are not correct, you can use the explicit include and lib options directly. You might also need to ensure the shared libraries can be found by the dynamic linker when building and using GCC, for example by setting the runtime shared library path ! variable (LD_LIBRARY_PATH on GNU/Linux and Solaris systems). !

!

These flags are applicable to the host platform only. When building a cross compiler, they will not be used to configure target libraries. !

!
!
--with-isl=pathname
!
--with-isl-include=pathname
!
--with-isl-lib=pathname
!
--with-cloog=pathname
!
--with-cloog-include=pathname
!
--with-cloog-lib=pathname
!

If you do not have ISL and the CLooG libraries installed in a standard location and you want to build GCC, you can explicitly specify the directory where they are installed ! (‘--with-isl=islinstalldir’, ! ‘--with-cloog=clooginstalldir’). The ! --with-isl=islinstalldir option is shorthand for ! --with-isl-lib=islinstalldir/lib and ! --with-isl-include=islinstalldir/include. Likewise the ! --with-cloog=clooginstalldir option is shorthand for ! --with-cloog-lib=clooginstalldir/lib and ! --with-cloog-include=clooginstalldir/include. If these shorthand assumptions are not correct, you can use the explicit include and lib options directly. !

!

These flags are applicable to the host platform only. When building a cross compiler, they will not be used to configure target libraries. !

!
!
--with-host-libstdcxx=linker-args
!

If you are linking with a static copy of PPL, you can use this option to specify how the linker should find the standard C++ library used internally by PPL. Typical values of linker-args might be ! ‘-lstdc++’ or ‘-Wl,-Bstatic,-lstdc++,-Bdynamic -lm’. If you are linking with a shared copy of PPL, you probably do not need this option; shared library dependencies will cause the linker to search for the standard C++ library automatically. !

!
!
--with-stage1-ldflags=flags
!

This option may be used to set linker flags to be used when linking stage 1 of GCC. These are also used when linking GCC if configured with ! --disable-bootstrap. By default no special flags are used. !

!
!
--with-stage1-libs=libs
!

This option may be used to set libraries to be used when linking stage 1 of GCC. These are also used when linking GCC if configured with ! --disable-bootstrap. The default is the argument to ! --with-host-libstdcxx, if specified. !

!
!
--with-boot-ldflags=flags
!

This option may be used to set linker flags to be used when linking stage 2 and later when bootstrapping GCC. If neither –with-boot-libs nor –with-host-libstdcxx is set to a value, then the default is ! ‘-static-libstdc++ -static-libgcc’. !

!
!
--with-boot-libs=libs
!

This option may be used to set libraries to be used when linking stage 2 and later when bootstrapping GCC. The default is the argument to ! --with-host-libstdcxx, if specified. !

!
!
--with-debug-prefix-map=map
!

Convert source directory names using -fdebug-prefix-map when building runtime libraries. ‘map’ is a space-separated ! list of maps of the form ‘old=new’. !

!
!
--enable-linker-build-id
!

Tells GCC to pass --build-id option to the linker for all final ! links (links performed without the -r or --relocatable option), if the linker supports it. If you specify ! --enable-linker-build-id, but your linker does not ! support --build-id option, a warning is issued and the ! --enable-linker-build-id option is ignored. The default is off. !

!
!
--with-linker-hash-style=choice
!

Tells GCC to pass --hash-style=choice option to the linker for all final links. choice can be one of ! ‘sysv’, ‘gnu’, and ‘both’ where ‘sysv’ is the default. !

!
!
--enable-gnu-unique-object
!
--disable-gnu-unique-object
!

Tells GCC to use the gnu_unique_object relocation for C++ template static data members and inline function local statics. Enabled by default for a native toolchain with an assembler that accepts it and GLIBC 2.11 or above, otherwise disabled. !

!
!
--enable-lto
!
--disable-lto
!

Enable support for link-time optimization (LTO). This is enabled by ! default, and may be disabled using --disable-lto. !

!
!
--with-plugin-ld=pathname
!

Enable an alternate linker to be used at link-time optimization (LTO) ! link time when -fuse-linker-plugin is enabled. This linker should have plugin support such as gold starting with ! version 2.20 or GNU ld starting with version 2.21. ! See -fuse-linker-plugin for details. !

!
!
--enable-canonical-system-headers
!
--disable-canonical-system-headers
!

Enable system header path canonicalization for libcpp. This can produce shorter header file paths in diagnostics and dependency output files, but these changed header paths may conflict with some compilation environments. Enabled by default, and may be disabled using ! --disable-canonical-system-headers. !

! !

Cross-Compiler-Specific Options

The following options only apply to building cross compilers. !

!
!
--with-sysroot
!
--with-sysroot=dir
!

Tells GCC to consider dir as the root of a tree that contains ! (a subset of) the root filesystem of the target operating system. Target system headers, libraries and run-time object files will be searched for in there. More specifically, this acts as if ! --sysroot=dir was added to the default options of the built compiler. The specified directory is not copied into the ! install tree, unlike the options --with-headers and ! --with-libs that this option obsoletes. The default value, ! in case --with-sysroot is not given an argument, is ! ${gcc_tooldir}/sys-root. If the specified directory is a ! subdirectory of ${exec_prefix}, then it will be found relative to the GCC binaries if the installation tree is moved. !

!

This option affects the system root for the compiler used to build target libraries (which runs on the build system) and the compiler newly installed with make install; it does not affect the compiler which is used to build GCC itself. !

!

If you specify the --with-native-system-header-dir=dirname option then the compiler will search that directory within dirname for ! native system headers rather than the default /usr/include. !

!
!
--with-build-sysroot
!
--with-build-sysroot=dir
!

Tells GCC to consider dir as the system root (see ! --with-sysroot) while building target libraries, instead of ! the directory specified with --with-sysroot. This option is ! only useful when you are already using --with-sysroot. You ! can use --with-build-sysroot when you are configuring with ! --prefix set to a directory that is different from the one in which you are installing GCC and your target libraries. !

!

This option affects the system root for the compiler used to build target libraries (which runs on the build system); it does not affect the compiler which is used to build GCC itself. !

!

If you specify the --with-native-system-header-dir=dirname option then the compiler will search that directory within dirname for ! native system headers rather than the default /usr/include. !

!
!
--with-headers
!
--with-headers=dir
!

Deprecated in favor of --with-sysroot. ! Specifies that target headers are available when building a cross compiler. The dir argument specifies a directory which has the target include ! files. These include files will be copied into the gcc install ! directory. This option with the dir argument is required when ! building a cross compiler, if prefix/target/sys-include ! doesn’t pre-exist. If prefix/target/sys-include does ! pre-exist, the dir argument may be omitted. fixincludes will be run on these files to make them compatible with GCC. !

!
!
--without-headers
!

Tells GCC not use any target headers from a libc when building a cross compiler. When crossing to GNU/Linux, you need the headers so GCC can build the exception handling for libgcc. !

!
!
--with-libs
!
--with-libs="dir1 dir2 … dirN"
!

Deprecated in favor of --with-sysroot. Specifies a list of directories which contain the target runtime ! libraries. These libraries will be copied into the gcc install directory. If the directory list is omitted, this option has no effect. !

!
!
--with-newlib
!

Specifies that ‘newlib’ is being used as the target C library. This causes __eprintf to be ! omitted from libgcc.a on the assumption that it will be provided by ! ‘newlib’. !

!
!
--with-avrlibc
!

Specifies that ‘AVR-Libc’ is being used as the target C library. This causes float support ! functions like __addsf3 to be omitted from libgcc.a on ! the assumption that it will be provided by libm.a. For more ! technical details, cf. PR54461. This option is only supported for the AVR target. It is not supported for RTEMS configurations, which currently use newlib. The option is supported since version 4.7.2 and is the default in 4.8.0 and newer. !

!
!
--with-build-time-tools=dir
!

Specifies where to find the set of target tools (assembler, linker, etc.) that will be used while building GCC itself. This option can be useful if the directory layouts are different between the system you are building GCC on, and the system where you will deploy it. !

!

For example, on an ‘ia64-hp-hpux’ system, you may have the GNU ! assembler and linker in /usr/bin, and the native tools in a different path, and build a toolchain that expects to find the ! native tools in /usr/bin. !

!

When you use this option, you should ensure that dir includes ! ar, as, ld, nm, ! ranlib and strip if necessary, and possibly ! objdump. Otherwise, GCC may use an inconsistent set of ! tools. !

! !

Java-Specific Options

The following option applies to the build of the Java front end. !

!
!
--disable-libgcj
!

Specify that the run-time libraries used by GCJ should not be built. This is useful in case you intend ! to use GCJ with some other run-time, or you’re going to install it separately, or it just happens not to build on your particular machine. In general, if the Java front end is enabled, the GCJ ! libraries will be enabled too, unless they’re known to not work on ! the target platform. If GCJ is enabled but ‘libgcj’ isn’t built, you may need to port it; in this case, before modifying the top-level ! configure.in so that ‘libgcj’ is enabled by default on this platform, ! you may use --enable-libgcj to override the default. !

!
!
!

The following options apply to building ‘libgcj’. !

! !

General Options

!
!
--enable-java-maintainer-mode
!

By default the ‘libjava’ build will not attempt to compile the ! .java source files to .class. Instead, it will use the ! .class files from the source tree. If you use this option you ! must have executables named ecj1 and gjavah in your path for use by the build. You must use this option if you intend to ! modify any .java files in libjava. !

!
!
--with-java-home=dirname
!

This ‘libjava’ option overrides the default value of the ! ‘java.home’ system property. It is also used to set ! ‘sun.boot.class.path’ to dirname/lib/rt.jar. By ! default ‘java.home’ is set to prefix and ! ‘sun.boot.class.path’ to ! datadir/java/libgcj-version.jar. !

!
!
--with-ecj-jar=filename
!

This option can be used to specify the location of an external jar file containing the Eclipse Java compiler. A specially modified ! version of this compiler is used by gcj to parse ! .java source files. If this option is given, the ! ‘libjava’ build will create and install an ecj1 executable which uses this jar file at runtime. !

!

If this option is not given, but an ecj.jar file is found in ! the topmost source tree at configure time, then the ‘libgcj’ ! build will create and install ecj1, and will also install the ! discovered ecj.jar into a suitable place in the install tree. !

!

If ecj1 is not installed, then the user will have to supply one ! on his path in order for gcj to properly parse .java source files. A suitable jar is available from ftp://sourceware.org/pub/java/. !

!
!
--disable-getenv-properties
!

Don’t set system properties from GCJ_PROPERTIES. !

!
!
--enable-hash-synchronization
!

Use a global hash table for monitor locks. Ordinarily, ! ‘libgcj’’s ‘configure’ script automatically makes the correct choice for this option for your platform. Only use this if you know you need the library to be configured differently. !

!
!
--enable-interpreter
!

Enable the Java interpreter. The interpreter is automatically enabled by default on all platforms that support it. This option is really only useful if you want to disable the interpreter ! (using --disable-interpreter). !

!
!
--disable-java-net
!

Disable java.net. This disables the native part of java.net only, using non-functional stubs for native method implementations. !

!
!
--disable-jvmpi
!

Disable JVMPI support. !

!
!
--disable-libgcj-bc
!

Disable BC ABI compilation of certain parts of libgcj. By default, ! some portions of libgcj are compiled with -findirect-dispatch ! and -fno-indirect-classes, allowing them to be overridden at run-time. !

!

If --disable-libgcj-bc is specified, libgcj is built without these options. This allows the compile-time linker to resolve dependencies when statically linking to libgcj. However it makes it impossible to override the affected portions of libgcj at run-time. !

!
!
--enable-reduced-reflection
!

Build most of libgcj with -freduced-reflection. This reduces the size of libgcj at the expense of not being able to do accurate reflection on the classes it contains. This option is safe if you know that code using libgcj will never use reflection on the standard runtime classes in libgcj (including using serialization, RMI or CORBA). !

!
!
--with-ecos
!

Enable runtime eCos target support. !

!
!
--without-libffi
!

Don’t use ‘libffi’. This will disable the interpreter and JNI ! support as well, as these require ‘libffi’ to work. !

!
!
--enable-libgcj-debug
!

Enable runtime debugging code. !

!
!
--enable-libgcj-multifile
!

If specified, causes all .java source files to be ! compiled into .class files in one invocation of ! ‘gcj’. This can speed up build time, but is more resource-intensive. If this option is unspecified or ! disabled, ‘gcj’ is invoked once for each .java ! file to compile into a .class file. !

!
!
--with-libiconv-prefix=DIR
!

Search for libiconv in DIR/include and DIR/lib. !

!
!
--enable-sjlj-exceptions
!

Force use of the setjmp/longjmp-based scheme for exceptions. ! ‘configure’ ordinarily picks the correct value based on the platform. Only use this option if you are sure you need a different setting. !

!
!
--with-system-zlib
!

Use installed ‘zlib’ rather than that included with GCC. !

!
!
--with-win32-nlsapi=ansi, unicows or unicode
!

Indicates how MinGW ‘libgcj’ translates between UNICODE characters and the Win32 API. !

!
!
--enable-java-home
!

If enabled, this creates a JPackage compatible SDK environment during install. Note that if –enable-java-home is used, –with-arch-directory=ARCH must also be specified. !

!
!
--with-arch-directory=ARCH
!

Specifies the name to use for the jre/lib/ARCH directory in the SDK environment created when –enable-java-home is passed. Typical names for this directory include i386, amd64, ia64, etc. !

!
!
--with-os-directory=DIR
!

Specifies the OS directory for the SDK include directory. This is set to auto ! detect, and is typically ’linux’. !

!
!
--with-origin-name=NAME
!

Specifies the JPackage origin name. This defaults to the ’gcj’ in java-1.5.0-gcj. !

!
!
--with-arch-suffix=SUFFIX
!

Specifies the suffix for the sdk directory. Defaults to the empty string. ! Examples include ’.x86_64’ in ’java-1.5.0-gcj-1.5.0.0.x86_64’. !

!
!
--with-jvm-root-dir=DIR
!

Specifies where to install the SDK. Default is $(prefix)/lib/jvm. !

!
!
--with-jvm-jar-dir=DIR
!

Specifies where to install jars. Default is $(prefix)/lib/jvm-exports. !

!
!
--with-python-dir=DIR
!

Specifies where to install the Python modules used for aot-compile. DIR should not include the prefix used in installation. For example, if the Python modules are to be installed in /usr/lib/python2.5/site-packages, then –with-python-dir=/lib/python2.5/site-packages should be passed. If this is not specified, then the Python modules are installed in $(prefix)/share/python. !

!
!
--enable-aot-compile-rpm
!

Adds aot-compile-rpm to the list of installed scripts. !

!
!
--enable-browser-plugin
!

Build the gcjwebplugin web browser plugin. !

!
!
--enable-static-libjava
!

Build static libraries in libjava. The default is to only build shared libraries. !

!
!
ansi
!

Use the single-byte char and the Win32 A functions natively, translating to and from UNICODE when using these functions. If unspecified, this is the default. !

!
!
unicows
!

Use the WCHAR and Win32 W functions natively. Adds ! -lunicows to libgcj.spec to link with ‘libunicows’. ! unicows.dll needs to be deployed on Microsoft Windows 9X machines ! running built executables. libunicows.a, an open-source ! import library around Microsoft’s unicows.dll, is obtained from http://libunicows.sourceforge.net/, which also gives details ! on getting unicows.dll from Microsoft. !

!
!
unicode
!

Use the WCHAR and Win32 W functions natively. Does not ! add -lunicows to libgcj.spec. The built executables will ! only run on Microsoft Windows NT and above. !

!
!
! !

AWT-Specific Options

!
!
--with-x
!

Use the X Window System. !

!
!
--enable-java-awt=PEER(S)
!

Specifies the AWT peer library or libraries to build alongside ! ‘libgcj’. If this option is unspecified or disabled, AWT ! will be non-functional. Current valid values are gtk and ! xlib. Multiple libraries should be separated by a ! comma (i.e. --enable-java-awt=gtk,xlib). !

!
!
--enable-gtk-cairo
!

Build the cairo Graphics2D implementation on GTK. !

!
!
--enable-java-gc=TYPE
!

Choose garbage collector. Defaults to boehm if unspecified. !

!
!
--disable-gtktest
!

Do not try to compile and run a test GTK+ program. !

!
!
--disable-glibtest
!

Do not try to compile and run a test GLIB program. !

!
!
--with-libart-prefix=PFX
!

Prefix where libart is installed (optional). !

!
!
--with-libart-exec-prefix=PFX
!

Exec prefix where libart is installed (optional). !

!
!
--disable-libarttest
!

Do not try to compile and run a test libart program. !

!
!
! !

Overriding configure test results

!

Sometimes, it might be necessary to override the result of some ! configure test, for example in order to ease porting to a new ! system or work around a bug in a test. The toplevel configure ! script provides three variables for this: !

!
!
build_configargs
!
!

The contents of this variable is passed to all build configure ! scripts. !

!
!
host_configargs
!
!

The contents of this variable is passed to all host configure ! scripts. !

!
!
target_configargs
!
!

The contents of this variable is passed to all target configure ! scripts. !

!
!
!

In order to avoid shell and make quoting issues for complex ! overrides, you can pass a setting for CONFIG_SITE and set ! variables in the site file. !

!
!

Return to the GCC Installation page !

- - --- 1,1293 ---- ! ! ! Installing GCC: Configuration ! ! ! ! ! ! ! ! ! !

Installing GCC: Configuration

! ! Like most GNU software, GCC must be configured before it can be built. This document describes the recommended configuration procedure for both native and cross targets. ! !

We use srcdir to refer to the toplevel source directory for GCC; we use objdir to refer to the toplevel build/object directory. ! !

If you obtained the sources via SVN, srcdir must refer to the top ! gcc directory, the one where the MAINTAINERS file can be ! found, and not its gcc subdirectory, otherwise the build will fail. ! !

If either srcdir or objdir is located on an automounted NFS ! file system, the shell's built-in pwd command will return temporary pathnames. Using these can lead to various sorts of build ! problems. To avoid this issue, set the PWDCMD environment ! variable to an automounter-aware pwd command, e.g., ! pawd or ‘amq -w’, during the configuration and build phases. ! !

First, we highly recommend that GCC be built into a separate directory from the sources which does not reside within the source tree. This is how we generally build GCC; building ! where srcdir == objdir should still work, but doesn't get extensive testing; building where objdir is a subdirectory of srcdir is unsupported. ! !

If you have previously built GCC in the same directory for a ! different target machine, do ‘make distclean’ to delete all files ! that might be invalid. One of the files this deletes is Makefile; ! if ‘make distclean’ complains that Makefile does not exist ! or issues a message like “don't know how to make distclean” it probably means that the directory is already suitably clean. However, with the recommended method of building in a separate objdir, you should simply use a different objdir for each target. ! !

Second, when configuring a native system, either cc or ! gcc must be in your path or you must set CC in your environment before running configure. Otherwise the configuration scripts may fail. !

To configure GCC: ! 

     % mkdir objdir
!      % cd objdir
!      % srcdir/configure [options] [target]
!
!

Distributor options

If you will be distributing binary versions of GCC, with modifications to the source code, you should use the options described in this section to make clear that your version contains modifications. ! !

!
--with-pkgversion=version
Specify a string that identifies your package. You may wish to include a build number or build date. This version string will be ! included in the output of gcc --version. This suffix does ! not replace the default version string, only the ‘GCC’ part. ! !

The default value is ‘GCC’. ! !

--with-bugurl=url
Specify the URL that users should visit if they wish to report a bug. You are of course welcome to forward bugs reported to you to the FSF, if you determine that they are not bugs in your modifications. !

The default value refers to the FSF's GCC bug tracker. ! !

! !

Target specification

! !
    !
  • GCC has code to correctly determine the correct value for target for nearly all native systems. Therefore, we highly recommend you do not provide a configure target when configuring a native compiler. !
  • target must be specified as --target=target when configuring a cross compiler; examples of valid targets would be m68k-elf, sh-elf, etc. !
  • Specifying just target instead of --target=target ! implies that the host defaults to target. !
!

Options specification

Use options to override several configure time options for ! GCC. A list of supported options follows; ‘configure ! --help’ may list other options, but those not listed below may not work and should not normally be used. ! !

Note that each --enable option has a corresponding ! --disable option and that each --with option has a ! corresponding --without option. ! !

!
--prefix=dirname
Specify the toplevel installation directory. This is the recommended way to install the tools into a directory other than the default. The toplevel installation directory defaults to ! /usr/local. ! !

We highly recommend against dirname being the same or a subdirectory of objdir or vice versa. If specifying a directory ! beneath a user's home directory tree, some shells will not expand ! dirname correctly if it contains the ‘~’ metacharacter; use ! $HOME instead. ! !

The following standard autoconf options are supported. Normally you should not need to use these options. !

!
--exec-prefix=dirname
Specify the toplevel installation directory for architecture-dependent files. The default is prefix. ! !
--bindir=dirname
Specify the installation directory for the executables called by users ! (such as gcc and g++). The default is ! exec-prefix/bin. ! !
--libdir=dirname
Specify the installation directory for object code libraries and ! internal data files of GCC. The default is exec-prefix/lib. ! !
--libexecdir=dirname
Specify the installation directory for internal executables of GCC. ! The default is exec-prefix/libexec. ! !
--with-slibdir=dirname
Specify the installation directory for the shared libgcc library. The default is libdir. ! !
--datarootdir=dirname
Specify the root of the directory tree for read-only architecture-independent ! data files referenced by GCC. The default is prefix/share. ! !
--infodir=dirname
Specify the installation directory for documentation in info format. ! The default is datarootdir/info. ! !
--datadir=dirname
Specify the installation directory for some architecture-independent data files referenced by GCC. The default is datarootdir. ! !
--docdir=dirname
Specify the installation directory for documentation files (other ! than Info) for GCC. The default is datarootdir/doc. ! !
--htmldir=dirname
Specify the installation directory for HTML documentation files. The default is docdir. ! !
--pdfdir=dirname
Specify the installation directory for PDF documentation files. The default is docdir. ! !
--mandir=dirname
Specify the installation directory for manual pages. The default is ! datarootdir/man. (Note that the manual pages are only extracts from the full GCC manuals, which are provided in Texinfo format. The manpages are derived by an automatic conversion process from parts of the full manual.) ! !
--with-gxx-include-dir=dirname
Specify the installation directory for G++ header files. The default depends on other configuration options, and differs between cross and native configurations. ! !
--with-specs=specs
Specify additional command line driver SPECS. This can be useful if you need to turn on a non-standard feature by ! default without modifying the compiler's source code, for instance ! --with-specs=%{!fcommon:%{!fno-common:-fno-common}}. See “Spec Files” in the main manual !
! !
--program-prefix=prefix
GCC supports some transformations of the names of its programs when installing them. This option prepends prefix to the names of programs to install in bindir (see above). For example, specifying ! --program-prefix=foo- would result in ‘gcc’ ! being installed as /usr/local/bin/foo-gcc. ! !
--program-suffix=suffix
Appends suffix to the names of programs to install in bindir ! (see above). For example, specifying --program-suffix=-3.1 ! would result in ‘gcc’ being installed as ! /usr/local/bin/gcc-3.1. ! !
--program-transform-name=pattern
Applies the ‘sed’ script pattern to be applied to the names of programs to install in bindir (see above). pattern has to ! consist of one or more basic ‘sed’ editing commands, separated by ! semicolons. For example, if you want the ‘gcc’ program name to be ! transformed to the installed program /usr/local/bin/myowngcc and ! the ‘g++’ program name to be transformed to ! /usr/local/bin/gspecial++ without changing other program names, you could use the pattern ! --program-transform-name='s/^gcc$/myowngcc/; s/^g++$/gspecial++/' to achieve this effect. ! !

All three options can be combined and used together, resulting in more complex conversion patterns. As a basic rule, prefix (and suffix) are prepended (appended) before further transformations can happen with a special transformation script pattern. ! !

As currently implemented, this option only takes effect for native ! builds; cross compiler binaries' names are not transformed even when a transformation is explicitly asked for by one of these options. ! !

For native builds, some of the installed programs are also installed with the target alias in front of their name, as in ! ‘i686-pc-linux-gnu-gcc’. All of the above transformations happen before the target alias is prepended to the name—so, specifying ! --program-prefix=foo- and program-suffix=-3.1, the resulting binary would be installed as ! /usr/local/bin/i686-pc-linux-gnu-foo-gcc-3.1. ! !

As a last shortcoming, none of the installed Ada programs are transformed yet, which will be fixed in some time. ! !

--with-local-prefix=dirname
Specify the installation directory for local include files. The default is ! /usr/local. Specify this option if you want the compiler to ! search directory dirname/include for locally installed ! header files instead of /usr/local/include. ! !

You should specify --with-local-prefix only if your ! site has a different convention (not /usr/local) for where to put site-specific files. ! !

The default value for --with-local-prefix is /usr/local ! regardless of the value of --prefix. Specifying ! --prefix has no effect on which directory GCC searches for local header files. This may seem counterintuitive, but actually it is logical. ! !

The purpose of --prefix is to specify where to install ! GCC. The local header files in /usr/local/include—if you put any in that directory—are not part of GCC. They are part of other programs—perhaps many others. (GCC installs its own header files in ! another directory which is based on the --prefix value.) ! !

Both the local-prefix include directory and the GCC-prefix include ! directory are part of GCC's “system include” directories. Although these two directories are not fixed, they need to be searched in the proper order for the correct processing of the include_next directive. The local-prefix include directory is searched before the GCC-prefix include directory. Another characteristic of system include directories is that pedantic warnings are turned off for headers in these directories. ! !

Some autoconf macros add -I directory options to the compiler command line, to ensure that directories containing installed ! packages' headers are searched. When directory is one of GCC's system include directories, GCC will ignore the option so that system directories continue to be processed in the correct order. This may result in a search order different from what was specified but the directory will still be searched. ! !

GCC automatically searches for ordinary libraries using ! GCC_EXEC_PREFIX. Thus, when the same installation prefix is used for both GCC and packages, GCC will automatically search for both headers and libraries. This provides a configuration that is easy to use. GCC behaves in a manner similar to that when it is ! installed as a system compiler in /usr. ! !

Sites that need to install multiple versions of GCC may not want to use the above simple configuration. It is possible to use the ! --program-prefix, --program-suffix and ! --program-transform-name options to install multiple versions into a single directory, but it may be simpler to use different prefixes ! and the --with-local-prefix option to specify the location of the site-specific files for each version. It will then be necessary for users to specify explicitly the location of local site libraries ! (e.g., with LIBRARY_PATH). ! !

The same value can be used for both --with-local-prefix and ! --prefix provided it is not /usr. This can be used ! to avoid the default search of /usr/local/include. ! !

Do not specify /usr as the --with-local-prefix! ! The directory you use for --with-local-prefix must not ! contain any of the system's standard header files. If it did contain them, certain programs would be miscompiled (including GNU Emacs, on certain targets), because this would override and nullify the header ! file corrections made by the fixincludes script. ! !

Indications are that people who use this option use it based on mistaken ideas of what it is for. People use it as if it specified where to install part of GCC. Perhaps they make this assumption because installing GCC creates the directory. ! !

--with-native-system-header-dir=dirname
Specifies that dirname is the directory that contains native system ! header files, rather than /usr/include. This option is most useful if you are creating a compiler that should be isolated from the system as much as possible. It is most commonly used with the ! --with-sysroot option and will cause GCC to search dirname inside the system root specified by that option. ! !
--enable-shared[=package[,...]]
Build shared versions of libraries, if shared libraries are supported on the target platform. Unlike GCC 2.95.x and earlier, shared libraries are enabled by default on all platforms that support shared libraries. ! !

If a list of packages is given as an argument, build shared libraries only for the listed packages. For other packages, only static libraries will be built. Package names currently recognized in the GCC tree are ! ‘libgcc’ (also known as ‘gcc’), ‘libstdc++’ (not ! ‘libstdc++-v3’), ‘libffi’, ‘zlib’, ‘boehm-gc’, ! ‘ada’, ‘libada’, ‘libjava’, ‘libgo’, and ‘libobjc’. ! Note ‘libiberty’ does not support shared libraries at all. ! !

Use --disable-shared to build only static libraries. Note that ! --disable-shared does not accept a list of package names as ! argument, only --enable-shared does. ! !

--with-gnu-as
Specify that the compiler should assume that the assembler it finds is the GNU assembler. However, this does not modify the rules to find an assembler and will result in confusion if the assembler found is not actually the GNU assembler. (Confusion may also result if the compiler finds the GNU assembler but has not been ! configured with --with-gnu-as.) If you have more than one assembler installed on your system, you may want to use this option in ! connection with --with-as=pathname or ! --with-build-time-tools=pathname. ! !

The following systems are the only ones where it makes a difference whether you use the GNU assembler. On any other system, ! --with-gnu-as has no effect. !

    !
  • ‘hppa1.0-any-any’ !
  • ‘hppa1.1-any-any’ !
  • ‘sparc-sun-solaris2.any’ !
  • ‘sparc64-any-solaris2.any’ !
! !
--with-as=pathname
Specify that the compiler should use the assembler pointed to by pathname, rather than the one found by the standard rules to find an assembler, which are: !
    !
  • Unless GCC is being built with a cross compiler, check the ! libexec/gcc/target/version directory. ! libexec defaults to exec-prefix/libexec; exec-prefix defaults to prefix, which ! defaults to /usr/local unless overridden by the ! --prefix=pathname switch described above. target ! is the target system triple, such as ‘sparc-sun-solaris2.7’, and version denotes the GCC version, such as 3.0. !
  • If the target system is the same that you are building on, check ! operating system specific directories (e.g. /usr/ccs/bin on Sun Solaris 2). !
  • Check in the PATH for a tool whose name is prefixed by the target system triple. !
  • Check in the PATH for a tool whose name is not prefixed by the target system triple, if the host and target system triple are the same (in other words, we use a host tool if it can be used for ! the target as well). !
!

You may want to use --with-as if no assembler is installed in the directories listed above, or if you have multiple assemblers installed and want to choose one that is not found by the above rules. ! !

--with-gnu-ld
Same as --with-gnu-as but for the linker. ! !
--with-ld=pathname
Same as --with-as but for the linker. ! !
--with-stabs
Specify that stabs debugging information should be used instead of whatever format the host normally uses. Normally GCC uses the same debug format as the host system. ! !

On MIPS based systems and on Alphas, you must specify whether you want GCC to create the normal ECOFF debugging format, or to use BSD-style stabs passed through the ECOFF symbol table. The normal ECOFF debug format cannot fully handle languages other than C. BSD stabs format can handle other languages, but it only works with the GNU debugger GDB. ! !

Normally, GCC uses the ECOFF debugging format by default; if you ! prefer BSD stabs, specify --with-stabs when you configure GCC. ! !

No matter which default you choose when you configure GCC, the user ! can use the -gcoff and -gstabs+ options to specify explicitly the debug format for a particular compilation. ! !

--with-stabs is meaningful on the ISC system on the 386, also, if ! --with-gas is used. It selects use of stabs debugging information embedded in COFF output. This kind of debugging information supports C++ well; ordinary COFF debugging information does not. ! !

--with-stabs is also meaningful on 386 systems running SVR4. It selects use of stabs debugging information embedded in ELF output. The C++ compiler currently (2.6.0) does not support the DWARF debugging information normally used on 386 SVR4 platforms; stabs provide a workable alternative. This requires gas and gdb, as the normal SVR4 tools can not generate or interpret stabs. ! !

--with-tls=dialect
Specify the default TLS dialect, for systems were there is a choice. For ARM targets, possible values for dialect are gnu or gnu2, which select between the original GNU dialect and the GNU TLS descriptor-based dialect. ! !
--enable-multiarch
Specify whether to enable or disable multiarch support. The default is to check for glibc start files in a multiarch location, and enable it if the files are found. The auto detection is enabled for native builds, ! and for cross builds configured with --with-sysroot, and without ! --with-native-system-header-dir. More documentation about multiarch can be found at http://wiki.debian.org/Multiarch. ! !
--disable-multilib
Specify that multiple target libraries to support different target variants, calling conventions, etc. should not be built. The default is to build a predefined set of them. ! !

Some targets provide finer-grained control over which multilibs are built ! (e.g., --disable-softfloat): !

!
arm-*-*
fpu, 26bit, underscore, interwork, biendian, nofmult. ! !
m68*-*-*
softfloat, m68881, m68000, m68020. ! !
mips*-*-*
single-float, biendian, softfloat. ! !
powerpc*-*-*, rs6000*-*-*
aix64, pthread, softfloat, powercpu, powerpccpu, powerpcos, biendian, sysv, aix. !
! !
--with-multilib-list=list
--without-multilib-list
Specify what multilibs to build. Currently only implemented for sh*-*-* and x86-64-*-linux*. ! !
!
sh*-*-*
list is a comma separated list of CPU names. These must be of the form sh* or m* (in which case they match the compiler option for that processor). The list should not contain any endian options - ! these are handled by --with-endian. ! !

If list is empty, then there will be no multilibs for extra processors. The multilib for the secondary endian remains enabled. ! !

As a special case, if an entry in the list starts with a ! ! (exclamation point), then it is added to the list of excluded multilibs. ! Entries of this sort should be compatible with ‘MULTILIB_EXCLUDES’ (once the leading ! has been stripped). ! !

If --with-multilib-list is not given, then a default set of ! multilibs is selected based on the value of --target. This is usually the complete set of libraries, but some targets imply a more specialized subset. !

Example 1: to configure a compiler for SH4A only, but supporting both ! endians, with little endian being the default: ! 

               --with-cpu=sh4a --with-endian=little,big --with-multilib-list=
!
!

Example 2: to configure a compiler for both SH4A and SH4AL-DSP, but with only little endian SH4AL: ! 

               --with-cpu=sh4a --with-endian=little,big \
!                --with-multilib-list=sh4al,!mb/m4al
!
!
x86-64-*-linux*
list is a comma separated list of m32, m64 and mx32 to enable 32-bit, 64-bit and x32 run-time libraries, respectively. If list is empty, then there will be no multilibs and only the default run-time library will be enabled. ! !

If --with-multilib-list is not given, then only 32-bit and ! 64-bit run-time libraries will be enabled.

!
--with-endian=endians
Specify what endians to use. Currently only implemented for sh*-*-*. ! !

endians may be one of the following: !

!
big
Use big endian exclusively. !
little
Use little endian exclusively. !
big,little
Use big endian by default. Provide a multilib for little endian. !
little,big
Use little endian by default. Provide a multilib for big endian.
!
--enable-threads
Specify that the target supports threads. This affects the Objective-C compiler and runtime ! library, and exception handling for other languages like C++ and Java. On some systems, this is the default. ! !

In general, the best (and, in many cases, the only known) threading model available will be configured for use. Beware that on some systems, GCC has not been taught what threading models are generally ! available for the system. In this case, --enable-threads is an ! alias for --enable-threads=single. ! !

--disable-threads
Specify that threading support should be disabled for the system. ! This is an alias for --enable-threads=single. ! !
--enable-threads=lib
Specify that lib is the thread support library. This affects the Objective-C compiler and runtime library, and exception handling for other languages like C++ and Java. The possibilities for lib are: ! !
!
aix
AIX thread support. !
dce
DCE thread support. !
lynx
LynxOS thread support. !
mipssde
MIPS SDE thread support. !
no
This is an alias for ‘single’. !
posix
Generic POSIX/Unix98 thread support. !
rtems
RTEMS thread support. !
single
Disable thread support, should work for all platforms. !
tpf
TPF thread support. !
vxworks
VxWorks thread support. !
win32
Microsoft Win32 API thread support.
!
--enable-tls
Specify that the target supports TLS (Thread Local Storage). Usually configure can correctly determine if TLS is supported. In cases where it guesses incorrectly, TLS can be explicitly enabled or disabled with ! --enable-tls or --disable-tls. This can happen if the assembler supports TLS but the C library does not, or if the assumptions made by the configure test are incorrect. ! !
--disable-tls
Specify that the target does not support TLS. ! This is an alias for --enable-tls=no. ! !
--with-cpu=cpu
--with-cpu-32=cpu
--with-cpu-64=cpu
Specify which cpu variant the compiler should generate code for by default. ! cpu will be used as the default value of the -mcpu= switch. This option is only supported on some targets, including ARM, i386, M68k, ! PowerPC, and SPARC. The --with-cpu-32 and ! --with-cpu-64 options specify separate default CPUs for 32-bit and 64-bit modes; these options are only supported for i386, x86-64 and PowerPC. ! !
--with-schedule=cpu
--with-arch=cpu
--with-arch-32=cpu
--with-arch-64=cpu
--with-tune=cpu
--with-tune-32=cpu
--with-tune-64=cpu
--with-abi=abi
--with-fpu=type
--with-float=type
These configure options provide default values for the -mschedule=, ! -march=, -mtune=, -mabi=, and -mfpu= ! options and for -mhard-float or -msoft-float. As with ! --with-cpu, which switches will be accepted and acceptable values of the arguments depend on the target. ! !
--with-mode=mode
Specify if the compiler should default to -marm or -mthumb. This option is only supported on ARM targets. ! !
--with-stack-offset=num
This option sets the default for the -mstack-offset=num option, and will thus generally also control the setting of this option for libraries. This option is only supported on Epiphany targets. ! !
--with-fpmath=isa
This options sets -mfpmath=sse by default and specifies the default ! ISA for floating-point arithmetics. You can select either ‘sse’ which ! enables -msse2 or ‘avx’ which enables -mavx by default. This option is only supported on i386 and x86-64 targets. ! !
--with-divide=type
Specify how the compiler should generate code for checking for ! division by zero. This option is only supported on the MIPS target. The possibilities for type are: !
!
traps
Division by zero checks use conditional traps (this is the default on ! systems that support conditional traps). !
breaks
Division by zero checks use the break instruction.
! ! !
--with-llsc
On MIPS targets, make -mllsc the default when no ! -mno-llsc option is passed. This is the default for Linux-based targets, as the kernel will emulate them if the ISA does not provide them. ! !
--without-llsc
On MIPS targets, make -mno-llsc the default when no ! -mllsc option is passed. ! !
--with-synci
On MIPS targets, make -msynci the default when no ! -mno-synci option is passed. ! !
--without-synci
On MIPS targets, make -mno-synci the default when no ! -msynci option is passed. This is the default. ! !
--with-mips-plt
On MIPS targets, make use of copy relocations and PLTs. These features are extensions to the traditional SVR4-based MIPS ABIs and require support from GNU binutils and the runtime C library. ! !
--enable-__cxa_atexit
Define if you want to use __cxa_atexit, rather than atexit, to ! register C++ destructors for local statics and global objects. This is essential for fully standards-compliant handling of destructors, but requires __cxa_atexit in libc. This option is currently only available on systems with GNU libc. When enabled, this will cause ! -fuse-cxa-atexit to be passed by default. ! !
--enable-gnu-indirect-function
Define if you want to enable the ifunc attribute. This option is currently only available on systems with GNU libc on certain targets. ! !
--enable-target-optspace
Specify that target ! libraries should be optimized for code space instead of code speed. This is the default for the m32r platform. ! !
--with-cpp-install-dir=dirname
Specify that the user visible cpp program should be installed ! in prefix/dirname/cpp, in addition to bindir. ! !
--enable-comdat
Enable COMDAT group support. This is primarily used to override the automatically detected value. ! !
--enable-initfini-array
Force the use of sections .init_array and .fini_array (instead of .init and .fini) for constructors and ! destructors. Option --disable-initfini-array has the opposite effect. If neither option is specified, the configure script will try to guess whether the .init_array and .fini_array sections are supported and, if they are, use them. ! !
--enable-maintainer-mode
The build rules that regenerate the Autoconf and Automake output files as ! well as the GCC master message catalog gcc.pot are normally disabled. This is because it can only be rebuilt if the complete source tree is present. If you have changed the sources and want to rebuild the ! catalog, configuring with --enable-maintainer-mode will enable this. Note that you need a recent version of the gettext tools to do so. ! !
--disable-bootstrap
For a native build, the default configuration is to perform ! a 3-stage bootstrap of the compiler when ‘make’ is invoked, testing that GCC can compile itself correctly. If you want to disable ! this process, you can configure with --disable-bootstrap. ! !
--enable-bootstrap
In special cases, you may want to perform a 3-stage build ! even if the target and host triplets are different. This is possible when the host can run code compiled for ! the target (e.g. host is i686-linux, target is i486-linux). Starting from GCC 4.2, to do this you have to configure explicitly ! with --enable-bootstrap. ! !
--enable-generated-files-in-srcdir
Neither the .c and .h files that are generated from Bison and flex nor the info manuals and man pages that are built from the .texi files are present in the SVN development tree. When building GCC from that development tree, or from one of our snapshots, those generated files are placed in your build directory, which allows for the source to be in a readonly directory. ! !

If you configure with --enable-generated-files-in-srcdir then those generated files will go into the source directory. This is mainly intended for generating release or prerelease tarballs of the GCC sources, since it is not a requirement that the users of source releases to have flex, Bison, or makeinfo. ! !

--enable-version-specific-runtime-libs
Specify that runtime libraries should be installed in the compiler specific ! subdirectory (libdir/gcc) rather than the usual places. In ! addition, ‘libstdc++’'s include files will be installed into libdir unless you overruled it by using ! --with-gxx-include-dir=dirname. Using this option is particularly useful if you intend to use several versions of GCC in ! parallel. This is currently supported by ‘libgfortran’, ! ‘libjava’, ‘libmudflap’, ‘libstdc++’, and ‘libobjc’. ! !
--enable-languages=lang1,lang2,...
Specify that only a particular subset of compilers and their runtime libraries should be built. For a list of valid values for langN you can issue the following command in the ! gcc directory of your GCC source tree:
! 
          grep language= */config-lang.in
!
!

Currently, you can use any of the following: all, ada, c, c++, fortran, ! go, java, objc, obj-c++. ! Building the Ada compiler has special requirements, see below. If you do not pass this flag, or specify the option all, then all ! default languages available in the gcc sub-tree will be configured. Ada, Go and Objective-C++ are not default languages; the rest are. ! !

--enable-stage1-languages=lang1,lang2,...
Specify that a particular subset of compilers and their runtime libraries should be built with the system C compiler during stage 1 of the bootstrap process, rather than only in later stages with the bootstrapped C compiler. The list of valid values is the same as for ! --enable-languages, and the option all will select all ! of the languages enabled by --enable-languages. This option is primarily useful for GCC development; for instance, when a development version of the compiler cannot bootstrap due to compiler bugs, or when one is debugging front ends other than the C front end. When this option is used, one can then build the target libraries for the ! specified languages with the stage-1 compiler by using make ! stage1-bubble all-target, or run the testsuite on the stage-1 compiler ! for the specified languages using make stage1-start check-gcc. ! !
--disable-libada
Specify that the run-time libraries and tools used by GNAT should not be built. This can be useful for debugging, or for compatibility with previous Ada build procedures, when it was required to explicitly ! do a ‘make -C gcc gnatlib_and_tools’. ! !
--disable-libssp
Specify that the run-time libraries for stack smashing protection should not be built. ! !
--disable-libquadmath
Specify that the GCC quad-precision math library should not be built. On some systems, the library is required to be linkable when building ! the Fortran front end, unless --disable-libquadmath-support is used. ! !
--disable-libquadmath-support
Specify that the Fortran front end and libgfortran do not add support for libquadmath on systems supporting it. ! !
--disable-libgomp
Specify that the run-time libraries used by GOMP should not be built. ! !
--with-dwarf2
Specify that the compiler should use DWARF 2 debugging information as the default. ! !
--enable-targets=all
--enable-targets=target_list
Some GCC targets, e.g. powerpc64-linux, build bi-arch compilers. These are compilers that are able to generate either 64-bit or 32-bit ! code. Typically, the corresponding 32-bit target, e.g. powerpc-linux for powerpc64-linux, only generates 32-bit code. This option enables the 32-bit target to be a bi-arch compiler, which is useful when you want a bi-arch compiler that defaults to 32-bit, and ! you are building a bi-arch or multi-arch binutils in a combined tree. On mips-linux, this will build a tri-arch compiler (ABI o32/n32/64), ! defaulted to o32. Currently, this option only affects sparc-linux, powerpc-linux, x86-linux, mips-linux and s390-linux. ! !
--enable-secureplt
This option enables -msecure-plt by default for powerpc-linux. See “RS/6000 and PowerPC Options” in the main manual ! !
--enable-cld
This option enables -mcld by default for 32-bit x86 targets. See “i386 and x86-64 Options” in the main manual ! !
--enable-win32-registry
--enable-win32-registry=key
--disable-win32-registry
The --enable-win32-registry option enables Microsoft Windows-hosted GCC to look up installations paths in the registry using the following key: ! 
          HKEY_LOCAL_MACHINE\SOFTWARE\Free Software Foundation\key
!
!

key defaults to GCC version number, and can be overridden by the ! --enable-win32-registry=key option. Vendors and distributors who use custom installers are encouraged to provide a different key, perhaps one comprised of vendor name and GCC version number, to avoid conflict with existing installations. This feature is enabled ! by default, and can be disabled by --disable-win32-registry option. This option has no effect on the other hosts. ! !

--nfp
Specify that the machine does not have a floating point unit. This ! option only applies to ‘m68k-sun-sunosn’. On any other ! system, --nfp has no effect. ! !
--enable-werror
--disable-werror
--enable-werror=yes
--enable-werror=no
When you specify this option, it controls whether certain files in the ! compiler are built with -Werror in bootstrap stage2 and later. ! If you don't specify it, -Werror is turned on for the main development trunk. However it defaults to off for release branches and ! final releases. The specific files which get -Werror are controlled by the Makefiles. ! !
--enable-checking
--enable-checking=list
When you specify this option, the compiler is built to perform internal consistency checks of the requested complexity. This does not change the generated code, but adds error checking within the compiler. This will slow down the compiler and may only work properly if you are building ! the compiler with GCC. This is ‘yes’ by default when building ! from SVN or snapshots, but ‘release’ for releases. The default ! for building the stage1 compiler is ‘yes’. More control over the checks may be had by specifying list. The categories of ! checks available are ‘yes’ (most common checks ! ‘assert,misc,tree,gc,rtlflag,runtime’), ‘no’ (no checks at ! all), ‘all’ (all but ‘valgrind’), ‘release’ (cheapest ! checks ‘assert,runtime’) or ‘none’ (same as ‘no’). ! Individual checks can be enabled with these flags ‘assert’, ! ‘df’, ‘fold’, ‘gc’, ‘gcac’ ‘misc’, ‘rtl’, ! ‘rtlflag’, ‘runtime’, ‘tree’, and ‘valgrind’. ! !

The ‘valgrind’ check requires the external valgrind simulator, available from http://valgrind.org/. The ! ‘df’, ‘rtl’, ‘gcac’ and ‘valgrind’ checks are very expensive. ! To disable all checking, ‘--disable-checking’ or ! ‘--enable-checking=none’ must be explicitly requested. Disabling assertions will make the compiler and runtime slightly faster but increase the risk of undetected internal errors causing wrong code to be generated. ! !

--disable-stage1-checking
--enable-stage1-checking
--enable-stage1-checking=list
If no --enable-checking option is specified the stage1 ! compiler will be built with ‘yes’ checking enabled, otherwise the stage1 checking flags are the same as specified by ! --enable-checking. To build the stage1 compiler with ! different checking options use --enable-stage1-checking. ! The list of checking options is the same as for --enable-checking. If your system is too slow or too small to bootstrap a released compiler ! with checking for stage1 enabled, you can use ‘--disable-stage1-checking’ to disable checking for the stage1 compiler. ! !
--enable-coverage
--enable-coverage=level
With this option, the compiler is built to collect self coverage information, every time it is run. This is for internal development purposes, and only works when the compiler is being built with gcc. The level argument controls whether the compiler is built optimized or ! not, values are ‘opt’ and ‘noopt’. For coverage analysis you want to disable optimization, for performance analysis you want to enable optimization. When coverage is enabled, the default level is without optimization. ! !
--enable-gather-detailed-mem-stats
When this option is specified more detailed information on memory allocation is gathered. This information is printed when using ! -fmem-report. ! !
--enable-nls
--disable-nls
The --enable-nls option enables Native Language Support (NLS), which lets GCC output diagnostics in languages other than American English. Native Language Support is enabled by default if not doing a ! canadian cross build. The --disable-nls option disables NLS. ! !
--with-included-gettext
If NLS is enabled, the --with-included-gettext option causes the build ! procedure to prefer its copy of GNU gettext. ! !
--with-catgets
If NLS is enabled, and if the host lacks gettext but has the inferior catgets interface, the GCC build procedure normally ! ignores catgets and instead uses GCC's copy of the GNU ! gettext library. The --with-catgets option causes the ! build procedure to use the host's catgets in this situation. ! !
--with-libiconv-prefix=dir
Search for libiconv header files in dir/include and ! libiconv library files in dir/lib. ! !
--enable-obsolete
Enable configuration for an obsoleted system. If you attempt to configure GCC for a system (build, host, or target) which has been obsoleted, and you do not specify this flag, configure will halt with an error message. ! !

All support for systems which have been obsoleted in one release of GCC is removed entirely in the next major release, unless someone steps forward to maintain the port. ! !

--enable-decimal-float
--enable-decimal-float=yes
--enable-decimal-float=no
--enable-decimal-float=bid
--enable-decimal-float=dpd
--disable-decimal-float
Enable (or disable) support for the C decimal floating point extension that is in the IEEE 754-2008 standard. This is enabled by default only on PowerPC, i386, and x86_64 GNU/Linux systems. Other systems may also support it, but require the user to specifically enable it. You can optionally control which decimal floating point format is used (either ! ‘bid’ or ‘dpd’). The ‘bid’ (binary integer decimal) ! format is default on i386 and x86_64 systems, and the ‘dpd’ (densely packed decimal) format is default on PowerPC systems. ! !
--enable-fixed-point
--disable-fixed-point
Enable (or disable) support for C fixed-point arithmetic. This option is enabled by default for some targets (such as MIPS) which have hardware-support for fixed-point operations. On other targets, you may enable this option manually. ! !
--with-long-double-128
Specify if long double type should be 128-bit by default on selected GNU/Linux architectures. If using --without-long-double-128, ! long double will be by default 64-bit, the same as double type. When neither of these configure options are used, the default will be 128-bit long double when built against GNU C Library 2.4 and later, 64-bit long double otherwise. ! !
--with-gmp=pathname
--with-gmp-include=pathname
--with-gmp-lib=pathname
--with-mpfr=pathname
--with-mpfr-include=pathname
--with-mpfr-lib=pathname
--with-mpc=pathname
--with-mpc-include=pathname
--with-mpc-lib=pathname
If you want to build GCC but do not have the GMP library, the MPFR library and/or the MPC library installed in a standard location and do not have their sources present in the GCC source tree then you can explicitly specify the directory where they are installed ! (‘--with-gmp=gmpinstalldir’, ! ‘--with-mpfr=mpfrinstalldir’, ! ‘--with-mpc=mpcinstalldir’). The ! --with-gmp=gmpinstalldir option is shorthand for ! --with-gmp-lib=gmpinstalldir/lib and ! --with-gmp-include=gmpinstalldir/include. Likewise the ! --with-mpfr=mpfrinstalldir option is shorthand for ! --with-mpfr-lib=mpfrinstalldir/lib and ! --with-mpfr-include=mpfrinstalldir/include, also the ! --with-mpc=mpcinstalldir option is shorthand for ! --with-mpc-lib=mpcinstalldir/lib and ! --with-mpc-include=mpcinstalldir/include. If these shorthand assumptions are not correct, you can use the explicit include and lib options directly. You might also need to ensure the shared libraries can be found by the dynamic linker when building and using GCC, for example by setting the runtime shared library path ! variable (LD_LIBRARY_PATH on GNU/Linux and Solaris systems). ! !

These flags are applicable to the host platform only. When building a cross compiler, they will not be used to configure target libraries. ! !

--with-isl=pathname
--with-isl-include=pathname
--with-isl-lib=pathname
--with-cloog=pathname
--with-cloog-include=pathname
--with-cloog-lib=pathname
If you do not have ISL and the CLooG libraries installed in a standard location and you want to build GCC, you can explicitly specify the directory where they are installed ! (‘--with-isl=islinstalldir’, ! ‘--with-cloog=clooginstalldir’). The ! --with-isl=islinstalldir option is shorthand for ! --with-isl-lib=islinstalldir/lib and ! --with-isl-include=islinstalldir/include. Likewise the ! --with-cloog=clooginstalldir option is shorthand for ! --with-cloog-lib=clooginstalldir/lib and ! --with-cloog-include=clooginstalldir/include. If these shorthand assumptions are not correct, you can use the explicit include and lib options directly. ! !

These flags are applicable to the host platform only. When building a cross compiler, they will not be used to configure target libraries. ! !

--with-host-libstdcxx=linker-args
If you are linking with a static copy of PPL, you can use this option to specify how the linker should find the standard C++ library used internally by PPL. Typical values of linker-args might be ! ‘-lstdc++’ or ‘-Wl,-Bstatic,-lstdc++,-Bdynamic -lm’. If you are linking with a shared copy of PPL, you probably do not need this option; shared library dependencies will cause the linker to search for the standard C++ library automatically. ! !
--with-stage1-ldflags=flags
This option may be used to set linker flags to be used when linking stage 1 of GCC. These are also used when linking GCC if configured with ! --disable-bootstrap. By default no special flags are used. ! !
--with-stage1-libs=libs
This option may be used to set libraries to be used when linking stage 1 of GCC. These are also used when linking GCC if configured with ! --disable-bootstrap. The default is the argument to ! --with-host-libstdcxx, if specified. ! !
--with-boot-ldflags=flags
This option may be used to set linker flags to be used when linking stage 2 and later when bootstrapping GCC. If neither –with-boot-libs nor –with-host-libstdcxx is set to a value, then the default is ! ‘-static-libstdc++ -static-libgcc’. ! !
--with-boot-libs=libs
This option may be used to set libraries to be used when linking stage 2 and later when bootstrapping GCC. The default is the argument to ! --with-host-libstdcxx, if specified. ! !
--with-debug-prefix-map=map
Convert source directory names using -fdebug-prefix-map when building runtime libraries. ‘map’ is a space-separated ! list of maps of the form ‘old=new’. ! !
--enable-linker-build-id
Tells GCC to pass --build-id option to the linker for all final ! links (links performed without the -r or --relocatable option), if the linker supports it. If you specify ! --enable-linker-build-id, but your linker does not ! support --build-id option, a warning is issued and the ! --enable-linker-build-id option is ignored. The default is off. ! !
--with-linker-hash-style=choice
Tells GCC to pass --hash-style=choice option to the linker for all final links. choice can be one of ! ‘sysv’, ‘gnu’, and ‘both’ where ‘sysv’ is the default. ! !
--enable-gnu-unique-object
--disable-gnu-unique-object
Tells GCC to use the gnu_unique_object relocation for C++ template static data members and inline function local statics. Enabled by default for a native toolchain with an assembler that accepts it and GLIBC 2.11 or above, otherwise disabled. ! !
--enable-lto
--disable-lto
Enable support for link-time optimization (LTO). This is enabled by ! default, and may be disabled using --disable-lto. ! !
--with-plugin-ld=pathname
Enable an alternate linker to be used at link-time optimization (LTO) ! link time when -fuse-linker-plugin is enabled. This linker should have plugin support such as gold starting with ! version 2.20 or GNU ld starting with version 2.21. ! See -fuse-linker-plugin for details. ! !
--enable-canonical-system-headers
--disable-canonical-system-headers
Enable system header path canonicalization for libcpp. This can produce shorter header file paths in diagnostics and dependency output files, but these changed header paths may conflict with some compilation environments. Enabled by default, and may be disabled using ! --disable-canonical-system-headers.
!

Cross-Compiler-Specific Options

!

The following options only apply to building cross compilers. ! !

!
--with-sysroot
--with-sysroot=dir
Tells GCC to consider dir as the root of a tree that contains ! (a subset of) the root filesystem of the target operating system. Target system headers, libraries and run-time object files will be searched for in there. More specifically, this acts as if ! --sysroot=dir was added to the default options of the built compiler. The specified directory is not copied into the ! install tree, unlike the options --with-headers and ! --with-libs that this option obsoletes. The default value, ! in case --with-sysroot is not given an argument, is ! ${gcc_tooldir}/sys-root. If the specified directory is a ! subdirectory of ${exec_prefix}, then it will be found relative to the GCC binaries if the installation tree is moved. ! !

This option affects the system root for the compiler used to build target libraries (which runs on the build system) and the compiler newly installed with make install; it does not affect the compiler which is used to build GCC itself. ! !

If you specify the --with-native-system-header-dir=dirname option then the compiler will search that directory within dirname for ! native system headers rather than the default /usr/include. ! !

--with-build-sysroot
--with-build-sysroot=dir
Tells GCC to consider dir as the system root (see ! --with-sysroot) while building target libraries, instead of ! the directory specified with --with-sysroot. This option is ! only useful when you are already using --with-sysroot. You ! can use --with-build-sysroot when you are configuring with ! --prefix set to a directory that is different from the one in which you are installing GCC and your target libraries. ! !

This option affects the system root for the compiler used to build target libraries (which runs on the build system); it does not affect the compiler which is used to build GCC itself. ! !

If you specify the --with-native-system-header-dir=dirname option then the compiler will search that directory within dirname for ! native system headers rather than the default /usr/include. ! !

--with-headers
--with-headers=dir
Deprecated in favor of --with-sysroot. ! Specifies that target headers are available when building a cross compiler. The dir argument specifies a directory which has the target include ! files. These include files will be copied into the gcc install ! directory. This option with the dir argument is required when ! building a cross compiler, if prefix/target/sys-include ! doesn't pre-exist. If prefix/target/sys-include does ! pre-exist, the dir argument may be omitted. fixincludes will be run on these files to make them compatible with GCC. ! !
--without-headers
Tells GCC not use any target headers from a libc when building a cross compiler. When crossing to GNU/Linux, you need the headers so GCC can build the exception handling for libgcc. ! !
--with-libs
--with-libs="dir1 dir2 ... dirN"
Deprecated in favor of --with-sysroot. Specifies a list of directories which contain the target runtime ! libraries. These libraries will be copied into the gcc install directory. If the directory list is omitted, this option has no effect. ! !
--with-newlib
Specifies that ‘newlib’ is being used as the target C library. This causes __eprintf to be ! omitted from libgcc.a on the assumption that it will be provided by ! ‘newlib’. ! !
--with-avrlibc
Specifies that ‘AVR-Libc’ is being used as the target C library. This causes float support ! functions like __addsf3 to be omitted from libgcc.a on ! the assumption that it will be provided by libm.a. For more ! technical details, cf. PR54461. This option is only supported for the AVR target. It is not supported for RTEMS configurations, which currently use newlib. The option is supported since version 4.7.2 and is the default in 4.8.0 and newer. ! !
--with-build-time-tools=dir
Specifies where to find the set of target tools (assembler, linker, etc.) that will be used while building GCC itself. This option can be useful if the directory layouts are different between the system you are building GCC on, and the system where you will deploy it. ! !

For example, on an ‘ia64-hp-hpux’ system, you may have the GNU ! assembler and linker in /usr/bin, and the native tools in a different path, and build a toolchain that expects to find the ! native tools in /usr/bin. ! !

When you use this option, you should ensure that dir includes ! ar, as, ld, nm, ! ranlib and strip if necessary, and possibly ! objdump. Otherwise, GCC may use an inconsistent set of ! tools.

!

Java-Specific Options

The following option applies to the build of the Java front end. ! !

!
--disable-libgcj
Specify that the run-time libraries used by GCJ should not be built. This is useful in case you intend ! to use GCJ with some other run-time, or you're going to install it separately, or it just happens not to build on your particular machine. In general, if the Java front end is enabled, the GCJ ! libraries will be enabled too, unless they're known to not work on ! the target platform. If GCJ is enabled but ‘libgcj’ isn't built, you may need to port it; in this case, before modifying the top-level ! configure.in so that ‘libgcj’ is enabled by default on this platform, ! you may use --enable-libgcj to override the default. !
!

The following options apply to building ‘libgcj’. ! !

General Options
! !
!
--enable-java-maintainer-mode
By default the ‘libjava’ build will not attempt to compile the ! .java source files to .class. Instead, it will use the ! .class files from the source tree. If you use this option you ! must have executables named ecj1 and gjavah in your path for use by the build. You must use this option if you intend to ! modify any .java files in libjava. ! !
--with-java-home=dirname
This ‘libjava’ option overrides the default value of the ! ‘java.home’ system property. It is also used to set ! ‘sun.boot.class.path’ to dirname/lib/rt.jar. By ! default ‘java.home’ is set to prefix and ! ‘sun.boot.class.path’ to ! datadir/java/libgcj-version.jar. ! !
--with-ecj-jar=filename
This option can be used to specify the location of an external jar file containing the Eclipse Java compiler. A specially modified ! version of this compiler is used by gcj to parse ! .java source files. If this option is given, the ! ‘libjava’ build will create and install an ecj1 executable which uses this jar file at runtime. ! !

If this option is not given, but an ecj.jar file is found in ! the topmost source tree at configure time, then the ‘libgcj’ ! build will create and install ecj1, and will also install the ! discovered ecj.jar into a suitable place in the install tree. ! !

If ecj1 is not installed, then the user will have to supply one ! on his path in order for gcj to properly parse .java source files. A suitable jar is available from ftp://sourceware.org/pub/java/. ! !

--disable-getenv-properties
Don't set system properties from GCJ_PROPERTIES. ! !
--enable-hash-synchronization
Use a global hash table for monitor locks. Ordinarily, ! ‘libgcj’'s ‘configure’ script automatically makes the correct choice for this option for your platform. Only use this if you know you need the library to be configured differently. ! !
--enable-interpreter
Enable the Java interpreter. The interpreter is automatically enabled by default on all platforms that support it. This option is really only useful if you want to disable the interpreter ! (using --disable-interpreter). ! !
--disable-java-net
Disable java.net. This disables the native part of java.net only, using non-functional stubs for native method implementations. ! !
--disable-jvmpi
Disable JVMPI support. ! !
--disable-libgcj-bc
Disable BC ABI compilation of certain parts of libgcj. By default, ! some portions of libgcj are compiled with -findirect-dispatch ! and -fno-indirect-classes, allowing them to be overridden at run-time. ! !

If --disable-libgcj-bc is specified, libgcj is built without these options. This allows the compile-time linker to resolve dependencies when statically linking to libgcj. However it makes it impossible to override the affected portions of libgcj at run-time. ! !

--enable-reduced-reflection
Build most of libgcj with -freduced-reflection. This reduces the size of libgcj at the expense of not being able to do accurate reflection on the classes it contains. This option is safe if you know that code using libgcj will never use reflection on the standard runtime classes in libgcj (including using serialization, RMI or CORBA). ! !
--with-ecos
Enable runtime eCos target support. ! !
--without-libffi
Don't use ‘libffi’. This will disable the interpreter and JNI ! support as well, as these require ‘libffi’ to work. ! !
--enable-libgcj-debug
Enable runtime debugging code. ! !
--enable-libgcj-multifile
If specified, causes all .java source files to be ! compiled into .class files in one invocation of ! ‘gcj’. This can speed up build time, but is more resource-intensive. If this option is unspecified or ! disabled, ‘gcj’ is invoked once for each .java ! file to compile into a .class file. ! !
--with-libiconv-prefix=DIR
Search for libiconv in DIR/include and DIR/lib. ! !
--enable-sjlj-exceptions
Force use of the setjmp/longjmp-based scheme for exceptions. ! ‘configure’ ordinarily picks the correct value based on the platform. Only use this option if you are sure you need a different setting. ! !
--with-system-zlib
Use installed ‘zlib’ rather than that included with GCC. ! !
--with-win32-nlsapi=ansi, unicows or unicode
Indicates how MinGW ‘libgcj’ translates between UNICODE characters and the Win32 API. ! !
--enable-java-home
If enabled, this creates a JPackage compatible SDK environment during install. Note that if –enable-java-home is used, –with-arch-directory=ARCH must also be specified. ! !
--with-arch-directory=ARCH
Specifies the name to use for the jre/lib/ARCH directory in the SDK environment created when –enable-java-home is passed. Typical names for this directory include i386, amd64, ia64, etc. ! !
--with-os-directory=DIR
Specifies the OS directory for the SDK include directory. This is set to auto ! detect, and is typically 'linux'. ! !
--with-origin-name=NAME
Specifies the JPackage origin name. This defaults to the 'gcj' in java-1.5.0-gcj. ! !
--with-arch-suffix=SUFFIX
Specifies the suffix for the sdk directory. Defaults to the empty string. ! Examples include '.x86_64' in 'java-1.5.0-gcj-1.5.0.0.x86_64'. ! !
--with-jvm-root-dir=DIR
Specifies where to install the SDK. Default is $(prefix)/lib/jvm. ! !
--with-jvm-jar-dir=DIR
Specifies where to install jars. Default is $(prefix)/lib/jvm-exports. ! !
--with-python-dir=DIR
Specifies where to install the Python modules used for aot-compile. DIR should not include the prefix used in installation. For example, if the Python modules are to be installed in /usr/lib/python2.5/site-packages, then –with-python-dir=/lib/python2.5/site-packages should be passed. If this is not specified, then the Python modules are installed in $(prefix)/share/python. ! !
--enable-aot-compile-rpm
Adds aot-compile-rpm to the list of installed scripts. ! !
--enable-browser-plugin
Build the gcjwebplugin web browser plugin. ! !
--enable-static-libjava
Build static libraries in libjava. The default is to only build shared libraries. ! !
!
ansi
Use the single-byte char and the Win32 A functions natively, translating to and from UNICODE when using these functions. If unspecified, this is the default. ! !
unicows
Use the WCHAR and Win32 W functions natively. Adds ! -lunicows to libgcj.spec to link with ‘libunicows’. ! unicows.dll needs to be deployed on Microsoft Windows 9X machines ! running built executables. libunicows.a, an open-source ! import library around Microsoft's unicows.dll, is obtained from http://libunicows.sourceforge.net/, which also gives details ! on getting unicows.dll from Microsoft. ! !
unicode
Use the WCHAR and Win32 W functions natively. Does not ! add -lunicows to libgcj.spec. The built executables will ! only run on Microsoft Windows NT and above.
+
!
AWT-Specific Options
!
!
--with-x
Use the X Window System. !
--enable-java-awt=PEER(S)
Specifies the AWT peer library or libraries to build alongside ! ‘libgcj’. If this option is unspecified or disabled, AWT ! will be non-functional. Current valid values are gtk and ! xlib. Multiple libraries should be separated by a ! comma (i.e. --enable-java-awt=gtk,xlib). !
--enable-gtk-cairo
Build the cairo Graphics2D implementation on GTK. !
--enable-java-gc=TYPE
Choose garbage collector. Defaults to boehm if unspecified. ! !
--disable-gtktest
Do not try to compile and run a test GTK+ program. ! !
--disable-glibtest
Do not try to compile and run a test GLIB program. ! !
--with-libart-prefix=PFX
Prefix where libart is installed (optional). ! !
--with-libart-exec-prefix=PFX
Exec prefix where libart is installed (optional). +
--disable-libarttest
Do not try to compile and run a test libart program. +
+
Overriding configure test results
+

Sometimes, it might be necessary to override the result of some + configure test, for example in order to ease porting to a new + system or work around a bug in a test. The toplevel configure + script provides three variables for this: +

+
build_configargs
The contents of this variable is passed to all build configure + scripts. + +
host_configargs
The contents of this variable is passed to all host configure + scripts. +
target_configargs
The contents of this variable is passed to all target configure + scripts. +
+

In order to avoid shell and make quoting issues for complex + overrides, you can pass a setting for CONFIG_SITE and set + variables in the site file. +

+

Return to the GCC Installation page + + + + + + + + + + diff -Nrcpad gcc-4.8.2/INSTALL/download.html gcc-4.8.3/INSTALL/download.html *** gcc-4.8.2/INSTALL/download.html Wed Oct 16 07:28:01 2013 --- gcc-4.8.3/INSTALL/download.html Thu May 22 09:13:50 2014 *************** *** 1,132 **** ! ! ! ! ! ! Installing GCC ! ! ! ! ! ! ! ! ! ! ! !

Installing GCC

! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

GCC is distributed via SVN and FTP ! tarballs compressed with gzip or ! bzip2. !

!

Please refer to the releases web page for information on how to obtain GCC. !

!

The source distribution includes the C, C++, Objective-C, Fortran, Java, and Ada (in the case of GCC 3.1 and later) compilers, as well as ! runtime libraries for C++, Objective-C, Fortran, and Java. For previous versions these were downloadable as separate components such as the core GCC distribution, which included the C language front end and shared components, and language-specific distributions including the language front end and the language runtime (where appropriate). !

!

If you also intend to build binutils (either to upgrade an existing installation or for use in place of the corresponding tools of your OS), unpack the binutils distribution either in the same directory or a separate one. In the latter case, add symbolic links to any components of the binutils you intend to build alongside the compiler ! (bfd, binutils, gas, gprof, ld, ! opcodes, …) to the directory containing the GCC sources. !

!

Likewise the GMP, MPFR and MPC libraries can be automatically built together with GCC. Unpack the GMP, MPFR and/or MPC source distributions in the directory containing the GCC sources and rename ! their directories to gmp, mpfr and mpc, respectively (or use symbolic links with the same name). -

-
-

Return to the GCC Installation page -

- - - - - - - - - - - --- 1,87 ---- ! ! ! Downloading GCC ! ! ! ! ! ! ! ! + +

Downloading GCC

+ + GCC is distributed via SVN and FTP + tarballs compressed with gzip or + bzip2. !

Please refer to the releases web page for information on how to obtain GCC. ! !

The source distribution includes the C, C++, Objective-C, Fortran, Java, and Ada (in the case of GCC 3.1 and later) compilers, as well as ! runtime libraries for C++, Objective-C, Fortran, and Java. For previous versions these were downloadable as separate components such as the core GCC distribution, which included the C language front end and shared components, and language-specific distributions including the language front end and the language runtime (where appropriate). ! !

If you also intend to build binutils (either to upgrade an existing installation or for use in place of the corresponding tools of your OS), unpack the binutils distribution either in the same directory or a separate one. In the latter case, add symbolic links to any components of the binutils you intend to build alongside the compiler ! (bfd, binutils, gas, gprof, ld, ! opcodes, ...) to the directory containing the GCC sources. ! !

Likewise the GMP, MPFR and MPC libraries can be automatically built together with GCC. Unpack the GMP, MPFR and/or MPC source distributions in the directory containing the GCC sources and rename ! their directories to gmp, mpfr and mpc, respectively (or use symbolic links with the same name). +

+

Return to the GCC Installation page + + + + + + + + + + + diff -Nrcpad gcc-4.8.2/INSTALL/finalinstall.html gcc-4.8.3/INSTALL/finalinstall.html *** gcc-4.8.2/INSTALL/finalinstall.html Wed Oct 16 07:28:03 2013 --- gcc-4.8.3/INSTALL/finalinstall.html Thu May 22 09:13:50 2014 *************** *** 1,227 **** ! ! ! ! ! ! Installing GCC ! ! ! ! ! ! ! ! ! ! ! ! !

Installing GCC

! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

Now that GCC has been built (and optionally tested), you can install it with !

! 
cd objdir && make install
!
! !

We strongly recommend to install into a target directory where there is no previous version of GCC present. Also, the GNAT runtime should not be stripped, as this would break certain features of the debugger that depend on this debugging information (catching Ada exceptions for instance). !

!

That step completes the installation of GCC; user level binaries can ! be found in prefix/bin where prefix is the value ! you specified with the --prefix to configure (or ! /usr/local by default). (If you specified --bindir, that directory will be used instead; otherwise, if you specified ! --exec-prefix, exec-prefix/bin will be used.) Headers for the C++ and Java libraries are installed in ! prefix/include; libraries in libdir ! (normally prefix/lib); internal parts of the compiler in ! libdir/gcc and libexecdir/gcc; documentation in info format in infodir (normally ! prefix/info). !

!

When installing cross-compilers, GCC’s executables are not only installed into bindir, that ! is, exec-prefix/bin, but additionally into ! exec-prefix/target-alias/bin, if that directory ! exists. Typically, such tooldirs hold target-specific binutils, including assembler and linker. !

!

Installation into a temporary staging area or into a chroot jail can be achieved with the command -

-
- 
make DESTDIR=path-to-rootdir install
-
!

where path-to-rootdir is the absolute path of a directory relative to which all installation paths will be interpreted. Note that the directory specified by DESTDIR need not exist yet; it will be created if necessary. !

!

There is a subtle point with tooldirs and DESTDIR: If you relocate a cross-compiler installation with ! e.g. ‘DESTDIR=rootdir’, then the directory ! rootdir/exec-prefix/target-alias/bin will be filled with duplicated GCC executables only if it already exists, it will not be created otherwise. This is regarded as a feature, not as a bug, because it gives slightly more control to the packagers using the DESTDIR feature. -

-

You can install stripped programs and libraries with -

-
- 
make install-strip
-
!

If you are bootstrapping a released version of GCC then please quickly review the build status page for your release, available from ! http://gcc.gnu.org/buildstat.html. If your system is not listed for the version of GCC that you built, send a note to gcc@gcc.gnu.org indicating ! that you successfully built and installed GCC. Include the following information: !

!
    !
  • Output from running srcdir/config.guess. Do not send that file itself, just the one-line output from running it. !
  • The output of ‘gcc -v’ for your newly installed gcc. This tells us which version of GCC you built and the options you passed to configure. !
  • Whether you enabled all languages or a subset of them. If you used a full distribution then this information is part of the configure ! options in the output of ‘gcc -v’, but if you downloaded the ! “core” compiler plus additional front ends then it isn’t apparent which ones you built unless you tell us about it. !
  • If the build was for GNU/Linux, also include: !
      !
    • The distribution name and version (e.g., Red Hat 7.1 or Debian 2.2.3); ! this information should be available from /etc/issue. !
    • The version of the Linux kernel, available from ‘uname --version’ ! or ‘uname -a’. !
    • The version of glibc you used; for RPM-based systems like Red Hat, ! Mandrake, and SuSE type ‘rpm -q glibc’ to get the glibc version, ! and on systems like Debian and Progeny use ‘dpkg -l libc6’. !
    !

    For other systems, you can include similar information if you think it is relevant. !

    !
  • Any other information that you think would be useful to people building GCC on the same configuration. The new entry in the build status list ! will include a link to the archived copy of your message. !
!

We’d also like to know if the host/target specific installation notes ! didn’t include your host/target information or if that information is incomplete or out of date. Send a note to gcc@gcc.gnu.org detailing how the information should be changed. !

!

If you find a bug, please report it following the bug reporting guidelines. !

!

If you want to print the GCC manuals, do ‘cd objdir; make ! dvi’. You will need to have texi2dvi (version at least 4.7) ! and TeX installed. This creates a number of .dvi files in subdirectories of objdir; these may be converted for ! printing with programs such as dvips. Alternately, by using ! ‘make pdf’ in place of ‘make dvi’, you can create documentation ! in the form of .pdf files; this requires texi2pdf, which is included with Texinfo version 4.8 and later. You can also ! buy printed manuals from the ! Free Software Foundation, though such manuals may not be for the most recent version of GCC. -

-

If you would like to generate online HTML documentation, do ‘cd - objdir; make html’ and HTML will be generated for the gcc manuals in - objdir/gcc/HTML. -

-
-

Return to the GCC Installation page -

- - - - - - --- 1,172 ---- ! ! ! Installing GCC: Final installation ! ! ! ! ! ! ! ! ! !

Installing GCC: Final installation

! Now that GCC has been built (and optionally tested), you can install it with ! 
     cd objdir && make install
!
!

We strongly recommend to install into a target directory where there is no previous version of GCC present. Also, the GNAT runtime should not be stripped, as this would break certain features of the debugger that depend on this debugging information (catching Ada exceptions for instance). ! !

That step completes the installation of GCC; user level binaries can ! be found in prefix/bin where prefix is the value ! you specified with the --prefix to configure (or ! /usr/local by default). (If you specified --bindir, that directory will be used instead; otherwise, if you specified ! --exec-prefix, exec-prefix/bin will be used.) Headers for the C++ and Java libraries are installed in ! prefix/include; libraries in libdir ! (normally prefix/lib); internal parts of the compiler in ! libdir/gcc and libexecdir/gcc; documentation in info format in infodir (normally ! prefix/info). ! !

When installing cross-compilers, GCC's executables are not only installed into bindir, that ! is, exec-prefix/bin, but additionally into ! exec-prefix/target-alias/bin, if that directory ! exists. Typically, such tooldirs hold target-specific binutils, including assembler and linker. ! !

Installation into a temporary staging area or into a chroot jail can be achieved with the command ! 

     make DESTDIR=path-to-rootdir install
!
!

where path-to-rootdir is the absolute path of a directory relative to which all installation paths will be interpreted. Note that the directory specified by DESTDIR need not exist yet; it will be created if necessary. ! !

There is a subtle point with tooldirs and DESTDIR: If you relocate a cross-compiler installation with ! e.g. ‘DESTDIR=rootdir’, then the directory ! rootdir/exec-prefix/target-alias/bin will be filled with duplicated GCC executables only if it already exists, it will not be created otherwise. This is regarded as a feature, not as a bug, because it gives slightly more control to the packagers using the DESTDIR feature. !

You can install stripped programs and libraries with ! ! 

     make install-strip
!
!

If you are bootstrapping a released version of GCC then please quickly review the build status page for your release, available from ! http://gcc.gnu.org/buildstat.html. If your system is not listed for the version of GCC that you built, send a note to gcc@gcc.gnu.org indicating ! that you successfully built and installed GCC. Include the following information: ! !

    !
  • Output from running srcdir/config.guess. Do not send that file itself, just the one-line output from running it. !
  • The output of ‘gcc -v’ for your newly installed gcc. This tells us which version of GCC you built and the options you passed to configure. !
  • Whether you enabled all languages or a subset of them. If you used a full distribution then this information is part of the configure ! options in the output of ‘gcc -v’, but if you downloaded the ! “core” compiler plus additional front ends then it isn't apparent which ones you built unless you tell us about it. !
  • If the build was for GNU/Linux, also include: !
      !
    • The distribution name and version (e.g., Red Hat 7.1 or Debian 2.2.3); ! this information should be available from /etc/issue. !
    • The version of the Linux kernel, available from ‘uname --version’ ! or ‘uname -a’. !
    • The version of glibc you used; for RPM-based systems like Red Hat, ! Mandrake, and SuSE type ‘rpm -q glibc’ to get the glibc version, ! and on systems like Debian and Progeny use ‘dpkg -l libc6’. !
    ! For other systems, you can include similar information if you think it is relevant. ! !
  • Any other information that you think would be useful to people building GCC on the same configuration. The new entry in the build status list ! will include a link to the archived copy of your message. !
!

We'd also like to know if the host/target specific installation notes ! didn't include your host/target information or if that information is incomplete or out of date. Send a note to gcc@gcc.gnu.org detailing how the information should be changed. ! !

If you find a bug, please report it following the bug reporting guidelines. ! !

If you want to print the GCC manuals, do ‘cd objdir; make ! dvi’. You will need to have texi2dvi (version at least 4.7) ! and TeX installed. This creates a number of .dvi files in subdirectories of objdir; these may be converted for ! printing with programs such as dvips. Alternately, by using ! ‘make pdf’ in place of ‘make dvi’, you can create documentation ! in the form of .pdf files; this requires texi2pdf, which is included with Texinfo version 4.8 and later. You can also ! buy printed manuals from the Free Software Foundation, though such manuals may not be for the most recent version of GCC. +

If you would like to generate online HTML documentation, do ‘cd + objdir; make html’ and HTML will be generated for the gcc manuals in + objdir/gcc/HTML. +

+

Return to the GCC Installation page + + + + + + + diff -Nrcpad gcc-4.8.2/INSTALL/gfdl.html gcc-4.8.3/INSTALL/gfdl.html *** gcc-4.8.2/INSTALL/gfdl.html Wed Oct 16 07:28:05 2013 --- gcc-4.8.3/INSTALL/gfdl.html Thu May 22 09:13:50 2014 *************** *** 1,133 **** ! ! ! ! ! ! Installing GCC ! ! ! ! ! ! ! ! ! ! ! !

Installing GCC

! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

Installing GCC: GNU Free Documentation License

! !
Version 1.3, 3 November 2008 !
!
! 
Copyright © 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc.
! http://fsf.org/
! 
! Everyone is permitted to copy and distribute verbatim copies
! of this license document, but changing it is not allowed.
!
!
    !
  1. PREAMBLE !

    The purpose of this License is to make a manual, textbook, or other ! functional and useful document free in the sense of freedom: to assure everyone the effective freedom to copy and redistribute it, ! with or without modifying it, either commercially or noncommercially. Secondarily, this License preserves for the author and publisher a way to get credit for their work, while not being considered responsible for modifications made by others. !

    !

    This License is a kind of “copyleft”, which means that derivative works of the document must themselves be free in the same sense. It complements the GNU General Public License, which is a copyleft license designed for free software. !

    !

    We have designed this License in order to use it for manuals for free software, because free software needs free documentation: a free program should come with manuals providing the same freedoms that the software does. But this License is not limited to software manuals; it can be used for any textual work, regardless of subject matter or whether it is published as a printed book. We recommend this License principally for works whose purpose is instruction or reference. -

    -
  2. APPLICABILITY AND DEFINITIONS !

    This License applies to any manual or other work, in any medium, that contains a notice placed by the copyright holder saying it can be distributed under the terms of this License. Such a notice grants a world-wide, royalty-free license, unlimited in duration, to use that --- 1,82 ---- ! ! ! Installing GCC: GNU Free Documentation License ! ! ! ! ! ! ! ! + +

    Installing GCC: GNU Free Documentation License

    +

    Installing GCC: GNU Free Documentation License

    !

    Version 1.3, 3 November 2008
    ! 
         Copyright © 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc.
!      http://fsf.org/
!      
!      Everyone is permitted to copy and distribute verbatim copies
!      of this license document, but changing it is not allowed.
!
    !
      !
    1. PREAMBLE !

      The purpose of this License is to make a manual, textbook, or other ! functional and useful document free in the sense of freedom: to assure everyone the effective freedom to copy and redistribute it, ! with or without modifying it, either commercially or noncommercially. Secondarily, this License preserves for the author and publisher a way to get credit for their work, while not being considered responsible for modifications made by others. ! !

      This License is a kind of “copyleft”, which means that derivative works of the document must themselves be free in the same sense. It complements the GNU General Public License, which is a copyleft license designed for free software. ! !

      We have designed this License in order to use it for manuals for free software, because free software needs free documentation: a free program should come with manuals providing the same freedoms that the software does. But this License is not limited to software manuals; it can be used for any textual work, regardless of subject matter or whether it is published as a printed book. We recommend this License principally for works whose purpose is instruction or reference. !

    2. APPLICABILITY AND DEFINITIONS ! !

      This License applies to any manual or other work, in any medium, that contains a notice placed by the copyright holder saying it can be distributed under the terms of this License. Such a notice grants a world-wide, royalty-free license, unlimited in duration, to use that *************** refers to any such manual or work. Any *** 136,149 **** licensee, and is addressed as “you”. You accept the license if you copy, modify or distribute the work in a way requiring permission under copyright law. !

      !

      A “Modified Version” of the Document means any work containing the Document or a portion of it, either copied verbatim, or with modifications and/or translated into another language. !

      !

      A “Secondary Section” is a named appendix or a front-matter section of the Document that deals exclusively with the relationship of the ! publishers or authors of the Document to the Document’s overall subject (or to related matters) and contains nothing that could fall directly within that overall subject. (Thus, if the Document is in part a textbook of mathematics, a Secondary Section may not explain --- 85,98 ---- licensee, and is addressed as “you”. You accept the license if you copy, modify or distribute the work in a way requiring permission under copyright law. ! !

      A “Modified Version” of the Document means any work containing the Document or a portion of it, either copied verbatim, or with modifications and/or translated into another language. ! !

      A “Secondary Section” is a named appendix or a front-matter section of the Document that deals exclusively with the relationship of the ! publishers or authors of the Document to the Document's overall subject (or to related matters) and contains nothing that could fall directly within that overall subject. (Thus, if the Document is in part a textbook of mathematics, a Secondary Section may not explain *************** any mathematics.) The relationship coul *** 151,171 **** connection with the subject or with related matters, or of legal, commercial, philosophical, ethical or political position regarding them. !

      !

      The “Invariant Sections” are certain Secondary Sections whose titles are designated, as being those of Invariant Sections, in the notice that says that the Document is released under this License. If a section does not fit the above definition of Secondary then it is not allowed to be designated as Invariant. The Document may contain zero Invariant Sections. If the Document does not identify any Invariant Sections then there are none. !

      !

      The “Cover Texts” are certain short passages of text that are listed, as Front-Cover Texts or Back-Cover Texts, in the notice that says that the Document is released under this License. A Front-Cover Text may be at most 5 words, and a Back-Cover Text may be at most 25 words. !

      !

      A “Transparent” copy of the Document means a machine-readable copy, represented in a format whose specification is available to the general public, that is suitable for revising the document straightforwardly with generic text editors or (for images composed of --- 100,120 ---- connection with the subject or with related matters, or of legal, commercial, philosophical, ethical or political position regarding them. ! !

      The “Invariant Sections” are certain Secondary Sections whose titles are designated, as being those of Invariant Sections, in the notice that says that the Document is released under this License. If a section does not fit the above definition of Secondary then it is not allowed to be designated as Invariant. The Document may contain zero Invariant Sections. If the Document does not identify any Invariant Sections then there are none. ! !

      The “Cover Texts” are certain short passages of text that are listed, as Front-Cover Texts or Back-Cover Texts, in the notice that says that the Document is released under this License. A Front-Cover Text may be at most 5 words, and a Back-Cover Text may be at most 25 words. ! !

      A “Transparent” copy of the Document means a machine-readable copy, represented in a format whose specification is available to the general public, that is suitable for revising the document straightforwardly with generic text editors or (for images composed of *************** drawing editor, and that is suitable for *** 174,185 **** for automatic translation to a variety of formats suitable for input to text formatters. A copy made in an otherwise Transparent file format whose markup, or absence of markup, has been arranged to thwart ! or discourage subsequent modification by readers is not Transparent. An image format is not Transparent if used for any substantial amount of text. A copy that is not “Transparent” is called “Opaque”. !

      !

      Examples of suitable formats for Transparent copies include plain ! ASCII without markup, Texinfo input format, LaTeX input format, SGML or XML using a publicly available DTD, and standard-conforming simple HTML, PostScript or PDF designed for human modification. Examples --- 123,134 ---- for automatic translation to a variety of formats suitable for input to text formatters. A copy made in an otherwise Transparent file format whose markup, or absence of markup, has been arranged to thwart ! or discourage subsequent modification by readers is not Transparent. An image format is not Transparent if used for any substantial amount of text. A copy that is not “Transparent” is called “Opaque”. ! !

      Examples of suitable formats for Transparent copies include plain ! ascii without markup, Texinfo input format, LaTeX input format, SGML or XML using a publicly available DTD, and standard-conforming simple HTML, PostScript or PDF designed for human modification. Examples *************** read and edited only by proprietary word *** 190,224 **** not generally available, and the machine-generated HTML, PostScript or PDF produced by some word processors for output purposes only. !

      !

      The “Title Page” means, for a printed book, the title page itself, plus such following pages as are needed to hold, legibly, the material this License requires to appear in the title page. For works in formats which do not have any title page as such, “Title Page” means ! the text near the most prominent appearance of the work’s title, preceding the beginning of the body of the text. !

      !

      The “publisher” means any person or entity that distributes copies of the Document to the public. !

      !

      A section “Entitled XYZ” means a named subunit of the Document whose title either is precisely XYZ or contains XYZ in parentheses following text that translates XYZ in another language. (Here XYZ stands for a specific section name mentioned below, such as “Acknowledgements”, “Dedications”, “Endorsements”, or “History”.) To “Preserve the Title” of such a section when you modify the Document means that it remains a section “Entitled XYZ” according to this definition. !

      !

      The Document may include Warranty Disclaimers next to the notice which states that this License applies to the Document. These Warranty Disclaimers are considered to be included by reference in this License, but only as regards disclaiming warranties: any other implication that these Warranty Disclaimers may have is void and has no effect on the meaning of this License. -

      -
    3. VERBATIM COPYING !

      You may copy and distribute the Document in any medium, either commercially or noncommercially, provided that this License, the copyright notices, and the license notice saying this License applies to the Document are reproduced in all copies, and that you add no other --- 139,173 ---- not generally available, and the machine-generated HTML, PostScript or PDF produced by some word processors for output purposes only. ! !

      The “Title Page” means, for a printed book, the title page itself, plus such following pages as are needed to hold, legibly, the material this License requires to appear in the title page. For works in formats which do not have any title page as such, “Title Page” means ! the text near the most prominent appearance of the work's title, preceding the beginning of the body of the text. ! !

      The “publisher” means any person or entity that distributes copies of the Document to the public. ! !

      A section “Entitled XYZ” means a named subunit of the Document whose title either is precisely XYZ or contains XYZ in parentheses following text that translates XYZ in another language. (Here XYZ stands for a specific section name mentioned below, such as “Acknowledgements”, “Dedications”, “Endorsements”, or “History”.) To “Preserve the Title” of such a section when you modify the Document means that it remains a section “Entitled XYZ” according to this definition. ! !

      The Document may include Warranty Disclaimers next to the notice which states that this License applies to the Document. These Warranty Disclaimers are considered to be included by reference in this License, but only as regards disclaiming warranties: any other implication that these Warranty Disclaimers may have is void and has no effect on the meaning of this License. !

    4. VERBATIM COPYING ! !

      You may copy and distribute the Document in any medium, either commercially or noncommercially, provided that this License, the copyright notices, and the license notice saying this License applies to the Document are reproduced in all copies, and that you add no other *************** technical measures to obstruct or contro *** 227,313 **** copying of the copies you make or distribute. However, you may accept compensation in exchange for copies. If you distribute a large enough number of copies you must also follow the conditions in section 3. !

      !

      You may also lend copies, under the same conditions stated above, and you may publicly display copies. -

      -
    5. COPYING IN QUANTITY !

      If you publish printed copies (or copies in media that commonly have printed covers) of the Document, numbering more than 100, and the ! Document’s license notice requires Cover Texts, you must enclose the copies in covers that carry, clearly and legibly, all these Cover Texts: Front-Cover Texts on the front cover, and Back-Cover Texts on the back cover. Both covers must also clearly and legibly identify you as the publisher of these copies. The front cover must present the full title with all words of the title equally prominent and ! visible. You may add other material on the covers in addition. Copying with changes limited to the covers, as long as they preserve the title of the Document and satisfy these conditions, can be treated as verbatim copying in other respects. !

      !

      If the required texts for either cover are too voluminous to fit legibly, you should put the first ones listed (as many as fit reasonably) on the actual cover, and continue the rest onto adjacent pages. !

      !

      If you publish or distribute Opaque copies of the Document numbering more than 100, you must either include a machine-readable Transparent copy along with each Opaque copy, or state in or with each Opaque copy a computer-network location from which the general network-using public has access to download using public-standard network protocols ! a complete Transparent copy of the Document, free of added material. If you use the latter option, you must take reasonably prudent steps, when you begin distribution of Opaque copies in quantity, to ensure that this Transparent copy will remain thus accessible at the stated location until at least one year after the last time you distribute an Opaque copy (directly or through your agents or retailers) of that edition to the public. !

      !

      It is requested, but not required, that you contact the authors of the Document well before redistributing any large number of copies, to give them a chance to provide you with an updated version of the Document. -

      -
    6. MODIFICATIONS !

      You may copy and distribute a Modified Version of the Document under the conditions of sections 2 and 3 above, provided that you release the Modified Version under precisely this License, with the Modified Version filling the role of the Document, thus licensing distribution and modification of the Modified Version to whoever possesses a copy of it. In addition, you must do these things in the Modified Version: !

      !
        !
      1. Use in the Title Page (and on the covers, if any) a title distinct from that of the Document, and from those of previous versions (which should, if there were any, be listed in the History section of the Document). You may use the same title as a previous version if the original publisher of that version gives permission. !
      2. List on the Title Page, as authors, one or more persons or entities responsible for authorship of the modifications in the Modified Version, together with at least five of the principal authors of the Document (all of its principal authors, if it has fewer than five), unless they release you from this requirement. !
      3. State on the Title page the name of the publisher of the Modified Version, as the publisher. !
      4. Preserve all the copyright notices of the Document. !
      5. Add an appropriate copyright notice for your modifications adjacent to the other copyright notices. !
      6. Include, immediately after the copyright notices, a license notice giving the public permission to use the Modified Version under the terms of this License, in the form shown in the Addendum below. !
      7. Preserve in that license notice the full lists of Invariant Sections ! and required Cover Texts given in the Document’s license notice. !
      8. Include an unaltered copy of this License. !
      9. Preserve the section Entitled “History”, Preserve its Title, and add to it an item stating at least the title, year, new authors, and publisher of the Modified Version as given on the Title Page. If there is no section Entitled “History” in the Document, create one --- 176,262 ---- copying of the copies you make or distribute. However, you may accept compensation in exchange for copies. If you distribute a large enough number of copies you must also follow the conditions in section 3. ! !

        You may also lend copies, under the same conditions stated above, and you may publicly display copies. !

      10. COPYING IN QUANTITY ! !

        If you publish printed copies (or copies in media that commonly have printed covers) of the Document, numbering more than 100, and the ! Document's license notice requires Cover Texts, you must enclose the copies in covers that carry, clearly and legibly, all these Cover Texts: Front-Cover Texts on the front cover, and Back-Cover Texts on the back cover. Both covers must also clearly and legibly identify you as the publisher of these copies. The front cover must present the full title with all words of the title equally prominent and ! visible. You may add other material on the covers in addition. Copying with changes limited to the covers, as long as they preserve the title of the Document and satisfy these conditions, can be treated as verbatim copying in other respects. ! !

        If the required texts for either cover are too voluminous to fit legibly, you should put the first ones listed (as many as fit reasonably) on the actual cover, and continue the rest onto adjacent pages. ! !

        If you publish or distribute Opaque copies of the Document numbering more than 100, you must either include a machine-readable Transparent copy along with each Opaque copy, or state in or with each Opaque copy a computer-network location from which the general network-using public has access to download using public-standard network protocols ! a complete Transparent copy of the Document, free of added material. If you use the latter option, you must take reasonably prudent steps, when you begin distribution of Opaque copies in quantity, to ensure that this Transparent copy will remain thus accessible at the stated location until at least one year after the last time you distribute an Opaque copy (directly or through your agents or retailers) of that edition to the public. ! !

        It is requested, but not required, that you contact the authors of the Document well before redistributing any large number of copies, to give them a chance to provide you with an updated version of the Document. !

      11. MODIFICATIONS ! !

        You may copy and distribute a Modified Version of the Document under the conditions of sections 2 and 3 above, provided that you release the Modified Version under precisely this License, with the Modified Version filling the role of the Document, thus licensing distribution and modification of the Modified Version to whoever possesses a copy of it. In addition, you must do these things in the Modified Version: ! !

          !
        1. Use in the Title Page (and on the covers, if any) a title distinct from that of the Document, and from those of previous versions (which should, if there were any, be listed in the History section of the Document). You may use the same title as a previous version if the original publisher of that version gives permission. !
        2. List on the Title Page, as authors, one or more persons or entities responsible for authorship of the modifications in the Modified Version, together with at least five of the principal authors of the Document (all of its principal authors, if it has fewer than five), unless they release you from this requirement. !
        3. State on the Title page the name of the publisher of the Modified Version, as the publisher. !
        4. Preserve all the copyright notices of the Document. !
        5. Add an appropriate copyright notice for your modifications adjacent to the other copyright notices. !
        6. Include, immediately after the copyright notices, a license notice giving the public permission to use the Modified Version under the terms of this License, in the form shown in the Addendum below. !
        7. Preserve in that license notice the full lists of Invariant Sections ! and required Cover Texts given in the Document's license notice. !
        8. Include an unaltered copy of this License. !
        9. Preserve the section Entitled “History”, Preserve its Title, and add to it an item stating at least the title, year, new authors, and publisher of the Modified Version as given on the Title Page. If there is no section Entitled “History” in the Document, create one *************** stating the title, year, authors, and pu *** 315,360 **** given on its Title Page, then add an item describing the Modified Version as stated in the previous sentence. !
        10. Preserve the network location, if any, given in the Document for public access to a Transparent copy of the Document, and likewise the network locations given in the Document for previous versions ! it was based on. These may be placed in the “History” section. You may omit a network location for a work that was published at least four years before the Document itself, or if the original publisher of the version it refers to gives permission. !
        11. For any section Entitled “Acknowledgements” or “Dedications”, Preserve the Title of the section, and preserve in the section all the substance and tone of each of the contributor acknowledgements and/or dedications given therein. !
        12. Preserve all the Invariant Sections of the Document, unaltered in their text and in their titles. Section numbers or the equivalent are not considered part of the section titles. !
        13. Delete any section Entitled “Endorsements”. Such a section may not be included in the Modified Version. !
        14. Do not retitle any existing section to be Entitled “Endorsements” or to conflict in title with any Invariant Section. !
        15. Preserve any Warranty Disclaimers. !
        !

        If the Modified Version includes new front-matter sections or appendices that qualify as Secondary Sections and contain no material copied from the Document, you may at your option designate some or all of these sections as invariant. To do this, add their titles to the ! list of Invariant Sections in the Modified Version’s license notice. These titles must be distinct from any other section titles. !

        !

        You may add a section Entitled “Endorsements”, provided it contains nothing but endorsements of your Modified Version by various parties—for example, statements of peer review or that the text has been approved by an organization as the authoritative definition of a standard. !

        !

        You may add a passage of up to five words as a Front-Cover Text, and a passage of up to 25 words as a Back-Cover Text, to the end of the list of Cover Texts in the Modified Version. Only one passage of Front-Cover Text and one of Back-Cover Text may be added by (or --- 264,309 ---- given on its Title Page, then add an item describing the Modified Version as stated in the previous sentence. !

      12. Preserve the network location, if any, given in the Document for public access to a Transparent copy of the Document, and likewise the network locations given in the Document for previous versions ! it was based on. These may be placed in the “History” section. You may omit a network location for a work that was published at least four years before the Document itself, or if the original publisher of the version it refers to gives permission. !
      13. For any section Entitled “Acknowledgements” or “Dedications”, Preserve the Title of the section, and preserve in the section all the substance and tone of each of the contributor acknowledgements and/or dedications given therein. !
      14. Preserve all the Invariant Sections of the Document, unaltered in their text and in their titles. Section numbers or the equivalent are not considered part of the section titles. !
      15. Delete any section Entitled “Endorsements”. Such a section may not be included in the Modified Version. !
      16. Do not retitle any existing section to be Entitled “Endorsements” or to conflict in title with any Invariant Section. !
      17. Preserve any Warranty Disclaimers. !
      !

      If the Modified Version includes new front-matter sections or appendices that qualify as Secondary Sections and contain no material copied from the Document, you may at your option designate some or all of these sections as invariant. To do this, add their titles to the ! list of Invariant Sections in the Modified Version's license notice. These titles must be distinct from any other section titles. ! !

      You may add a section Entitled “Endorsements”, provided it contains nothing but endorsements of your Modified Version by various parties—for example, statements of peer review or that the text has been approved by an organization as the authoritative definition of a standard. ! !

      You may add a passage of up to five words as a Front-Cover Text, and a passage of up to 25 words as a Back-Cover Text, to the end of the list of Cover Texts in the Modified Version. Only one passage of Front-Cover Text and one of Back-Cover Text may be added by (or *************** includes a cover text for the same cover *** 363,433 **** by arrangement made by the same entity you are acting on behalf of, you may not add another; but you may replace the old one, on explicit permission from the previous publisher that added the old one. !

      !

      The author(s) and publisher(s) of the Document do not by this License give permission to use their names for publicity for or to assert or imply endorsement of any Modified Version. -

      -
    7. COMBINING DOCUMENTS !

      You may combine the Document with other documents released under this License, under the terms defined in section 4 above for modified versions, provided that you include in the combination all of the Invariant Sections of all of the original documents, unmodified, and list them all as Invariant Sections of your combined work in its license notice, and that you preserve all their Warranty Disclaimers. !

      !

      The combined work need only contain one copy of this License, and multiple identical Invariant Sections may be replaced with a single copy. If there are multiple Invariant Sections with the same name but different contents, make the title of each such section unique by adding at the end of it, in parentheses, the name of the original ! author or publisher of that section if known, or else a unique number. Make the same adjustment to the section titles in the list of Invariant Sections in the license notice of the combined work. !

      !

      In the combination, you must combine any sections Entitled “History” in the various original documents, forming one section Entitled “History”; likewise combine any sections Entitled “Acknowledgements”, and any sections Entitled “Dedications”. You must delete all sections Entitled “Endorsements.” -

      -
    8. COLLECTIONS OF DOCUMENTS !

      You may make a collection consisting of the Document and other documents released under this License, and replace the individual copies of this License in the various documents with a single copy that is included in the collection, provided that you follow the rules of this License for verbatim copying of each of the documents in all other respects. !

      !

      You may extract a single document from such a collection, and distribute it individually under this License, provided you insert a copy of this License into the extracted document, and follow this License in all other respects regarding verbatim copying of that document. -

      -
    9. AGGREGATION WITH INDEPENDENT WORKS !

      A compilation of the Document or its derivatives with other separate and independent documents or works, in or on a volume of a storage or distribution medium, is called an “aggregate” if the copyright resulting from the compilation is not used to limit the legal rights ! of the compilation’s users beyond what the individual works permit. When the Document is included in an aggregate, this License does not apply to the other works in the aggregate which are not themselves derivative works of the Document. !

      !

      If the Cover Text requirement of section 3 is applicable to these copies of the Document, then if the Document is less than one half of ! the entire aggregate, the Document’s Cover Texts may be placed on covers that bracket the Document within the aggregate, or the ! electronic equivalent of covers if the Document is in electronic form. Otherwise they must appear on printed covers that bracket the whole aggregate. -

      -
    10. TRANSLATION !

      Translation is considered a kind of modification, so you may ! distribute translations of the Document under the terms of section 4. Replacing Invariant Sections with translations requires special permission from their copyright holders, but you may include translations of some or all Invariant Sections in addition to the --- 312,382 ---- by arrangement made by the same entity you are acting on behalf of, you may not add another; but you may replace the old one, on explicit permission from the previous publisher that added the old one. ! !

      The author(s) and publisher(s) of the Document do not by this License give permission to use their names for publicity for or to assert or imply endorsement of any Modified Version. !

    11. COMBINING DOCUMENTS ! !

      You may combine the Document with other documents released under this License, under the terms defined in section 4 above for modified versions, provided that you include in the combination all of the Invariant Sections of all of the original documents, unmodified, and list them all as Invariant Sections of your combined work in its license notice, and that you preserve all their Warranty Disclaimers. ! !

      The combined work need only contain one copy of this License, and multiple identical Invariant Sections may be replaced with a single copy. If there are multiple Invariant Sections with the same name but different contents, make the title of each such section unique by adding at the end of it, in parentheses, the name of the original ! author or publisher of that section if known, or else a unique number. Make the same adjustment to the section titles in the list of Invariant Sections in the license notice of the combined work. ! !

      In the combination, you must combine any sections Entitled “History” in the various original documents, forming one section Entitled “History”; likewise combine any sections Entitled “Acknowledgements”, and any sections Entitled “Dedications”. You must delete all sections Entitled “Endorsements.” !

    12. COLLECTIONS OF DOCUMENTS ! !

      You may make a collection consisting of the Document and other documents released under this License, and replace the individual copies of this License in the various documents with a single copy that is included in the collection, provided that you follow the rules of this License for verbatim copying of each of the documents in all other respects. ! !

      You may extract a single document from such a collection, and distribute it individually under this License, provided you insert a copy of this License into the extracted document, and follow this License in all other respects regarding verbatim copying of that document. !

    13. AGGREGATION WITH INDEPENDENT WORKS ! !

      A compilation of the Document or its derivatives with other separate and independent documents or works, in or on a volume of a storage or distribution medium, is called an “aggregate” if the copyright resulting from the compilation is not used to limit the legal rights ! of the compilation's users beyond what the individual works permit. When the Document is included in an aggregate, this License does not apply to the other works in the aggregate which are not themselves derivative works of the Document. ! !

      If the Cover Text requirement of section 3 is applicable to these copies of the Document, then if the Document is less than one half of ! the entire aggregate, the Document's Cover Texts may be placed on covers that bracket the Document within the aggregate, or the ! electronic equivalent of covers if the Document is in electronic form. Otherwise they must appear on printed covers that bracket the whole aggregate. !

    14. TRANSLATION ! !

      Translation is considered a kind of modification, so you may ! distribute translations of the Document under the terms of section 4. Replacing Invariant Sections with translations requires special permission from their copyright holders, but you may include translations of some or all Invariant Sections in addition to the *************** the original English version of this Lic *** 438,485 **** of those notices and disclaimers. In case of a disagreement between the translation and the original version of this License or a notice or disclaimer, the original version will prevail. !

      !

      If a section in the Document is Entitled “Acknowledgements”, “Dedications”, or “History”, the requirement (section 4) to Preserve its Title (section 1) will typically require changing the actual title. -

      -
    15. TERMINATION !

      You may not copy, modify, sublicense, or distribute the Document except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense, or distribute it is void, and will automatically terminate your rights under this License. !

      !

      However, if you cease all violation of this License, then your license from a particular copyright holder is reinstated (a) provisionally, unless and until the copyright holder explicitly and finally terminates your license, and (b) permanently, if the copyright holder fails to notify you of the violation by some reasonable means prior to 60 days after the cessation. !

      !

      Moreover, your license from a particular copyright holder is reinstated permanently if the copyright holder notifies you of the violation by some reasonable means, this is the first time you have received notice of violation of this License (for any work) from that copyright holder, and you cure the violation prior to 30 days after your receipt of the notice. !

      !

      Termination of your rights under this section does not terminate the licenses of parties who have received copies or rights from you under this License. If your rights have been terminated and not permanently reinstated, receipt of a copy of some or all of the same material does not give you any rights to use it. -

      -
    16. FUTURE REVISIONS OF THIS LICENSE !

      The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. See http://www.gnu.org/copyleft/. !

      !

      Each version of the License is given a distinguishing version number. If the Document specifies that a particular numbered version of this License “or any later version” applies to it, you have the option of following the terms and conditions either of that specified version or --- 387,434 ---- of those notices and disclaimers. In case of a disagreement between the translation and the original version of this License or a notice or disclaimer, the original version will prevail. ! !

      If a section in the Document is Entitled “Acknowledgements”, “Dedications”, or “History”, the requirement (section 4) to Preserve its Title (section 1) will typically require changing the actual title. !

    17. TERMINATION ! !

      You may not copy, modify, sublicense, or distribute the Document except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense, or distribute it is void, and will automatically terminate your rights under this License. ! !

      However, if you cease all violation of this License, then your license from a particular copyright holder is reinstated (a) provisionally, unless and until the copyright holder explicitly and finally terminates your license, and (b) permanently, if the copyright holder fails to notify you of the violation by some reasonable means prior to 60 days after the cessation. ! !

      Moreover, your license from a particular copyright holder is reinstated permanently if the copyright holder notifies you of the violation by some reasonable means, this is the first time you have received notice of violation of this License (for any work) from that copyright holder, and you cure the violation prior to 30 days after your receipt of the notice. ! !

      Termination of your rights under this section does not terminate the licenses of parties who have received copies or rights from you under this License. If your rights have been terminated and not permanently reinstated, receipt of a copy of some or all of the same material does not give you any rights to use it. !

    18. FUTURE REVISIONS OF THIS LICENSE ! !

      The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. See http://www.gnu.org/copyleft/. ! !

      Each version of the License is given a distinguishing version number. If the Document specifies that a particular numbered version of this License “or any later version” applies to it, you have the option of following the terms and conditions either of that specified version or *************** Free Software Foundation. If the Docume *** 488,571 **** number of this License, you may choose any version ever published (not as a draft) by the Free Software Foundation. If the Document specifies that a proxy can decide which future versions of this ! License can be used, that proxy’s public statement of acceptance of a version permanently authorizes you to choose that version for the Document. -

      -
    19. RELICENSING !

      “Massive Multiauthor Collaboration Site” (or “MMC Site”) means any World Wide Web server that publishes copyrightable works and also provides prominent facilities for anybody to edit those works. A public wiki that anybody can edit is an example of such a server. A “Massive Multiauthor Collaboration” (or “MMC”) contained in the site means any set of copyrightable works thus published on the MMC site. !

      !

      “CC-BY-SA” means the Creative Commons Attribution-Share Alike 3.0 license published by Creative Commons Corporation, a not-for-profit corporation with a principal place of business in San Francisco, California, as well as future copyleft versions of that license published by that same organization. !

      !

      “Incorporate” means to publish or republish a Document, in whole or in part, as part of another Document. !

      !

      An MMC is “eligible for relicensing” if it is licensed under this License, and if all works that were first published under this License somewhere other than this MMC, and subsequently incorporated in whole or in part into the MMC, (1) had no cover texts or invariant sections, and (2) were thus incorporated prior to November 1, 2008. !

      !

      The operator of an MMC Site may republish an MMC contained in the site under CC-BY-SA on the same site at any time before August 1, 2009, provided the MMC is eligible for relicensing. -

      -
    ! !

    ADDENDUM: How to use this License for your documents

    To use this License in a document you have written, include a copy of the License in the document and put the following copyright and license notices just after the title page: -

    -
    - 
      Copyright (C)  year  your name.
-   Permission is granted to copy, distribute and/or modify this document
-   under the terms of the GNU Free Documentation License, Version 1.3
-   or any later version published by the Free Software Foundation;
-   with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
-   Texts.  A copy of the license is included in the section entitled ``GNU
-   Free Documentation License''.
-
    !

    If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts, replace the “with...Texts.” line with this: -

    -
    - 
        with the Invariant Sections being list their titles, with
-     the Front-Cover Texts being list, and with the Back-Cover Texts
-     being list.
-
    !

    If you have Invariant Sections without Cover Texts, or some other combination of the three, merge those two alternatives to suit the situation. !

    !

    If your document contains nontrivial examples of program code, we recommend releasing these examples in parallel under your choice of free software license, such as the GNU General Public License, to permit their use in free software. -

    - -
    -

    Return to the GCC Installation page -

    - -
    - - --- 437,515 ---- number of this License, you may choose any version ever published (not as a draft) by the Free Software Foundation. If the Document specifies that a proxy can decide which future versions of this ! License can be used, that proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Document. !
  3. RELICENSING ! !

    “Massive Multiauthor Collaboration Site” (or “MMC Site”) means any World Wide Web server that publishes copyrightable works and also provides prominent facilities for anybody to edit those works. A public wiki that anybody can edit is an example of such a server. A “Massive Multiauthor Collaboration” (or “MMC”) contained in the site means any set of copyrightable works thus published on the MMC site. ! !

    “CC-BY-SA” means the Creative Commons Attribution-Share Alike 3.0 license published by Creative Commons Corporation, a not-for-profit corporation with a principal place of business in San Francisco, California, as well as future copyleft versions of that license published by that same organization. ! !

    “Incorporate” means to publish or republish a Document, in whole or in part, as part of another Document. ! !

    An MMC is “eligible for relicensing” if it is licensed under this License, and if all works that were first published under this License somewhere other than this MMC, and subsequently incorporated in whole or in part into the MMC, (1) had no cover texts or invariant sections, and (2) were thus incorporated prior to November 1, 2008. ! !

    The operator of an MMC Site may republish an MMC contained in the site under CC-BY-SA on the same site at any time before August 1, 2009, provided the MMC is eligible for relicensing. !

! !

ADDENDUM: How to use this License for your documents

To use this License in a document you have written, include a copy of the License in the document and put the following copyright and license notices just after the title page: ! 

       Copyright (C)  year  your name.
!        Permission is granted to copy, distribute and/or modify this document
!        under the terms of the GNU Free Documentation License, Version 1.3
!        or any later version published by the Free Software Foundation;
!        with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
!        Texts.  A copy of the license is included in the section entitled ``GNU
!        Free Documentation License''.
!
!

If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts, replace the “with...Texts.” line with this: ! 

         with the Invariant Sections being list their titles, with
!          the Front-Cover Texts being list, and with the Back-Cover Texts
!          being list.
!
!

If you have Invariant Sections without Cover Texts, or some other combination of the three, merge those two alternatives to suit the situation. ! !

If your document contains nontrivial examples of program code, we recommend releasing these examples in parallel under your choice of free software license, such as the GNU General Public License, to permit their use in free software. + + + + +

+

Return to the GCC Installation page + + + diff -Nrcpad gcc-4.8.2/INSTALL/index.html gcc-4.8.3/INSTALL/index.html *** gcc-4.8.2/INSTALL/index.html Wed Oct 16 07:28:00 2013 --- gcc-4.8.3/INSTALL/index.html Thu May 22 09:13:50 2014 *************** *** 1,165 **** ! ! ! ! ! ! Installing GCC ! ! ! ! ! ! ! ! ! ! ! ! !

Installing GCC

! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

The latest version of this document is always available at ! http://gcc.gnu.org/install/. It refers to the current development sources, instructions for specific released versions are included with the sources. !

!

This document describes the generic installation procedure for GCC as well as detailing some target specific installation instructions. !

!

GCC includes several components that previously were separate distributions with their own installation instructions. This document supersedes all package-specific installation instructions. !

!

Before starting the build/install procedure please check the ! host/target specific installation notes. We recommend you browse the entire generic installation instructions before you proceed. !

!

Lists of successful builds for released versions of GCC are ! available at http://gcc.gnu.org/buildstat.html. These lists are updated as new information becomes available. -

-

The installation procedure itself is broken into five steps. -

-
    -
  1. Prerequisites -
  2. Downloading the source -
  3. Configuration -
  4. Building -
  5. Testing (optional) -
  6. Final install -
!

Please note that GCC does not support ‘make uninstall’ and probably ! won’t do so in the near future as this would open a can of worms. Instead, we suggest that you install GCC into a directory of its own and simply remove that directory when you do not need that specific version of GCC any longer, and, if shared libraries are installed there as well, no more binaries exist that use them. !

!

There are also some old installation instructions, which are mostly obsolete but still contain some information which has not yet been merged into the main part of this manual. !

!
!

Return to the GCC Installation page !

!

Copyright © 1988-2013 Free Software Foundation, Inc. !


!

Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, the Front-Cover texts being (a) (see below), and with the Back-Cover Texts being (b) (see below). A copy of the ! license is included in the section entitled “GNU ! Free Documentation License”. !

!

(a) The FSF’s Front-Cover Text is: !

!

A GNU Manual !

!

(b) The FSF’s Back-Cover Text is: !

!

You have freedom to copy and modify this GNU Manual, like GNU ! software. Copies published by the Free Software Foundation raise ! funds for GNU development. !

! ! ! ! ! ! ! ! ! - - --- 1,123 ---- ! ! ! Installing GCC ! ! ! ! ! ! ! ! ! !

Installing GCC

! The latest version of this document is always available at ! http://gcc.gnu.org/install/. It refers to the current development sources, instructions for specific released versions are included with the sources. ! !

This document describes the generic installation procedure for GCC as well as detailing some target specific installation instructions. ! !

GCC includes several components that previously were separate distributions with their own installation instructions. This document supersedes all package-specific installation instructions. ! !

Before starting the build/install procedure please check the ! host/target specific installation notes. We recommend you browse the entire generic installation instructions before you proceed. ! !

Lists of successful builds for released versions of GCC are ! available at http://gcc.gnu.org/buildstat.html. These lists are updated as new information becomes available. !

The installation procedure itself is broken into five steps. ! !

    !
  1. Prerequisites !
  2. Downloading the source !
  3. Configuration !
  4. Building !
  5. Testing (optional) !
  6. Final install !
! !

Please note that GCC does not support ‘make uninstall’ and probably ! won't do so in the near future as this would open a can of worms. Instead, we suggest that you install GCC into a directory of its own and simply remove that directory when you do not need that specific version of GCC any longer, and, if shared libraries are installed there as well, no more binaries exist that use them. ! !

There are also some old installation instructions, which are mostly obsolete but still contain some information which has not yet been merged into the main part of this manual. ! !

!

Return to the GCC Installation page ! !

Copyright © 1988-2013 Free Software Foundation, Inc. ! 

! 
!
! Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, the Front-Cover texts being (a) (see below), and with the Back-Cover Texts being (b) (see below). A copy of the ! license is included in the section entitled “GNU Free Documentation License”. +

(a) The FSF's Front-Cover Text is: +

A GNU Manual +

(b) The FSF's Back-Cover Text is: +

You have freedom to copy and modify this GNU Manual, like GNU + software. Copies published by the Free Software Foundation raise + funds for GNU development. + + + + + + + + + + + + + diff -Nrcpad gcc-4.8.2/INSTALL/old.html gcc-4.8.3/INSTALL/old.html *** gcc-4.8.2/INSTALL/old.html Wed Oct 16 07:28:04 2013 --- gcc-4.8.3/INSTALL/old.html Thu May 22 09:13:50 2014 *************** *** 1,231 **** ! ! ! ! ! ! Installing GCC ! ! ! ! ! ! ! ! ! ! ! ! !

Installing GCC

! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

Old installation documentation

!

Note most of this information is out of date and superseded by the previous chapters of this manual. It is provided for historical reference only, because of a lack of volunteers to merge it into the main manual. -

!

Here is the procedure for installing GCC on a GNU or Unix system. !

!
    !
  1. If you have chosen a configuration for GCC which requires other GNU tools (such as GAS or the GNU linker) instead of the standard system tools, install the required tools in the build directory under the names ! as, ld or whatever is appropriate. !

    Alternatively, you can do subsequent compilation using a value of the PATH environment variable such that the necessary GNU tools come before the standard system tools. -

    -
  2. Specify the host, build and target machine configurations. You do this - when you run the configure script. !

    The build machine is the system which you are using, the ! host machine is the system where you want to run the resulting ! compiler (normally the build machine), and the target machine is the system for which you want the compiler to generate code. !

    !

    If you are building a compiler to produce code for the machine it runs on (a native compiler), you normally do not need to specify any operands ! to configure; it will try to guess the type of machine you are on ! and use that as the build, host and target machines. So you don’t need to specify a configuration when building a native compiler unless ! configure cannot figure out what your configuration is or guesses wrong. !

    !

    In those cases, specify the build machine’s configuration name ! with the --host option; the host and target will default to be the same as the host machine. -

    -

    Here is an example: -

    -
    - 
    ./configure --host=sparc-sun-sunos4.1
-
    !

    A configuration name may be canonical or it may be more or less abbreviated. !

    !

    A canonical configuration name has three parts, separated by dashes. ! It looks like this: ‘cpu-company-system’. ! (The three parts may themselves contain dashes; configure can figure out which dashes serve which purpose.) For example, ! ‘m68k-sun-sunos4.1’ specifies a Sun 3. !

    !

    You can also replace parts of the configuration by nicknames or aliases. ! For example, ‘sun3’ stands for ‘m68k-sun’, so ! ‘sun3-sunos4.1’ is another way to specify a Sun 3. !

    !

    You can specify a version number after any of the system types, and some of the CPU types. In most cases, the version is irrelevant, and will be ignored. So you might as well specify the version if you know it. !

    !

    See Configurations, for a list of supported configuration names and notes on many of the configurations. You should check the notes in that section before proceeding any further with the installation of GCC. -

    -
!

Configurations Supported by GCC

!

Here are the possible CPU types: !

!
!

1750a, a29k, alpha, arm, avr, cn, clipper, dsp16xx, elxsi, fr30, h8300, hppa1.0, hppa1.1, i370, i386, i486, i586, i686, i786, i860, i960, ip2k, m32r, m68000, m68k, m88k, mcore, mips, mipsel, mips64, mips64el, mn10200, mn10300, ns32k, pdp11, powerpc, powerpcle, romp, rs6000, sh, sparc, ! sparclite, sparc64, v850, vax, we32k. !

!

Here are the recognized company names. As you can see, customary abbreviations are used rather than the longer official names. !

!
!

acorn, alliant, altos, apollo, apple, att, bull, cbm, convergent, convex, crds, dec, dg, dolphin, elxsi, encore, harris, hitachi, hp, ibm, intergraph, isi, mips, motorola, ncr, next, ns, omron, plexus, ! sequent, sgi, sony, sun, tti, unicom, wrs. !

!

The company name is meaningful only to disambiguate when the rest of the information supplied is insufficient. You can omit it, writing ! just ‘cpu-system’, if it is not needed. For example, ! ‘vax-ultrix4.2’ is equivalent to ‘vax-dec-ultrix4.2’. !

!

Here is a list of system types: !

!
!

386bsd, aix, acis, amigaos, aos, aout, aux, bosx, bsd, clix, coff, ctix, cxux, dgux, dynix, ebmon, ecoff, elf, esix, freebsd, hms, genix, gnu, linux, linux-gnu, hiux, hpux, iris, irix, isc, luna, lynxos, mach, minix, msdos, mvs, netbsd, newsos, nindy, ns, osf, osfrose, ptx, riscix, riscos, rtu, sco, sim, solaris, sunos, sym, sysv, udi, ultrix, unicos, uniplus, unos, vms, vsta, ! vxworks, winnt, xenix. !

!

You can omit the system type; then configure guesses the operating system from the CPU and company. !

!

You can add a version number to the system type; this may or may not ! make a difference. For example, you can write ‘bsd4.3’ or ! ‘bsd4.4’ to distinguish versions of BSD. In practice, the version ! number is most needed for ‘sysv3’ and ‘sysv4’, which are often treated differently. !

!

‘linux-gnu’ is the canonical name for the GNU/Linux target; however ! GCC will also accept ‘linux’. The version of the kernel in use is ! not relevant on these systems. A suffix such as ‘libc1’ or ‘aout’ distinguishes major versions of the C library; all of the suffixed versions are obsolete. !

!

If you specify an impossible combination such as ‘i860-dg-vms’, ! then you may get an error message from configure, or it may ! ignore part of the information and do the best it can with the rest. ! configure always prints the canonical name for the alternative that it used. GCC does not support all possible alternatives. !

!

Often a particular model of machine has a name. Many machine names are recognized as aliases for CPU/company combinations. Thus, the machine ! name ‘sun3’, mentioned above, is an alias for ‘m68k-sun’. Sometimes we accept a company name as a machine name, when the name is popularly used for a particular machine. Here is a table of the known machine names: !

!
!

3300, 3b1, 3bn, 7300, altos3068, altos, apollo68, att-7300, balance, convex-cn, crds, decstation-3100, decstation, delta, encore, --- 1,181 ---- ! ! ! Installing GCC: Old documentation ! ! ! ! ! ! ! ! ! !

Installing GCC: Old documentation

Old installation documentation

! !

Note most of this information is out of date and superseded by the previous chapters of this manual. It is provided for historical reference only, because of a lack of volunteers to merge it into the main manual. !

Here is the procedure for installing GCC on a GNU or Unix system. ! !

    !
  1. If you have chosen a configuration for GCC which requires other GNU tools (such as GAS or the GNU linker) instead of the standard system tools, install the required tools in the build directory under the names ! as, ld or whatever is appropriate. !

    Alternatively, you can do subsequent compilation using a value of the PATH environment variable such that the necessary GNU tools come before the standard system tools. !

  2. Specify the host, build and target machine configurations. You do this ! when you run the configure script. ! !

    The build machine is the system which you are using, the ! host machine is the system where you want to run the resulting ! compiler (normally the build machine), and the target machine is the system for which you want the compiler to generate code. ! !

    If you are building a compiler to produce code for the machine it runs on (a native compiler), you normally do not need to specify any operands ! to configure; it will try to guess the type of machine you are on ! and use that as the build, host and target machines. So you don't need to specify a configuration when building a native compiler unless ! configure cannot figure out what your configuration is or guesses wrong. ! !

    In those cases, specify the build machine's configuration name ! with the --host option; the host and target will default to be the same as the host machine. !

    Here is an example: ! ! 

              ./configure --host=sparc-sun-sunos4.1
!
    !

    A configuration name may be canonical or it may be more or less abbreviated. ! !

    A canonical configuration name has three parts, separated by dashes. ! It looks like this: ‘cpu-company-system’. ! (The three parts may themselves contain dashes; configure can figure out which dashes serve which purpose.) For example, ! ‘m68k-sun-sunos4.1’ specifies a Sun 3. ! !

    You can also replace parts of the configuration by nicknames or aliases. ! For example, ‘sun3’ stands for ‘m68k-sun’, so ! ‘sun3-sunos4.1’ is another way to specify a Sun 3. ! !

    You can specify a version number after any of the system types, and some of the CPU types. In most cases, the version is irrelevant, and will be ignored. So you might as well specify the version if you know it. ! !

    See Configurations, for a list of supported configuration names and notes on many of the configurations. You should check the notes in that section before proceeding any further with the installation of GCC. !

!

Configurations Supported by GCC

! Here are the possible CPU types: ! !
! ! 1750a, a29k, alpha, arm, avr, cn, clipper, dsp16xx, elxsi, fr30, h8300, hppa1.0, hppa1.1, i370, i386, i486, i586, i686, i786, i860, i960, ip2k, m32r, m68000, m68k, m88k, mcore, mips, mipsel, mips64, mips64el, mn10200, mn10300, ns32k, pdp11, powerpc, powerpcle, romp, rs6000, sh, sparc, ! sparclite, sparc64, v850, vax, we32k. !
!

Here are the recognized company names. As you can see, customary abbreviations are used rather than the longer official names. ! ! !

! acorn, alliant, altos, apollo, apple, att, bull, cbm, convergent, convex, crds, dec, dg, dolphin, elxsi, encore, harris, hitachi, hp, ibm, intergraph, isi, mips, motorola, ncr, next, ns, omron, plexus, ! sequent, sgi, sony, sun, tti, unicom, wrs. !
!

The company name is meaningful only to disambiguate when the rest of the information supplied is insufficient. You can omit it, writing ! just ‘cpu-system’, if it is not needed. For example, ! ‘vax-ultrix4.2’ is equivalent to ‘vax-dec-ultrix4.2’. ! !

Here is a list of system types: ! !

! 386bsd, aix, acis, amigaos, aos, aout, aux, bosx, bsd, clix, coff, ctix, cxux, dgux, dynix, ebmon, ecoff, elf, esix, freebsd, hms, genix, gnu, linux, linux-gnu, hiux, hpux, iris, irix, isc, luna, lynxos, mach, minix, msdos, mvs, netbsd, newsos, nindy, ns, osf, osfrose, ptx, riscix, riscos, rtu, sco, sim, solaris, sunos, sym, sysv, udi, ultrix, unicos, uniplus, unos, vms, vsta, ! vxworks, winnt, xenix. !
!

You can omit the system type; then configure guesses the operating system from the CPU and company. ! !

You can add a version number to the system type; this may or may not ! make a difference. For example, you can write ‘bsd4.3’ or ! ‘bsd4.4’ to distinguish versions of BSD. In practice, the version ! number is most needed for ‘sysv3’ and ‘sysv4’, which are often treated differently. ! !

‘linux-gnu’ is the canonical name for the GNU/Linux target; however ! GCC will also accept ‘linux’. The version of the kernel in use is ! not relevant on these systems. A suffix such as ‘libc1’ or ‘aout’ distinguishes major versions of the C library; all of the suffixed versions are obsolete. ! !

If you specify an impossible combination such as ‘i860-dg-vms’, ! then you may get an error message from configure, or it may ! ignore part of the information and do the best it can with the rest. ! configure always prints the canonical name for the alternative that it used. GCC does not support all possible alternatives. ! !

Often a particular model of machine has a name. Many machine names are recognized as aliases for CPU/company combinations. Thus, the machine ! name ‘sun3’, mentioned above, is an alias for ‘m68k-sun’. Sometimes we accept a company name as a machine name, when the name is popularly used for a particular machine. Here is a table of the known machine names: ! !

! 3300, 3b1, 3bn, 7300, altos3068, altos, apollo68, att-7300, balance, convex-cn, crds, decstation-3100, decstation, delta, encore, *************** m3230, magnum, merlin, miniframe, *** 236,253 **** mmax, news-3600, news800, news, next, pbd, pc532, pmax, powerpc, powerpcle, ps2, risc-news, rtpc, sun2, sun386i, sun386, sun3, ! sun4, symmetry, tower-32, tower. !

!

Remember that a machine name specifies both the cpu type and the company ! name.

Return to the GCC Installation page -

- - - - - --- 186,201 ---- mmax, news-3600, news800, news, next, pbd, pc532, pmax, powerpc, powerpcle, ps2, risc-news, rtpc, sun2, sun386i, sun386, sun3, ! sun4, symmetry, tower-32, tower. !
!

Remember that a machine name specifies both the cpu type and the company ! name.

Return to the GCC Installation page + + + + diff -Nrcpad gcc-4.8.2/INSTALL/prerequisites.html gcc-4.8.3/INSTALL/prerequisites.html *** gcc-4.8.2/INSTALL/prerequisites.html Wed Oct 16 07:28:01 2013 --- gcc-4.8.3/INSTALL/prerequisites.html Thu May 22 09:13:50 2014 *************** *** 1,405 **** ! ! ! ! ! ! Installing GCC ! ! ! ! ! ! ! ! ! ! ! ! !

Installing GCC

! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

GCC requires that various tools and packages be available for use in the build procedure. Modifying GCC sources requires additional tools described below. !

! !

Tools/packages necessary for building GCC

!
!
ISO C++98 compiler
!

Necessary to bootstrap GCC, although versions of GCC prior to 4.8 also allow bootstrapping with a ISO C89 compiler and versions of GCC prior to 3.4 also allow bootstrapping with a traditional (K&R) C compiler. !

!

To build all languages in a cross-compiler or other configuration where 3-stage bootstrap is not performed, you need to start with an existing GCC binary (version 3.4 or later) because source code for language frontends other than C might use GCC extensions. !

!

Note that to bootstrap GCC with versions of GCC earlier than 3.4, you ! may need to use --disable-stage1-checking, though bootstrapping the compiler with such earlier compilers is strongly discouraged. !

!
!
GNAT
!
!

In order to build the Ada compiler (GNAT) you must already have GNAT installed because portions of the Ada frontend are written in Ada (with GNAT extensions.) Refer to the Ada installation instructions for more specific information. !

!
!
A “working” POSIX compatible shell, or GNU bash
!
!

Necessary when running configure because some ! /bin/sh shells have bugs and may crash when configuring the ! target libraries. In other cases, /bin/sh or ksh have disastrous corner-case performance problems. This ! can cause target configure runs to literally take days to complete in some cases. !

!

So on some platforms /bin/ksh is sufficient, on others it ! isn’t. See the host/target specific instructions for your platform, or ! use bash to be sure. Then set CONFIG_SHELL in your environment to your “good” shell prior to running ! configure/make. !

!

zsh is not a fully compliant POSIX shell and will not work when configuring GCC. !

!
!
A POSIX or SVR4 awk
!
!

Necessary for creating some of the generated source files for GCC. If in doubt, use a recent GNU awk version, as some of the older ones are broken. GNU awk version 3.1.5 is known to work. !

!
!
GNU binutils
!
!

Necessary in some circumstances, optional in others. See the host/target specific instructions for your platform for the exact requirements. !

!
!
gzip version 1.2.4 (or later) or
!
bzip2 version 1.0.2 (or later)
!
!

Necessary to uncompress GCC tar files when source code is obtained via FTP mirror sites. !

!
!
GNU make version 3.80 (or later)
!
!

You must have GNU make installed to build GCC. !

!
!
GNU tar version 1.14 (or later)
!
!

Necessary (only on some platforms) to untar the source code. Many ! systems’ tar programs will also work, only try GNU ! tar if you have problems. !

!
!
Perl version 5.6.1 (or later)
!
!

Necessary when targeting Darwin, building ‘libstdc++’, ! and not using --disable-symvers. ! Necessary when targeting Solaris 2 with Sun ld and not using ! --disable-symvers. The bundled perl in Solaris 8 and up works. !

!

Necessary when regenerating Makefile dependencies in libiberty. ! Necessary when regenerating libiberty/functions.texi. ! Necessary when generating manpages from Texinfo manuals. Used by various scripts to generate some files included in SVN (mainly Unicode-related and rarely changing) from source tables. !

!
!
jar, or InfoZIP (zip and unzip)
!
!

Necessary to build libgcj, the GCJ runtime. !

!
!

Several support libraries are necessary to build GCC, some are required, others optional. While any sufficiently new version of required tools usually work, library requirements are generally stricter. Newer ! versions may work in some cases, but it’s safer to use the exact versions documented. We appreciate bug reports about problems with newer versions, though. If your OS vendor provides packages for the support libraries then using those packages may be the simplest way to install the libraries. !

!
!
GNU Multiple Precision Library (GMP) version 4.3.2 (or later)
!
!

Necessary to build GCC. If a GMP source distribution is found in a ! subdirectory of your GCC sources named gmp, it will be built together with GCC. Alternatively, if GMP is already installed but it is not in your library search path, you will have to configure with the ! --with-gmp configure option. See also --with-gmp-lib ! and --with-gmp-include. !

!
!
MPFR Library version 2.4.2 (or later)
!
!

Necessary to build GCC. It can be downloaded from http://www.mpfr.org/. If an MPFR source distribution is found ! in a subdirectory of your GCC sources named mpfr, it will be built together with GCC. Alternatively, if MPFR is already installed but it is not in your default library search path, the ! --with-mpfr configure option should be used. See also ! --with-mpfr-lib and --with-mpfr-include. !

!
!
MPC Library version 0.8.1 (or later)
!
!

Necessary to build GCC. It can be downloaded from http://www.multiprecision.org/. If an MPC source distribution ! is found in a subdirectory of your GCC sources named mpc, it will be built together with GCC. Alternatively, if MPC is already installed but it is not in your default library search path, the ! --with-mpc configure option should be used. See also ! --with-mpc-lib and --with-mpc-include. !

!
!
ISL Library version 0.11.1
!
!

Necessary to build GCC with the Graphite loop optimizations. It can be downloaded from ftp://gcc.gnu.org/pub/gcc/infrastructure/ ! as isl-0.11.1.tar.bz2. !

!

The --with-isl configure option should be used if ISL is not installed in your default library search path. !

!
!
CLooG 0.18.0
!
!

Necessary to build GCC with the Graphite loop optimizations. It can be downloaded from ftp://gcc.gnu.org/pub/gcc/infrastructure/ as ! cloog-0.18.0.tar.gz. The --with-cloog configure option should ! be used if CLooG is not installed in your default library search path. ! CLooG needs to be built against ISL 0.11.1. Use --with-isl=system to direct CLooG to pick up an already installed ISL, otherwise it will use ISL 0.11.1 as bundled with CLooG. CLooG needs to be configured to use GMP ! internally, use --with-bits=gmp to direct it to do that. !

!
!
! !

Tools/packages necessary for modifying GCC

!
!
autoconf version 2.64
!
GNU m4 version 1.4.6 (or later)
!
!

Necessary when modifying configure.ac, aclocal.m4, etc. ! to regenerate configure and config.in files. !

!
!
automake version 1.11.1
!
!

Necessary when modifying a Makefile.am file to regenerate its ! associated Makefile.in. !

!

Much of GCC does not use automake, so directly edit the Makefile.in ! file. Specifically this applies to the gcc, intl, ! libcpp, libiberty, libobjc directories as well as any of their subdirectories. !

!

For directories that use automake, GCC requires the latest release in the 1.11 series, which is currently 1.11.1. When regenerating a directory to a newer version, please update all the directories using an older 1.11 to the latest released version. !

!
!
gettext version 0.14.5 (or later)
!
!

Needed to regenerate gcc.pot. !

!
!
gperf version 2.7.2 (or later)
!
!

Necessary when modifying gperf input files, e.g. ! gcc/cp/cfns.gperf to regenerate its associated header file, e.g. ! gcc/cp/cfns.h. !

!
!
DejaGnu 1.4.4
!
Expect
!
Tcl
!
!

Necessary to run the GCC testsuite; see the section on testing for details. !

!
!
autogen version 5.5.4 (or later) and
!
guile version 1.4.1 (or later)
!
!

Necessary to regenerate fixinc/fixincl.x from ! fixinc/inclhack.def and fixinc/*.tpl. !

!

Necessary to run ‘make check’ for fixinc. !

!

Necessary to regenerate the top level Makefile.in file from ! Makefile.tpl and Makefile.def. !

!
!
Flex version 2.5.4 (or later)
!
!

Necessary when modifying *.l files. !

!

Necessary to build GCC during development because the generated output files are not included in the SVN repository. They are included in releases. !

!
!
Texinfo version 4.7 (or later)
!
!

Necessary for running makeinfo when modifying *.texi files to test your changes. !

!

Necessary for running make dvi or make pdf to create printable documentation in DVI or PDF format. Texinfo version ! 4.8 or later is required for make pdf. !

!

Necessary to build GCC documentation during development because the generated output files are not included in the SVN repository. They are included in releases. -

-
-
TeX (any working version)
-
-

Necessary for running texi2dvi and texi2pdf, which - are used when running make dvi or make pdf to create - DVI or PDF files, respectively. -

-
-
SVN (any version)
-
SSH (any version)
-
-

Necessary to access the SVN repository. Public releases and weekly - snapshots of the development sources are also available via FTP. -

-
-
GNU diffutils version 2.7 (or later)
-
-

Useful when submitting patches for the GCC source code. -

-
-
patch version 2.5.4 (or later)
-
-

Necessary when applying patches, created with diff, to one’s - own sources. -

-
-
ecj1
-
gjavah
-
-

If you wish to modify .java files in libjava, you will need to - configure with --enable-java-maintainer-mode, and you will need - to have executables named ecj1 and gjavah in your path. - The ecj1 executable should run the Eclipse Java compiler via - the GCC-specific entry point. You can download a suitable jar from - ftp://sourceware.org/pub/java/, or by running the script - contrib/download_ecj. -

-
-
antlr.jar version 2.7.1 (or later)
-
antlr binary
-
-

If you wish to build the gjdoc binary in libjava, you will - need to have an antlr.jar library available. The library is - searched for in system locations but can be specified with - --with-antlr-jar= instead. When configuring with - --enable-java-maintainer-mode, you will need to have one of - the executables named cantlr, runantlr or - antlr in your path. -

-
-
- -
-

Return to the GCC Installation page -

- - - - - --- 1,296 ---- ! ! ! Prerequisites for GCC ! ! ! ! ! ! ! ! ! !

Prerequisites for GCC

! ! GCC requires that various tools and packages be available for use in the build procedure. Modifying GCC sources requires additional tools described below. ! !

Tools/packages necessary for building GCC

! !
!
ISO C++98 compiler
Necessary to bootstrap GCC, although versions of GCC prior to 4.8 also allow bootstrapping with a ISO C89 compiler and versions of GCC prior to 3.4 also allow bootstrapping with a traditional (K&R) C compiler. ! !

To build all languages in a cross-compiler or other configuration where 3-stage bootstrap is not performed, you need to start with an existing GCC binary (version 3.4 or later) because source code for language frontends other than C might use GCC extensions. ! !

Note that to bootstrap GCC with versions of GCC earlier than 3.4, you ! may need to use --disable-stage1-checking, though bootstrapping the compiler with such earlier compilers is strongly discouraged. ! !

GNAT
! In order to build the Ada compiler (GNAT) you must already have GNAT installed because portions of the Ada frontend are written in Ada (with GNAT extensions.) Refer to the Ada installation instructions for more specific information. ! !
A “working” POSIX compatible shell, or GNU bash
! Necessary when running configure because some ! /bin/sh shells have bugs and may crash when configuring the ! target libraries. In other cases, /bin/sh or ksh have disastrous corner-case performance problems. This ! can cause target configure runs to literally take days to complete in some cases. ! !

So on some platforms /bin/ksh is sufficient, on others it ! isn't. See the host/target specific instructions for your platform, or ! use bash to be sure. Then set CONFIG_SHELL in your environment to your “good” shell prior to running ! configure/make. ! !

zsh is not a fully compliant POSIX shell and will not work when configuring GCC. ! !

A POSIX or SVR4 awk
! Necessary for creating some of the generated source files for GCC. If in doubt, use a recent GNU awk version, as some of the older ones are broken. GNU awk version 3.1.5 is known to work. ! !
GNU binutils
! Necessary in some circumstances, optional in others. See the host/target specific instructions for your platform for the exact requirements. ! !
gzip version 1.2.4 (or later) or
bzip2 version 1.0.2 (or later)
! Necessary to uncompress GCC tar files when source code is obtained via FTP mirror sites. ! !
GNU make version 3.80 (or later)
! You must have GNU make installed to build GCC. ! !
GNU tar version 1.14 (or later)
! Necessary (only on some platforms) to untar the source code. Many ! systems' tar programs will also work, only try GNU ! tar if you have problems. ! !
Perl version 5.6.1 (or later)
! Necessary when targeting Darwin, building ‘libstdc++’, ! and not using --disable-symvers. ! Necessary when targeting Solaris 2 with Sun ld and not using ! --disable-symvers. The bundled perl in Solaris 8 and up works. ! !

Necessary when regenerating Makefile dependencies in libiberty. ! Necessary when regenerating libiberty/functions.texi. ! Necessary when generating manpages from Texinfo manuals. Used by various scripts to generate some files included in SVN (mainly Unicode-related and rarely changing) from source tables. ! !

jar, or InfoZIP (zip and unzip)
! Necessary to build libgcj, the GCJ runtime. !
!

Several support libraries are necessary to build GCC, some are required, others optional. While any sufficiently new version of required tools usually work, library requirements are generally stricter. Newer ! versions may work in some cases, but it's safer to use the exact versions documented. We appreciate bug reports about problems with newer versions, though. If your OS vendor provides packages for the support libraries then using those packages may be the simplest way to install the libraries. ! !

!
GNU Multiple Precision Library (GMP) version 4.3.2 (or later)
! Necessary to build GCC. If a GMP source distribution is found in a ! subdirectory of your GCC sources named gmp, it will be built together with GCC. Alternatively, if GMP is already installed but it is not in your library search path, you will have to configure with the ! --with-gmp configure option. See also --with-gmp-lib ! and --with-gmp-include. ! !
MPFR Library version 2.4.2 (or later)
! Necessary to build GCC. It can be downloaded from http://www.mpfr.org/. If an MPFR source distribution is found ! in a subdirectory of your GCC sources named mpfr, it will be built together with GCC. Alternatively, if MPFR is already installed but it is not in your default library search path, the ! --with-mpfr configure option should be used. See also ! --with-mpfr-lib and --with-mpfr-include. ! !
MPC Library version 0.8.1 (or later)
! Necessary to build GCC. It can be downloaded from http://www.multiprecision.org/. If an MPC source distribution ! is found in a subdirectory of your GCC sources named mpc, it will be built together with GCC. Alternatively, if MPC is already installed but it is not in your default library search path, the ! --with-mpc configure option should be used. See also ! --with-mpc-lib and --with-mpc-include. ! !
ISL Library version 0.11.1
! Necessary to build GCC with the Graphite loop optimizations. It can be downloaded from ftp://gcc.gnu.org/pub/gcc/infrastructure/ ! as isl-0.11.1.tar.bz2. ! !

The --with-isl configure option should be used if ISL is not installed in your default library search path. ! !

CLooG 0.18.0
! Necessary to build GCC with the Graphite loop optimizations. It can be downloaded from ftp://gcc.gnu.org/pub/gcc/infrastructure/ as ! cloog-0.18.0.tar.gz. The --with-cloog configure option should ! be used if CLooG is not installed in your default library search path. ! CLooG needs to be built against ISL 0.11.1. Use --with-isl=system to direct CLooG to pick up an already installed ISL, otherwise it will use ISL 0.11.1 as bundled with CLooG. CLooG needs to be configured to use GMP ! internally, use --with-bits=gmp to direct it to do that. !
! !

Tools/packages necessary for modifying GCC

! !
!
autoconf version 2.64
GNU m4 version 1.4.6 (or later)
! Necessary when modifying configure.ac, aclocal.m4, etc. ! to regenerate configure and config.in files. ! !
automake version 1.11.1
! Necessary when modifying a Makefile.am file to regenerate its ! associated Makefile.in. ! !

Much of GCC does not use automake, so directly edit the Makefile.in ! file. Specifically this applies to the gcc, intl, ! libcpp, libiberty, libobjc directories as well as any of their subdirectories. ! !

For directories that use automake, GCC requires the latest release in the 1.11 series, which is currently 1.11.1. When regenerating a directory to a newer version, please update all the directories using an older 1.11 to the latest released version. ! !

gettext version 0.14.5 (or later)
! Needed to regenerate gcc.pot. ! !
gperf version 2.7.2 (or later)
! Necessary when modifying gperf input files, e.g. ! gcc/cp/cfns.gperf to regenerate its associated header file, e.g. ! gcc/cp/cfns.h. ! !
DejaGnu 1.4.4
Expect
Tcl
! Necessary to run the GCC testsuite; see the section on testing for details. ! !
autogen version 5.5.4 (or later) and
guile version 1.4.1 (or later)
! Necessary to regenerate fixinc/fixincl.x from ! fixinc/inclhack.def and fixinc/*.tpl. ! !

Necessary to run ‘make check’ for fixinc. ! !

Necessary to regenerate the top level Makefile.in file from ! Makefile.tpl and Makefile.def. ! !

Flex version 2.5.4 (or later)
! Necessary when modifying *.l files. ! !

Necessary to build GCC during development because the generated output files are not included in the SVN repository. They are included in releases. ! !

Texinfo version 4.7 (or later)
! Necessary for running makeinfo when modifying *.texi files to test your changes. ! !

Necessary for running make dvi or make pdf to create printable documentation in DVI or PDF format. Texinfo version ! 4.8 or later is required for make pdf. ! !

Necessary to build GCC documentation during development because the generated output files are not included in the SVN repository. They are included in releases. +

TeX (any working version)
+ Necessary for running texi2dvi and texi2pdf, which + are used when running make dvi or make pdf to create + DVI or PDF files, respectively. +
SVN (any version)
SSH (any version)
+ Necessary to access the SVN repository. Public releases and weekly + snapshots of the development sources are also available via FTP. +
GNU diffutils version 2.7 (or later)
+ Useful when submitting patches for the GCC source code. +
patch version 2.5.4 (or later)
+ Necessary when applying patches, created with diff, to one's + own sources. +
ecj1
gjavah
+ If you wish to modify .java files in libjava, you will need to + configure with --enable-java-maintainer-mode, and you will need + to have executables named ecj1 and gjavah in your path. + The ecj1 executable should run the Eclipse Java compiler via + the GCC-specific entry point. You can download a suitable jar from + ftp://sourceware.org/pub/java/, or by running the script + contrib/download_ecj. +
antlr.jar version 2.7.1 (or later)
antlr binary
+ If you wish to build the gjdoc binary in libjava, you will + need to have an antlr.jar library available. The library is + searched for in system locations but can be specified with + --with-antlr-jar= instead. When configuring with + --enable-java-maintainer-mode, you will need to have one of + the executables named cantlr, runantlr or + antlr in your path. +
+

+

Return to the GCC Installation page + + + + + + + + + + + + diff -Nrcpad gcc-4.8.2/INSTALL/specific.html gcc-4.8.3/INSTALL/specific.html *** gcc-4.8.2/INSTALL/specific.html Wed Oct 16 07:28:00 2013 --- gcc-4.8.3/INSTALL/specific.html Thu May 22 09:13:50 2014 *************** *** 1,675 **** ! ! ! ! ! ! Installing GCC ! ! ! ! ! ! ! ! ! ! ! ! !

Installing GCC

! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

Please read this document carefully before installing the GNU Compiler Collection on your machine. !

!

Note that this list of install notes is not a list of supported hosts or targets. Not all supported hosts and targets are listed here, only the ones that require host-specific or target-specific ! information have to. !

! ! ! !
!

alpha*-*-*

This section contains general configuration information for all alpha-based platforms using ELF (in particular, ignore this section for DEC OSF/1, Digital UNIX and Tru64 UNIX). In addition to reading this section, please read all other sections that match your target. !

!

We require binutils 2.11.2 or newer. Previous binutils releases had a number of problems with DWARF 2 debugging information, not the least of which is incorrect linking of shared libraries. !

!
!

alpha*-dec-osf5.1

Systems using processors that implement the DEC Alpha architecture and are running the DEC/Compaq/HP Unix (DEC OSF/1, Digital UNIX, or Compaq/HP Tru64 UNIX) operating system, for example the DEC Alpha AXP systems. !

!

Support for Tru64 UNIX V5.1 has been removed in GCC 4.8. As of GCC 4.6, support for Tru64 UNIX V4.0 and V5.0 has been removed. As of GCC 3.2, versions before alpha*-dec-osf4 are no longer supported. (These are the versions which identify themselves as DEC OSF/1.) -

-
-

amd64-*-solaris2.1[0-9]*

!

This is a synonym for ‘x86_64-*-solaris2.1[0-9]*’. !

!
!

arm-*-eabi

ARM-family processors. Subtargets that use the ELF object format require GNU binutils 2.13 or newer. Such subtargets include: arm-*-netbsdelf, arm-*-*linux-* and arm-*-rtemseabi. !

!
!

avr

ATMEL AVR-family micro controllers. These are used in embedded ! applications. There are no standard Unix configurations. See “AVR Options” in the main manual for the list of supported MCU types. !

!

Use ‘configure --target=avr --enable-languages="c"’ to configure GCC. !

!

Further installation notes and other useful information about AVR tools can also be obtained from: -

- !

We strongly recommend using binutils 2.13 or newer. !

!

The following error: !

! 
Error: register required
!
!

indicates that you should upgrade to a newer version of the binutils. !

!
!

Blackfin

!

The Blackfin processor, an Analog Devices DSP. See “Blackfin Options” in the main manual !

!

More information, and a version of binutils with support for this processor, is available at http://blackfin.uclinux.org -

-
-

CR16

!

The CR16 CompactRISC architecture is a 16-bit architecture. This architecture is used in embedded applications. -

!

See “CR16 Options” in the main manual for a list of CR16-specific options. !

!

Use ‘configure --target=cr16-elf --enable-languages=c,c++’ to configure ! GCC for building a CR16 elf cross-compiler. !

!

Use ‘configure --target=cr16-uclinux --enable-languages=c,c++’ to configure ! GCC for building a CR16 uclinux cross-compiler. !

!
!

CRIS

CRIS is the CPU architecture in Axis Communications ETRAX system-on-a-chip series. These are used in embedded applications. !

!

See “CRIS Options” in the main manual for a list of CRIS-specific options. !

!

There are a few different CRIS targets: !

!
cris-axis-elf
!

Mainly for monolithic embedded systems. Includes a multilib for the ! ‘v10’ core used in ‘ETRAX 100 LX’. !

!
cris-axis-linux-gnu
!

A GNU/Linux port for the CRIS architecture, currently targeting ! ‘ETRAX 100 LX’ by default. !

!

For cris-axis-elf you need binutils 2.11 or newer. For cris-axis-linux-gnu you need binutils 2.12 or newer. !

!

Pre-packaged tools can be obtained from ftp://ftp.axis.com/pub/axis/tools/cris/compiler-kit/. More information about this platform is available at http://developer.axis.com/. !

!
!

DOS

Please have a look at the binaries page. !

!

You cannot install GCC by itself on MSDOS; it will not compile under any MSDOS compiler except itself. You need to get the complete compilation package DJGPP, which includes binaries as well as sources, and includes all the necessary compilation tools and libraries. !

!
!

epiphany-*-elf

!

Adapteva Epiphany. This configuration is intended for embedded systems. !

!
!

*-*-freebsd*

Support for FreeBSD 1 was discontinued in GCC 3.2. Support for FreeBSD 2 (and any mutant a.out variants of FreeBSD 3) was discontinued in GCC 4.0. !

!

In order to better utilize FreeBSD base system functionality and match the configuration of the system compiler, GCC 4.5 and above as well as GCC 4.4 past 2010-06-20 leverage SSP support in libc (which is present on FreeBSD 7 or later) and the use of __cxa_atexit by default (on FreeBSD 6 or later). The use of dl_iterate_phdr inside ! libgcc_s.so.1 and boehm-gc (on FreeBSD 7 or later) is enabled by GCC 4.5 and above. !

!

We support FreeBSD using the ELF file format with DWARF 2 debugging ! for all CPU architectures. You may use -gstabs instead of ! -g, if you really want the old debugging format. There are no known issues with mixing object files and libraries with different debugging formats. Otherwise, this release of GCC should now match more of the configuration used in the stock FreeBSD configuration of ! GCC. In particular, --enable-threads is now configured by default. However, as a general user, do not attempt to replace the system compiler with this release. Known to bootstrap and check with good results on FreeBSD 7.2-STABLE. In the past, known to bootstrap and check with good results on FreeBSD 3.0, 3.4, 4.0, 4.2, 4.3, 4.4, 4.5, 4.8, 4.9 and 5-CURRENT. !

!

The version of binutils installed in /usr/bin probably works with this release of GCC. Bootstrapping against the latest GNU ! binutils and/or the version found in /usr/ports/devel/binutils has been known to enable additional features and improve overall testsuite results. However, it is currently known that boehm-gc (which itself is required for java) may not configure properly on FreeBSD prior to the FreeBSD 7.0 release with GNU binutils after 2.16.1. !

!
!

h8300-hms

Renesas H8/300 series of processors. !

!

Please have a look at the binaries page. !

!

The calling convention and structure layout has changed in release 2.6. All code must be recompiled. The calling convention now passes the first three arguments in function calls in registers. Structures are no longer a multiple of 2 bytes. !

!
!

hppa*-hp-hpux*

Support for HP-UX version 9 and older was discontinued in GCC 3.4. !

!

We require using gas/binutils on all hppa platforms. Version 2.19 or later is recommended. !

!

It may be helpful to configure GCC with the ! --with-gnu-as and ! --with-as=… options to ensure that GCC can find GAS. !

!

The HP assembler should not be used with GCC. It is rarely tested and may ! not work. It shouldn’t be used with any languages other than C due to its many limitations. !

!

Specifically, -g does not work (HP-UX uses a peculiar debugging format which GCC does not know about). It also inserts timestamps into each object file it creates, causing the 3-stage comparison test to fail during a bootstrap. You should be able to continue by saying ! ‘make all-host all-target’ after getting the failure from ‘make’. !

!

Various GCC features are not supported. For example, it does not support weak symbols or alias definitions. As a result, explicit template instantiations are required when using C++. This makes it difficult if not impossible to build many C++ applications. !

!

There are two default scheduling models for instructions. These are PROCESSOR_7100LC and PROCESSOR_8000. They are selected from the pa-risc ! architecture specified for the target machine when configuring. PROCESSOR_8000 is the default. PROCESSOR_7100LC is selected when ! the target is a ‘hppa1*’ machine. !

!

The PROCESSOR_8000 model is not well suited to older processors. Thus, it is important to completely specify the machine architecture when configuring if you want a model other than PROCESSOR_8000. The macro TARGET_SCHED_DEFAULT can be defined in BOOT_CFLAGS if a different default scheduling model is desired. !

!

As of GCC 4.0, GCC uses the UNIX 95 namespace for HP-UX 10.10 ! through 11.00, and the UNIX 98 namespace for HP-UX 11.11 and later. This namespace change might cause problems when bootstrapping with an earlier version of GCC or the HP compiler as essentially the same namespace is required for an entire build. This problem can be avoided ! in a number of ways. With HP cc, UNIX_STD can be set to ‘95’ ! or ‘98’. Another way is to add an appropriate set of predefines ! to CC. The description for the munix= option contains a list of the predefines used with each standard. !

!

More specific information to ‘hppa*-hp-hpux*’ targets follows. !

!
!

hppa*-hp-hpux10

For hpux10.20, we highly recommend you pick up the latest sed patch PHCO_19798 from HP. !

!

The C++ ABI has changed incompatibly in GCC 4.0. COMDAT subspaces are used for one-only code and data. This resolves many of the previous problems in using C++ on this target. However, the ABI is not compatible with the one implemented under HP-UX 11 using secondary definitions. !

!
!

hppa*-hp-hpux11

GCC 3.0 and up support HP-UX 11. GCC 2.95.x is not supported and cannot be used to compile GCC 3.0 and up. !

!

The libffi and libjava libraries haven’t been ported to 64-bit HP-UX and don’t build. !

!

Refer to binaries for information about obtaining precompiled GCC binaries for HP-UX. Precompiled binaries must be obtained ! to build the Ada language as it can’t be bootstrapped using C. Ada is only available for the 32-bit PA-RISC runtime. !

!

Starting with GCC 3.4 an ISO C compiler is required to bootstrap. The ! bundled compiler supports only traditional C; you will need either HP’s unbundled compiler, or a binary distribution of GCC. !

!

It is possible to build GCC 3.3 starting with the bundled HP compiler, but the process requires several steps. GCC 3.3 can then be used to build later versions. The fastjar program contains ISO C code and ! can’t be built with the HP bundled compiler. This problem can be avoided by not building the Java language. For example, use the ! --enable-languages="c,c++,f77,objc" option in your configure command. !

!

There are several possible approaches to building the distribution. Binutils can be built first using the HP tools. Then, the GCC distribution can be built. The second approach is to build GCC ! first using the HP tools, then build binutils, then rebuild GCC. There have been problems with various binary distributions, so it is best not to start from a binary distribution. !

!

On 64-bit capable systems, there are two distinct targets. Different installation prefixes must be used if both are to be installed on ! the same system. The ‘hppa[1-2]*-hp-hpux11*’ target generates code ! for the 32-bit PA-RISC runtime architecture and uses the HP linker. ! The ‘hppa64-hp-hpux11*’ target generates 64-bit code for the PA-RISC 2.0 architecture. !

!

The script config.guess now selects the target type based on the compiler ! detected during configuration. You must define PATH or CC so ! that configure finds an appropriate compiler for the initial bootstrap. ! When CC is used, the definition should contain the options that are ! needed whenever CC is used. !

!

Specifically, options that determine the runtime architecture must be ! in CC to correctly select the target for the build. It is also ! convenient to place many other compiler options in CC. For example, ! CC="cc -Ac +DA2.0W -Wp,-H16376 -D_CLASSIC_TYPES -D_HPUX_SOURCE" can be used to bootstrap the GCC 3.3 branch with the HP compiler in ! 64-bit K&R/bundled mode. The +DA2.0W option will result in ! the automatic selection of the ‘hppa64-hp-hpux11*’ target. The macro definition table of cpp needs to be increased for a successful build with the HP compiler. _CLASSIC_TYPES and _HPUX_SOURCE need to be defined when building with the bundled compiler, or when using the ! -Ac option. These defines aren’t necessary with -Ae. !

!

It is best to explicitly configure the ‘hppa64-hp-hpux11*’ target ! with the --with-ld=… option. This overrides the standard search for ld. The two linkers supported on this target require different commands. The default linker is determined during configuration. As a ! result, it’s not possible to switch linkers in the middle of a GCC build. This has been reported to sometimes occur in unified builds of binutils and GCC. !

!

A recent linker patch must be installed for the correct operation of GCC 3.3 and later. PHSS_26559 and PHSS_24304 are the oldest linker patches that are known to work. They are for HP-UX 11.00 and 11.11, respectively. PHSS_24303, the companion to ! PHSS_24304, might be usable but it hasn’t been tested. These patches have been superseded. Consult the HP patch database to obtain the currently recommended linker patch for your system. !

!

The patches are necessary for the support of weak symbols on the 32-bit port, and for the running of initializers and finalizers. Weak symbols are implemented using SOM secondary definition symbols. Prior ! to HP-UX 11, there are bugs in the linker support for secondary symbols. The patches correct a problem of linker core dumps creating shared libraries containing secondary symbols, as well as various other linking issues involving secondary symbols. !

!

GCC 3.3 uses the ELF DT_INIT_ARRAY and DT_FINI_ARRAY capabilities to run initializers and finalizers on the 64-bit port. The 32-bit port ! uses the linker +init and +fini options for the same purpose. The patches correct various problems with the +init/+fini options, including program core dumps. Binutils 2.14 corrects a ! problem on the 64-bit port resulting from HP’s non-standard use of the .init and .fini sections for array initializers and finalizers. !

!

Although the HP and GNU linkers are both supported for the ! ‘hppa64-hp-hpux11*’ target, it is strongly recommended that the HP linker be used for link editing on this target. !

!

At this time, the GNU linker does not support the creation of long ! branch stubs. As a result, it can’t successfully link binaries containing branch offsets larger than 8 megabytes. In addition, there are problems linking shared libraries, linking executables ! with -static, and with dwarf2 unwind and exception support. ! It also doesn’t provide stubs for internal calls to global functions ! in shared libraries, so these calls can’t be overloaded. !

!

The HP dynamic loader does not support GNU symbol versioning, so symbol versioning is not supported. It may be necessary to disable symbol ! versioning with --disable-symvers when using GNU ld. !

!

POSIX threads are the default. The optional DCE thread library is not ! supported, so --enable-threads=dce does not work. !

!
!

*-*-linux-gnu

Versions of libstdc++-v3 starting with 3.2.1 require bug fixes present in glibc 2.2.5 and later. More information is available in the libstdc++-v3 documentation. -

-
-

i?86-*-linux*

!

As of GCC 3.3, binutils 2.13.1 or later is required for this platform. See bug 10877 for more information. !

!

If you receive Signal 11 errors when building on GNU/Linux, then it is possible you have a hardware problem. Further information on this can be found on www.bitwizard.nl. !

!
!

i?86-*-solaris2.9

!

The Sun assembler in Solaris 9 has several bugs and limitations. While GCC works around them, several features are missing, so it is recommended to use the GNU assembler instead. There is no bundled version, but the current version, from GNU binutils 2.22, is known to work. !

!

Solaris 2/x86 doesn’t support the execution of SSE/SSE2 instructions before Solaris 9 4/04, even if the CPU supports them. Programs will receive SIGILL if they try. The fix is available both in Solaris 9 Update 6 and kernel patch 112234-12 or newer. To avoid this problem, ! -march defaults to ‘pentiumpro’ on Solaris 9. If you have the patch installed, you can configure GCC with an appropriate ! --with-arch option, but need GNU as for SSE2 support. !

!
!

i?86-*-solaris2.10

Use this for Solaris 10 or later on x86 and x86-64 systems. Starting ! with GCC 4.7, there is also a 64-bit ‘amd64-*-solaris2.1[0-9]*’ or ! ‘x86_64-*-solaris2.1[0-9]*’ configuration that corresponds to ! ‘sparcv9-sun-solaris2*’. !

!

It is recommended that you configure GCC to use the GNU assembler, in ! /usr/sfw/bin/gas. The versions included in Solaris 10, from GNU binutils 2.15, and Solaris 11, from GNU binutils 2.19, work fine, although the current version, from GNU binutils 2.22, is known to work, too. Recent versions of the Sun assembler in ! /usr/ccs/bin/as work almost as well, though. !

!

For linking, the Sun linker, is preferred. If you want to use the GNU ! linker instead, which is available in /usr/sfw/bin/gld, note that due to a packaging bug the version in Solaris 10, from GNU binutils 2.15, cannot be used, while the version in Solaris 11, from GNU binutils 2.19, works, as does the latest version, from GNU binutils 2.22. !

!

To use GNU as, configure with the options ! --with-gnu-as --with-as=/usr/sfw/bin/gas. It may be necessary ! to configure with --without-gnu-ld --with-ld=/usr/ccs/bin/ld to ! guarantee use of Sun ld. !

!
!

ia64-*-linux

IA-64 processor (also known as IPF, or Itanium Processor Family) running GNU/Linux. !

!

If you are using the installed system libunwind library with ! --with-system-libunwind, then you must use libunwind 0.98 or later. !

!

None of the following versions of GCC has an ABI that is compatible with any of the other versions in this list, with the exception that Red Hat 2.96 and Trillian 000171 are compatible with each other: ! 3.1, 3.0.2, 3.0.1, 3.0, Red Hat 2.96, and Trillian 000717. ! This primarily affects C++ programs and programs that create shared libraries. ! GCC 3.1 or later is recommended for compiling linux, the kernel. As of version 3.1 GCC is believed to be fully ABI compliant, and hence no more major ABI changes are expected. !

!
!

ia64-*-hpux*

Building GCC on this target requires the GNU Assembler. The bundled HP assembler will not work. To prevent GCC from using the wrong assembler, ! the option --with-gnu-as may be necessary. !

!

The GCC libunwind library has not been ported to HPUX. This means that for ! GCC versions 3.2.3 and earlier, --enable-libunwind-exceptions ! is required to build GCC. For GCC 3.3 and later, this is the default. ! For gcc 3.4.3 and later, --enable-libunwind-exceptions is removed and the system libunwind library will always be used. !

!
! !

*-ibm-aix*

!

Support for AIX version 3 and older was discontinued in GCC 3.4. Support for AIX version 4.2 and older was discontinued in GCC 4.5. !

!

“out of memory” bootstrap failures may indicate a problem with process resource limits (ulimit). Hard limits are configured in the ! /etc/security/limits system configuration file. !

!

GCC can bootstrap with recent versions of IBM XLC, but bootstrapping with an earlier release of GCC is recommended. Bootstrapping with XLC requires a larger data segment, which can be enabled through the LDR_CNTRL environment variable, e.g., -

-
- 
% LDR_CNTRL=MAXDATA=0x50000000
- % export LDR_CNTRL
-
!

One can start with a pre-compiled version of GCC to build from ! sources. One may delete GCC’s “fixed” header files when starting with a version of GCC built for an earlier release of AIX. -

-

To speed up the configuration phases of bootstrapping and installing GCC, - one may use GNU Bash instead of AIX /bin/sh, e.g., -

-
- 
% CONFIG_SHELL=/opt/freeware/bin/bash
- % export CONFIG_SHELL
-
!

and then proceed as described in the build ! instructions, where we strongly recommend specifying an absolute path to invoke srcdir/configure. !

!

Because GCC on AIX is built as a 32-bit executable by default, (although it can generate 64-bit programs) the GMP and MPFR libraries required by gfortran must be 32-bit libraries. Building GMP and MPFR as static archive libraries works better than shared libraries. !

!

Errors involving alloca when building GCC generally are due to an incorrect definition of CC in the Makefile or mixing files compiled with the native C compiler and GCC. During the stage1 phase of ! the build, the native AIX compiler must be invoked as cc ! (not xlc). Once configure has been informed of ! xlc, one needs to use ‘make distclean’ to remove the ! configure cache files and ensure that CC environment variable ! does not provide a definition that will confuse configure. If this error occurs during stage2 or later, then the problem most likely is the version of Make (see above). !

!

The native as and ld are recommended for bootstrapping on AIX. The GNU Assembler, GNU Linker, and GNU Binutils version 2.20 is the minimum level that supports bootstrap on ! AIX 5. The GNU Assembler has not been updated to support AIX 6 or AIX 7. The native AIX tools do interoperate with GCC. !

!

AIX 5.3 TL10, AIX 6.1 TL05 and AIX 7.1 TL00 introduced an AIX assembler change that sometimes produces corrupt assembly files causing AIX linker errors. The bug breaks GCC bootstrap on AIX and can cause compilation failures with existing GCC installations. An --- 1,645 ---- ! ! ! Host/Target specific installation notes for GCC ! ! ! ! ! ! ! ! ! !

Host/Target specific installation notes for GCC

! ! Please read this document carefully before installing the GNU Compiler Collection on your machine. ! !

Note that this list of install notes is not a list of supported hosts or targets. Not all supported hosts and targets are listed here, only the ones that require host-specific or target-specific ! information have to. !

+ !

!

! !

alpha*-*-*

This section contains general configuration information for all alpha-based platforms using ELF (in particular, ignore this section for DEC OSF/1, Digital UNIX and Tru64 UNIX). In addition to reading this section, please read all other sections that match your target. ! !

We require binutils 2.11.2 or newer. Previous binutils releases had a number of problems with DWARF 2 debugging information, not the least of which is incorrect linking of shared libraries. ! !

! !

alpha*-dec-osf5.1

!

Systems using processors that implement the DEC Alpha architecture and are running the DEC/Compaq/HP Unix (DEC OSF/1, Digital UNIX, or Compaq/HP Tru64 UNIX) operating system, for example the DEC Alpha AXP systems. ! !

Support for Tru64 UNIX V5.1 has been removed in GCC 4.8. As of GCC 4.6, support for Tru64 UNIX V4.0 and V5.0 has been removed. As of GCC 3.2, versions before alpha*-dec-osf4 are no longer supported. (These are the versions which identify themselves as DEC OSF/1.) !

! !

amd64-*-solaris2.1[0-9]*

! !

This is a synonym for ‘x86_64-*-solaris2.1[0-9]*’. ! !

! !

arm-*-eabi

!

ARM-family processors. Subtargets that use the ELF object format require GNU binutils 2.13 or newer. Such subtargets include: arm-*-netbsdelf, arm-*-*linux-* and arm-*-rtemseabi. ! !

! !

avr

ATMEL AVR-family micro controllers. These are used in embedded ! applications. There are no standard Unix configurations. See “AVR Options” in the main manual for the list of supported MCU types. ! !

Use ‘configure --target=avr --enable-languages="c"’ to configure GCC. ! !

Further installation notes and other useful information about AVR tools can also be obtained from: !

!

We strongly recommend using binutils 2.13 or newer. !

The following error: ! 

     Error: register required
!
!

indicates that you should upgrade to a newer version of the binutils. ! !

! !

Blackfin

! !

The Blackfin processor, an Analog Devices DSP. See “Blackfin Options” in the main manual ! !

More information, and a version of binutils with support for this processor, is available at http://blackfin.uclinux.org !

! !

CR16

! !

The CR16 CompactRISC architecture is a 16-bit architecture. This architecture is used in embedded applications. !

See “CR16 Options” in the main manual for a list of CR16-specific options. ! !

Use ‘configure --target=cr16-elf --enable-languages=c,c++’ to configure ! GCC for building a CR16 elf cross-compiler. ! !

Use ‘configure --target=cr16-uclinux --enable-languages=c,c++’ to configure ! GCC for building a CR16 uclinux cross-compiler. ! !

! !

CRIS

CRIS is the CPU architecture in Axis Communications ETRAX system-on-a-chip series. These are used in embedded applications. ! !

See “CRIS Options” in the main manual for a list of CRIS-specific options. ! !

There are a few different CRIS targets: !

!
cris-axis-elf
Mainly for monolithic embedded systems. Includes a multilib for the ! ‘v10’ core used in ‘ETRAX 100 LX’. !
cris-axis-linux-gnu
A GNU/Linux port for the CRIS architecture, currently targeting ! ‘ETRAX 100 LX’ by default.
!

For cris-axis-elf you need binutils 2.11 or newer. For cris-axis-linux-gnu you need binutils 2.12 or newer. ! !

Pre-packaged tools can be obtained from ftp://ftp.axis.com/pub/axis/tools/cris/compiler-kit/. More information about this platform is available at http://developer.axis.com/. ! !

! !

DOS

Please have a look at the binaries page. ! !

You cannot install GCC by itself on MSDOS; it will not compile under any MSDOS compiler except itself. You need to get the complete compilation package DJGPP, which includes binaries as well as sources, and includes all the necessary compilation tools and libraries. ! !

! !

epiphany-*-elf

! !

Adapteva Epiphany. This configuration is intended for embedded systems. ! !

! !

*-*-freebsd*

Support for FreeBSD 1 was discontinued in GCC 3.2. Support for FreeBSD 2 (and any mutant a.out variants of FreeBSD 3) was discontinued in GCC 4.0. ! !

In order to better utilize FreeBSD base system functionality and match the configuration of the system compiler, GCC 4.5 and above as well as GCC 4.4 past 2010-06-20 leverage SSP support in libc (which is present on FreeBSD 7 or later) and the use of __cxa_atexit by default (on FreeBSD 6 or later). The use of dl_iterate_phdr inside ! libgcc_s.so.1 and boehm-gc (on FreeBSD 7 or later) is enabled by GCC 4.5 and above. ! !

We support FreeBSD using the ELF file format with DWARF 2 debugging ! for all CPU architectures. You may use -gstabs instead of ! -g, if you really want the old debugging format. There are no known issues with mixing object files and libraries with different debugging formats. Otherwise, this release of GCC should now match more of the configuration used in the stock FreeBSD configuration of ! GCC. In particular, --enable-threads is now configured by default. However, as a general user, do not attempt to replace the system compiler with this release. Known to bootstrap and check with good results on FreeBSD 7.2-STABLE. In the past, known to bootstrap and check with good results on FreeBSD 3.0, 3.4, 4.0, 4.2, 4.3, 4.4, 4.5, 4.8, 4.9 and 5-CURRENT. ! !

The version of binutils installed in /usr/bin probably works with this release of GCC. Bootstrapping against the latest GNU ! binutils and/or the version found in /usr/ports/devel/binutils has been known to enable additional features and improve overall testsuite results. However, it is currently known that boehm-gc (which itself is required for java) may not configure properly on FreeBSD prior to the FreeBSD 7.0 release with GNU binutils after 2.16.1. ! !

! !

h8300-hms

!

Renesas H8/300 series of processors. ! !

Please have a look at the binaries page. ! !

The calling convention and structure layout has changed in release 2.6. All code must be recompiled. The calling convention now passes the first three arguments in function calls in registers. Structures are no longer a multiple of 2 bytes. ! !

! !

hppa*-hp-hpux*

!

Support for HP-UX version 9 and older was discontinued in GCC 3.4. ! !

We require using gas/binutils on all hppa platforms. Version 2.19 or later is recommended. ! !

It may be helpful to configure GCC with the ! --with-gnu-as and ! --with-as=... options to ensure that GCC can find GAS. ! !

The HP assembler should not be used with GCC. It is rarely tested and may ! not work. It shouldn't be used with any languages other than C due to its many limitations. ! !

Specifically, -g does not work (HP-UX uses a peculiar debugging format which GCC does not know about). It also inserts timestamps into each object file it creates, causing the 3-stage comparison test to fail during a bootstrap. You should be able to continue by saying ! ‘make all-host all-target’ after getting the failure from ‘make’. ! !

Various GCC features are not supported. For example, it does not support weak symbols or alias definitions. As a result, explicit template instantiations are required when using C++. This makes it difficult if not impossible to build many C++ applications. ! !

There are two default scheduling models for instructions. These are PROCESSOR_7100LC and PROCESSOR_8000. They are selected from the pa-risc ! architecture specified for the target machine when configuring. PROCESSOR_8000 is the default. PROCESSOR_7100LC is selected when ! the target is a ‘hppa1*’ machine. ! !

The PROCESSOR_8000 model is not well suited to older processors. Thus, it is important to completely specify the machine architecture when configuring if you want a model other than PROCESSOR_8000. The macro TARGET_SCHED_DEFAULT can be defined in BOOT_CFLAGS if a different default scheduling model is desired. ! !

As of GCC 4.0, GCC uses the UNIX 95 namespace for HP-UX 10.10 ! through 11.00, and the UNIX 98 namespace for HP-UX 11.11 and later. This namespace change might cause problems when bootstrapping with an earlier version of GCC or the HP compiler as essentially the same namespace is required for an entire build. This problem can be avoided ! in a number of ways. With HP cc, UNIX_STD can be set to ‘95’ ! or ‘98’. Another way is to add an appropriate set of predefines ! to CC. The description for the munix= option contains a list of the predefines used with each standard. ! !

More specific information to ‘hppa*-hp-hpux*’ targets follows. ! !

! !

hppa*-hp-hpux10

For hpux10.20, we highly recommend you pick up the latest sed patch PHCO_19798 from HP. ! !

The C++ ABI has changed incompatibly in GCC 4.0. COMDAT subspaces are used for one-only code and data. This resolves many of the previous problems in using C++ on this target. However, the ABI is not compatible with the one implemented under HP-UX 11 using secondary definitions. ! !

! !

hppa*-hp-hpux11

GCC 3.0 and up support HP-UX 11. GCC 2.95.x is not supported and cannot be used to compile GCC 3.0 and up. ! !

The libffi and libjava libraries haven't been ported to 64-bit HP-UX and don't build. ! !

Refer to binaries for information about obtaining precompiled GCC binaries for HP-UX. Precompiled binaries must be obtained ! to build the Ada language as it can't be bootstrapped using C. Ada is only available for the 32-bit PA-RISC runtime. ! !

Starting with GCC 3.4 an ISO C compiler is required to bootstrap. The ! bundled compiler supports only traditional C; you will need either HP's unbundled compiler, or a binary distribution of GCC. ! !

It is possible to build GCC 3.3 starting with the bundled HP compiler, but the process requires several steps. GCC 3.3 can then be used to build later versions. The fastjar program contains ISO C code and ! can't be built with the HP bundled compiler. This problem can be avoided by not building the Java language. For example, use the ! --enable-languages="c,c++,f77,objc" option in your configure command. ! !

There are several possible approaches to building the distribution. Binutils can be built first using the HP tools. Then, the GCC distribution can be built. The second approach is to build GCC ! first using the HP tools, then build binutils, then rebuild GCC. There have been problems with various binary distributions, so it is best not to start from a binary distribution. ! !

On 64-bit capable systems, there are two distinct targets. Different installation prefixes must be used if both are to be installed on ! the same system. The ‘hppa[1-2]*-hp-hpux11*’ target generates code ! for the 32-bit PA-RISC runtime architecture and uses the HP linker. ! The ‘hppa64-hp-hpux11*’ target generates 64-bit code for the PA-RISC 2.0 architecture. ! !

The script config.guess now selects the target type based on the compiler ! detected during configuration. You must define PATH or CC so ! that configure finds an appropriate compiler for the initial bootstrap. ! When CC is used, the definition should contain the options that are ! needed whenever CC is used. ! !

Specifically, options that determine the runtime architecture must be ! in CC to correctly select the target for the build. It is also ! convenient to place many other compiler options in CC. For example, ! CC="cc -Ac +DA2.0W -Wp,-H16376 -D_CLASSIC_TYPES -D_HPUX_SOURCE" can be used to bootstrap the GCC 3.3 branch with the HP compiler in ! 64-bit K&R/bundled mode. The +DA2.0W option will result in ! the automatic selection of the ‘hppa64-hp-hpux11*’ target. The macro definition table of cpp needs to be increased for a successful build with the HP compiler. _CLASSIC_TYPES and _HPUX_SOURCE need to be defined when building with the bundled compiler, or when using the ! -Ac option. These defines aren't necessary with -Ae. ! !

It is best to explicitly configure the ‘hppa64-hp-hpux11*’ target ! with the --with-ld=... option. This overrides the standard search for ld. The two linkers supported on this target require different commands. The default linker is determined during configuration. As a ! result, it's not possible to switch linkers in the middle of a GCC build. This has been reported to sometimes occur in unified builds of binutils and GCC. ! !

A recent linker patch must be installed for the correct operation of GCC 3.3 and later. PHSS_26559 and PHSS_24304 are the oldest linker patches that are known to work. They are for HP-UX 11.00 and 11.11, respectively. PHSS_24303, the companion to ! PHSS_24304, might be usable but it hasn't been tested. These patches have been superseded. Consult the HP patch database to obtain the currently recommended linker patch for your system. ! !

The patches are necessary for the support of weak symbols on the 32-bit port, and for the running of initializers and finalizers. Weak symbols are implemented using SOM secondary definition symbols. Prior ! to HP-UX 11, there are bugs in the linker support for secondary symbols. The patches correct a problem of linker core dumps creating shared libraries containing secondary symbols, as well as various other linking issues involving secondary symbols. ! !

GCC 3.3 uses the ELF DT_INIT_ARRAY and DT_FINI_ARRAY capabilities to run initializers and finalizers on the 64-bit port. The 32-bit port ! uses the linker +init and +fini options for the same purpose. The patches correct various problems with the +init/+fini options, including program core dumps. Binutils 2.14 corrects a ! problem on the 64-bit port resulting from HP's non-standard use of the .init and .fini sections for array initializers and finalizers. ! !

Although the HP and GNU linkers are both supported for the ! ‘hppa64-hp-hpux11*’ target, it is strongly recommended that the HP linker be used for link editing on this target. ! !

At this time, the GNU linker does not support the creation of long ! branch stubs. As a result, it can't successfully link binaries containing branch offsets larger than 8 megabytes. In addition, there are problems linking shared libraries, linking executables ! with -static, and with dwarf2 unwind and exception support. ! It also doesn't provide stubs for internal calls to global functions ! in shared libraries, so these calls can't be overloaded. ! !

The HP dynamic loader does not support GNU symbol versioning, so symbol versioning is not supported. It may be necessary to disable symbol ! versioning with --disable-symvers when using GNU ld. ! !

POSIX threads are the default. The optional DCE thread library is not ! supported, so --enable-threads=dce does not work. ! !

! !

*-*-linux-gnu

Versions of libstdc++-v3 starting with 3.2.1 require bug fixes present in glibc 2.2.5 and later. More information is available in the libstdc++-v3 documentation. !

! !

i?86-*-linux*

! !

As of GCC 3.3, binutils 2.13.1 or later is required for this platform. See bug 10877 for more information. ! !

If you receive Signal 11 errors when building on GNU/Linux, then it is possible you have a hardware problem. Further information on this can be found on www.bitwizard.nl. ! !

! !

i?86-*-solaris2.9

! !

The Sun assembler in Solaris 9 has several bugs and limitations. While GCC works around them, several features are missing, so it is + recommended to use the GNU assembler instead. There is no bundled version, but the current version, from GNU binutils 2.22, is known to work. ! !

Solaris 2/x86 doesn't support the execution of SSE/SSE2 instructions before Solaris 9 4/04, even if the CPU supports them. Programs will receive SIGILL if they try. The fix is available both in Solaris 9 Update 6 and kernel patch 112234-12 or newer. To avoid this problem, ! -march defaults to ‘pentiumpro’ on Solaris 9. If you have the patch installed, you can configure GCC with an appropriate ! --with-arch option, but need GNU as for SSE2 support. ! !

! !

i?86-*-solaris2.10

!

Use this for Solaris 10 or later on x86 and x86-64 systems. Starting ! with GCC 4.7, there is also a 64-bit ‘amd64-*-solaris2.1[0-9]*’ or ! ‘x86_64-*-solaris2.1[0-9]*’ configuration that corresponds to ! ‘sparcv9-sun-solaris2*’. ! !

It is recommended that you configure GCC to use the GNU assembler, in ! /usr/sfw/bin/gas. The versions included in Solaris 10, from GNU binutils 2.15, and Solaris 11, from GNU binutils 2.19, work fine, although the current version, from GNU binutils 2.22, is known to work, too. Recent versions of the Sun assembler in ! /usr/ccs/bin/as work almost as well, though. ! ! !

For linking, the Sun linker, is preferred. If you want to use the GNU ! linker instead, which is available in /usr/sfw/bin/gld, note that due to a packaging bug the version in Solaris 10, from GNU binutils 2.15, cannot be used, while the version in Solaris 11, from GNU binutils 2.19, works, as does the latest version, from GNU binutils 2.22. ! !

To use GNU as, configure with the options ! --with-gnu-as --with-as=/usr/sfw/bin/gas. It may be necessary ! to configure with --without-gnu-ld --with-ld=/usr/ccs/bin/ld to ! guarantee use of Sun ld. ! ! !

! !

ia64-*-linux

!

IA-64 processor (also known as IPF, or Itanium Processor Family) running GNU/Linux. ! !

If you are using the installed system libunwind library with ! --with-system-libunwind, then you must use libunwind 0.98 or later. ! !

None of the following versions of GCC has an ABI that is compatible with any of the other versions in this list, with the exception that Red Hat 2.96 and Trillian 000171 are compatible with each other: ! 3.1, 3.0.2, 3.0.1, 3.0, Red Hat 2.96, and Trillian 000717. ! This primarily affects C++ programs and programs that create shared libraries. ! GCC 3.1 or later is recommended for compiling linux, the kernel. As of version 3.1 GCC is believed to be fully ABI compliant, and hence no more major ABI changes are expected. ! !

! !

ia64-*-hpux*

!

Building GCC on this target requires the GNU Assembler. The bundled HP assembler will not work. To prevent GCC from using the wrong assembler, ! the option --with-gnu-as may be necessary. ! !

The GCC libunwind library has not been ported to HPUX. This means that for ! GCC versions 3.2.3 and earlier, --enable-libunwind-exceptions ! is required to build GCC. For GCC 3.3 and later, this is the default. ! For gcc 3.4.3 and later, --enable-libunwind-exceptions is removed and the system libunwind library will always be used. ! !

! ! !

*-ibm-aix*

! !

Support for AIX version 3 and older was discontinued in GCC 3.4. Support for AIX version 4.2 and older was discontinued in GCC 4.5. ! !

“out of memory” bootstrap failures may indicate a problem with process resource limits (ulimit). Hard limits are configured in the ! /etc/security/limits system configuration file. ! !

GCC can bootstrap with recent versions of IBM XLC, but bootstrapping with an earlier release of GCC is recommended. Bootstrapping with XLC requires a larger data segment, which can be enabled through the LDR_CNTRL environment variable, e.g., ! 

     % LDR_CNTRL=MAXDATA=0x50000000
!      % export LDR_CNTRL
!
!

One can start with a pre-compiled version of GCC to build from ! sources. One may delete GCC's “fixed” header files when starting with a version of GCC built for an earlier release of AIX. !

To speed up the configuration phases of bootstrapping and installing GCC, ! one may use GNU Bash instead of AIX /bin/sh, e.g., ! ! 

     % CONFIG_SHELL=/opt/freeware/bin/bash
!      % export CONFIG_SHELL
!
!

and then proceed as described in the build instructions, where we strongly recommend specifying an absolute path to invoke srcdir/configure. ! !

Because GCC on AIX is built as a 32-bit executable by default, (although it can generate 64-bit programs) the GMP and MPFR libraries required by gfortran must be 32-bit libraries. Building GMP and MPFR as static archive libraries works better than shared libraries. ! !

Errors involving alloca when building GCC generally are due to an incorrect definition of CC in the Makefile or mixing files compiled with the native C compiler and GCC. During the stage1 phase of ! the build, the native AIX compiler must be invoked as cc ! (not xlc). Once configure has been informed of ! xlc, one needs to use ‘make distclean’ to remove the ! configure cache files and ensure that CC environment variable ! does not provide a definition that will confuse configure. If this error occurs during stage2 or later, then the problem most likely is the version of Make (see above). ! !

The native as and ld are recommended for bootstrapping on AIX. The GNU Assembler, GNU Linker, and GNU Binutils version 2.20 is the minimum level that supports bootstrap on ! AIX 5. The GNU Assembler has not been updated to support AIX 6 or AIX 7. The native AIX tools do interoperate with GCC. ! !

AIX 5.3 TL10, AIX 6.1 TL05 and AIX 7.1 TL00 introduced an AIX assembler change that sometimes produces corrupt assembly files causing AIX linker errors. The bug breaks GCC bootstrap on AIX and can cause compilation failures with existing GCC installations. An *************** AIX iFix for AIX 5.3 is available (APAR *** 677,1418 **** IZ98477 for AIX 5.3 TL11 and IZ98134 for AIX 5.3 TL12). AIX 5.3 TL11 SP8, AIX 5.3 TL12 SP5, AIX 6.1 TL04 SP11, AIX 6.1 TL05 SP7, AIX 6.1 TL06 SP6, AIX 6.1 TL07 and AIX 7.1 TL01 should include the fix. !

!

Building libstdc++.a requires a fix for an AIX Assembler bug APAR IY26685 (AIX 4.3) or APAR IY25528 (AIX 5.1). It also requires a fix for another AIX Assembler bug and a co-dependent AIX Archiver fix referenced as APAR IY53606 (AIX 5.2) or as APAR IY54774 (AIX 5.1) !

!

‘libstdc++’ in GCC 3.4 increments the major version number of the ! shared object and GCC installation places the libstdc++.a shared library in a common location which will overwrite the and GCC 3.3 version of the shared library. Applications either need to be re-linked against the new shared library or the GCC 3.1 and GCC 3.3 ! versions of the ‘libstdc++’ shared object needs to be available ! to the AIX runtime loader. The GCC 3.1 ‘libstdc++.so.4’, if ! present, and GCC 3.3 ‘libstdc++.so.5’ shared objects can be installed for runtime dynamic loading using the following steps to set ! the ‘F_LOADONLY’ flag in the shared object for each ! multilib libstdc++.a installed: !

!

Extract the shared objects from the currently installed ! libstdc++.a archive: !

! 
% ar -x libstdc++.a libstdc++.so.4 libstdc++.so.5
!
!

Enable the ‘F_LOADONLY’ flag so that the shared object will be available for runtime dynamic loading, but not linking: !

! 
% strip -e libstdc++.so.4 libstdc++.so.5
!
! !

Archive the runtime-only shared object in the GCC 3.4 ! libstdc++.a archive: !

! 
% ar -q libstdc++.a libstdc++.so.4 libstdc++.so.5
!
! !

Linking executables and shared libraries may produce warnings of duplicate symbols. The assembly files generated by GCC for AIX always have included multiple symbol definitions for certain global variable and function declarations in the original program. The warnings should not prevent the linker from producing a correct library or runnable executable. !

!

AIX 4.3 utilizes a “large format” archive to support both 32-bit and 64-bit object modules. The routines provided in AIX 4.3.0 and AIX 4.3.1 ! to parse archive libraries did not handle the new format correctly. These routines are used by GCC and result in error messages during linking such as “not a COFF file”. The version of the routines shipped ! with AIX 4.3.1 should work for a 32-bit environment. The -g option of the archive command may be used to create archives of 32-bit objects using the original “small format”. A correct version of the routines is shipped with AIX 4.3.2 and above. !

!

Some versions of the AIX binder (linker) can fail with a relocation ! overflow severe error when the -bbigtoc option is used to link GCC-produced object files into an executable that overflows the TOC. A fix for APAR IX75823 (OVERFLOW DURING LINK WHEN USING GCC AND -BBIGTOC) is available from IBM Customer Support and from its techsupport.services.ibm.com website as PTF U455193. !

!

The AIX 4.3.2.1 linker (bos.rte.bind_cmds Level 4.3.2.1) will dump core with a segmentation fault when invoked by any version of GCC. A fix for APAR IX87327 is available from IBM Customer Support and from its techsupport.services.ibm.com website as PTF U461879. This fix is incorporated in AIX 4.3.3 and above. !

!

The initial assembler shipped with AIX 4.3.0 generates incorrect object files. A fix for APAR IX74254 (64BIT DISASSEMBLED OUTPUT FROM COMPILER FAILS TO ASSEMBLE/BIND) is available from IBM Customer Support and from its techsupport.services.ibm.com website as PTF U453956. This fix is incorporated in AIX 4.3.1 and above. !

!

AIX provides National Language Support (NLS). Compilers and assemblers use NLS to support locale-specific representations of various data ! formats including floating-point numbers (e.g., ‘.’ vs ‘,’ for separating decimal fractions). There have been problems reported where GCC does not produce the same floating-point formats that the assembler ! expects. If one encounters this problem, set the LANG ! environment variable to ‘C’ or ‘En_US’. !

!

A default can be specified with the -mcpu=cpu_type ! switch and using the configure option --with-cpu-cpu_type. !

!
!

iq2000-*-elf

Vitesse IQ2000 processors. These are used in embedded applications. There are no standard Unix configurations. !

!
!

lm32-*-elf

!

Lattice Mico32 processor. This configuration is intended for embedded systems. !

!
!

lm32-*-uclinux

!

Lattice Mico32 processor. This configuration is intended for embedded systems running uClinux. !

!
!

m32c-*-elf

!

Renesas M32C processor. This configuration is intended for embedded systems. !

!
!

m32r-*-elf

!

Renesas M32R processor. This configuration is intended for embedded systems. !

!
!

m68k-*-*

By default, ! ‘m68k-*-elf*’, ‘m68k-*-rtems’, ‘m68k-*-uclinux’ and ! ‘m68k-*-linux’ build libraries for both M680x0 and ColdFire processors. If you only need the M680x0 libraries, you can omit the ColdFire ones by passing ! --with-arch=m68k to configure. Alternatively, you ! can omit the M680x0 libraries by passing --with-arch=cf to ! configure. These targets default to 5206 or 5475 code as appropriate for the target system when ! configured with --with-arch=cf and 68020 code otherwise. !

!

The ‘m68k-*-netbsd’ and ! ‘m68k-*-openbsd’ targets also support the --with-arch option. They will generate ColdFire CFV4e code when configured with ! --with-arch=cf and 68020 code otherwise. !

!

You can override the default processors listed above by configuring ! with --with-cpu=target. This target can either ! be a -mcpu argument or one of the following values: ! ‘m68000’, ‘m68010’, ‘m68020’, ‘m68030’, ! ‘m68040’, ‘m68060’, ‘m68020-40’ and ‘m68020-60’. !

!

GCC requires at least binutils version 2.17 on these targets. !

!
!

m68k-*-uclinux

GCC 4.3 changed the uClinux configuration so that it uses the ! ‘m68k-linux-gnu’ ABI rather than the ‘m68k-elf’ ABI. It also added improved support for C++ and flat shared libraries, both of which were ABI changes. -

!
!

mep-*-elf

!

Toshiba Media embedded Processor. This configuration is intended for embedded systems. !

!
!

microblaze-*-elf

!

Xilinx MicroBlaze processor. This configuration is intended for embedded systems. !

!
!

mips-*-*

If on a MIPS system you get an error message saying “does not have gp ! sections for all it’s [sic] sectons [sic]”, don’t worry about it. This happens whenever you use GAS with the MIPS linker, but there is not really anything wrong, and it is okay to use the output file. You can stop such warnings by installing the GNU linker. !

!

It would be nice to extend GAS to produce the gp tables, but they are optional, and there should not be a warning about their absence. !

!

The libstdc++ atomic locking routines for MIPS targets requires MIPS II and later. A patch went in just after the GCC 3.3 release to ! make ‘mips*-*-*’ use the generic implementation instead. You can also ! configure for ‘mipsel-elf’ as a workaround. The ! ‘mips*-*-linux*’ target continues to use the MIPS II routines. More work on this is expected in future releases. -

!

The built-in __sync_* functions are available on MIPS II and ! later systems and others that support the ‘ll’, ‘sc’ and ! ‘sync’ instructions. This can be overridden by passing ! --with-llsc or --without-llsc when configuring GCC. Since the Linux kernel emulates these instructions if they are ! missing, the default for ‘mips*-*-linux*’ targets is ! --with-llsc. The --with-llsc and ! --without-llsc configure options may be overridden at compile ! time by passing the -mllsc or -mno-llsc options to the compiler. !

!

MIPS systems check for division by zero (unless ! -mno-check-zero-division is passed to the compiler) by generating either a conditional trap or a break instruction. Using trap results in smaller code, but is only supported on MIPS II and later. Also, some versions of the Linux kernel have a bug that prevents trap from generating the proper signal (SIGFPE). To enable ! the use of break, use the --with-divide=breaks ! configure option when configuring GCC. The default is to use traps on systems that support them. !

!

The assembler from GNU binutils 2.17 and earlier has a bug in the way it sorts relocations for REL targets (o32, o64, EABI). This can cause bad code to be generated for simple C++ programs. Also the linker from GNU binutils versions prior to 2.17 has a bug which causes the ! runtime linker stubs in very large programs, like libgcj.so, to be incorrectly generated. GNU Binutils 2.18 and later (and snapshots made after Nov. 9, 2006) should be free from both of these problems. !

!
!

mips-sgi-irix5

Support for IRIX 5 has been removed in GCC 4.6. !

!
!

mips-sgi-irix6

Support for IRIX 6.5 has been removed in GCC 4.8. Support for IRIX 6 releases before 6.5 has been removed in GCC 4.6, as well as support for the O32 ABI. !

!
!

moxie-*-elf

The moxie processor. -

-
-

powerpc-*-*

!

You can specify a default version for the -mcpu=cpu_type ! switch by using the configure option --with-cpu-cpu_type. !

!

You will need binutils 2.15 or newer for a working GCC. !

!
!

powerpc-*-darwin*

PowerPC running Darwin (Mac OS X kernel). !

!

Pre-installed versions of Mac OS X may not include any developer tools, meaning that you will not be able to build GCC from source. Tool binaries are available at http://opensource.apple.com/. !

!

This version of GCC requires at least cctools-590.36. The cctools-590.36 package referenced from http://gcc.gnu.org/ml/gcc/2006-03/msg00507.html will not work on systems older than 10.3.9 (aka darwin7.9.0). !

!
!

powerpc-*-elf

PowerPC system in big endian mode, running System V.4. !

!
!

powerpc*-*-linux-gnu*

PowerPC system in big endian mode running Linux. !

!
!

powerpc-*-netbsd*

PowerPC system in big endian mode running NetBSD. !

!
!

powerpc-*-eabisim

Embedded PowerPC system in big endian mode for use in running under the PSIM simulator. !

!
!

powerpc-*-eabi

Embedded PowerPC system in big endian mode. !

!
!

powerpcle-*-elf

PowerPC system in little endian mode, running System V.4. !

!
!

powerpcle-*-eabisim

Embedded PowerPC system in little endian mode for use in running under the PSIM simulator. !

!
!

powerpcle-*-eabi

Embedded PowerPC system in little endian mode. !

!
!

rl78-*-elf

!

The Renesas RL78 processor. This configuration is intended for embedded systems. !

!
!

rx-*-elf

The Renesas RX processor. See http://eu.renesas.com/fmwk.jsp?cnt=rx600_series_landing.jsp&fp=/products/mpumcu/rx_family/rx600_series for more information about this processor. !

!
!

s390-*-linux*

S/390 system running GNU/Linux for S/390. !

!
!

s390x-*-linux*

zSeries system (64-bit) running GNU/Linux for zSeries. !

!
!

s390x-ibm-tpf*

zSeries system (64-bit) running TPF. This platform is supported as cross-compilation target only. !

!
!

*-*-solaris2*

Support for Solaris 8 has removed in GCC 4.8. Support for Solaris 7 has been removed in GCC 4.6. !

!

Sun does not ship a C compiler with Solaris 2 before Solaris 10, though you can download the Sun Studio compilers for free. In Solaris 10 and ! 11, GCC 3.4.3 is available as /usr/sfw/bin/gcc. Solaris 11 ! also provides GCC 4.5.2 as /usr/gcc/4.5/bin/gcc. Alternatively, you can install a pre-built GCC to bootstrap and install GCC. See the binaries page for details. !

!

The Solaris 2 /bin/sh will often fail to configure ! ‘libstdc++-v3’, ‘boehm-gc’ or ‘libjava’. We therefore recommend using the following initial sequence of commands -

-
- 
% CONFIG_SHELL=/bin/ksh
- % export CONFIG_SHELL
-
!

and proceed as described in the configure instructions. In addition we strongly recommend specifying an absolute path to invoke ! srcdir/configure. !

!

Solaris 2 comes with a number of optional OS packages. Some of these are needed to use GCC fully, namely SUNWarc, SUNWbtool, SUNWesu, SUNWhea, SUNWlibm, SUNWsprot, and SUNWtoo. If you did not install all optional packages when installing Solaris 2, you will need to verify that the packages that GCC needs are installed. !

!

To check whether an optional package is installed, use ! the pkginfo command. To add an optional package, use the ! pkgadd command. For further details, see the Solaris 2 documentation. !

!

Trying to use the linker and other tools in ! /usr/ucb to install GCC has been observed to cause trouble. For example, the linker may hang indefinitely. The fix is to remove ! /usr/ucb from your PATH. !

!

The build process works more smoothly with the legacy Sun tools so, if you ! have /usr/xpg4/bin in your PATH, we recommend that you place ! /usr/bin before /usr/xpg4/bin for the duration of the build. !

!

We recommend the use of the Sun assembler or the GNU assembler, in ! conjunction with the Sun linker. The GNU as versions included in Solaris 10, from GNU binutils 2.15, and Solaris 11, from GNU binutils 2.19, are known to work. They can be found in ! /usr/sfw/bin/gas. Current versions of GNU binutils (2.22) are known to work as well. Note that your mileage may vary if you use a combination of the GNU tools and the Sun tools: while the ! combination GNU as + Sun ld should reasonably work, ! the reverse combination Sun as + GNU ld may fail to ! build or cause memory corruption at runtime in some cases for C++ programs. ! GNU ld usually works as well, although the version included in Solaris 10 cannot be used due to several bugs. Again, the current version (2.22) is known to work, but generally lacks platform specific ! features, so better stay with Sun ld. To use the LTO linker ! plugin (-fuse-linker-plugin) with GNU ld, GNU ! binutils must be configured with --enable-largefile. !

!

To enable symbol versioning in ‘libstdc++’ with Sun ld, ! you need to have any version of GNU c++filt, which is part of ! GNU binutils. ‘libstdc++’ symbol versioning will be disabled if no ! appropriate version is found. Sun c++filt from the Sun Studio compilers does not work. !

!

Sun bug 4296832 turns up when compiling X11 headers with GCC 2.95 or ! newer: g++ will complain that types are missing. These headers assume that omitting the type means int; this assumption worked for C90 but is wrong for C++, and is now wrong for C99 also. !

!

Sun bug 4927647 sometimes causes random spurious testsuite failures ! related to missing diagnostic output. This bug doesn’t affect GCC ! itself, rather it is a kernel bug triggered by the expect program which is used only by the GCC testsuite driver. When the bug ! causes the expect program to miss anticipated output, extra testsuite failures appear. !

!

There are patches for Solaris 9 (117171-11 or newer for SPARC, 117172-11 or newer for Intel) that address this problem. !

!

Thread-local storage (TLS) is supported in Solaris 9, but requires ! some patches. The ‘libthread’ patches provide the ! __tls_get_addr (SPARC, 64-bit x86) resp. ___tls_get_addr (32-bit x86) functions. On Solaris 9, the necessary support on SPARC is present since FCS, while 114432-05 or newer is required on Intel. Additionally, on Solaris 9/x86, patch 113986-02 or newer is ! required for the Sun ld and runtime linker (ld.so.1) support, while Solaris 9/SPARC works since FCS. The linker ! patches must be installed even if GNU ld is used. Sun ! as in Solaris 9 doesn’t support the necessary ! relocations, so GNU as must be used. The configure script checks for those prerequisites and automatically enables TLS support if they are met. Although those minimal patch versions should work, it is recommended to use the latest patch versions which include additional bug fixes. !

!
!

sparc*-*-*

This section contains general configuration information for all SPARC-based platforms. In addition to reading this section, please read all other sections that match your target. !

!

Newer versions of the GNU Multiple Precision Library (GMP), the MPFR library and the MPC library are known to be miscompiled by earlier versions of GCC on these platforms. We therefore recommend the use of the exact versions of these libraries listed as minimal versions in the prerequisites. !

!
!

sparc-sun-solaris2*

When GCC is configured to use GNU binutils 2.14 or later, the binaries ! produced are smaller than the ones produced using Sun’s native tools; this difference is quite significant for binaries containing debugging information. !

!

Starting with Solaris 7, the operating system is capable of executing 64-bit SPARC V9 binaries. GCC 3.1 and later properly supports ! this; the -m64 option enables 64-bit code generation. However, if all you want is code tuned for the UltraSPARC CPU, you ! should try the -mtune=ultrasparc option instead, which produces code that, unlike full 64-bit code, can still run on non-UltraSPARC machines. !

!

When configuring on a Solaris 7 or later system that is running a kernel that supports only 32-bit binaries, one must configure with ! --disable-multilib, since we will not be able to build the 64-bit target libraries. !

!

GCC 3.3 and GCC 3.4 trigger code generation bugs in earlier versions of the GNU compiler (especially GCC 3.0.x versions), which lead to the miscompilation of the stage1 compiler and the subsequent failure of the bootstrap process. A workaround is to use GCC 3.2.3 as an intermediary stage, i.e. to bootstrap that compiler with the base compiler and then use it to bootstrap the final compiler. !

!

GCC 3.4 triggers a code generation bug in versions 5.4 (Sun ONE Studio 7) and 5.5 (Sun ONE Studio 8) of the Sun compiler, which causes a bootstrap failure in form of a miscompilation of the stage1 compiler by the Sun compiler. This is Sun bug 4974440. This is fixed with patch 112760-07. !

!

GCC 3.4 changed the default debugging format from Stabs to DWARF-2 for 32-bit code on Solaris 7 and later. If you use the Sun assembler, this change apparently runs afoul of Sun bug 4910101 (which is referenced as ! an x86-only problem by Sun, probably because they do not use DWARF-2). A symptom of the problem is that you cannot compile C++ programs like ! groff 1.19.1 without getting messages similar to the following: !

!
! 
ld: warning: relocation error: R_SPARC_UA32: …
!   external symbolic relocation against non-allocatable section
!   .debug_info cannot be processed at runtime: relocation ignored.
!
!

To work around this problem, compile with -gstabs+ instead of ! plain -g. !

!

When configuring the GNU Multiple Precision Library (GMP), the MPFR library or the MPC library on a Solaris 7 or later system, the canonical ! target triplet must be specified as the build parameter on the ! configure line. This target triplet can be obtained by invoking ./config.guess in the toplevel source directory of GCC (and not that of GMP or MPFR or MPC). For example on a Solaris 9 system: -

-
- 
% ./configure --build=sparc-sun-solaris2.9 --prefix=xxx
-
!
!

sparc-sun-solaris2.10

There is a bug in older versions of the Sun assembler which breaks thread-local storage (TLS). A typical error message is -

-
- 
ld: fatal: relocation error: R_SPARC_TLS_LE_HIX22: file /var/tmp//ccamPA1v.o:
-   symbol <unknown>: bad symbol type SECT: symbol type must be TLS
-
!

This bug is fixed in Sun patch 118683-03 or later. !

!
!

sparc-*-linux*

GCC versions 3.0 and higher require binutils 2.11.2 and glibc 2.2.4 or newer on this platform. All earlier binutils and glibc releases mishandled unaligned relocations on sparc-*-* targets. -

!
!

sparc64-*-solaris2*

When configuring the GNU Multiple Precision Library (GMP), the MPFR library or the MPC library, the canonical target triplet must be specified ! as the build parameter on the configure line. For example on a Solaris 9 system: -

-
- 
% ./configure --build=sparc64-sun-solaris2.9 --prefix=xxx
-
!

The following compiler flags must be specified in the configure step in order to bootstrap this target with the Sun compiler: -

-
- 
% CC="cc -xarch=v9 -xildoff" srcdir/configure [options] [target]
-
!

-xarch=v9 specifies the SPARC-V9 architecture to the Sun toolchain ! and -xildoff turns off the incremental linker. !

!
!

sparcv9-*-solaris2*

!

This is a synonym for ‘sparc64-*-solaris2*’. !

!
!

c6x-*-*

The C6X family of processors. This port requires binutils-2.22 or newer. !

!
!

tilegx-*-linux*

The TILE-Gx processor running GNU/Linux. This port requires binutils-2.22 or newer. !

!
!

tilepro-*-linux*

The TILEPro processor running GNU/Linux. This port requires binutils-2.22 or newer. !

!
!

*-*-vxworks*

Support for VxWorks is in flux. At present GCC supports only the ! very recent VxWorks 5.5 (aka Tornado 2.2) release, and only on PowerPC. ! We welcome patches for other architectures supported by VxWorks 5.5. Support for VxWorks AE would also be welcome; we believe this is merely a matter of writing an appropriate “configlette” (see below). We are not interested in supporting older, a.out or COFF-based, versions of VxWorks in GCC 3. !

!

VxWorks comes with an older version of GCC installed in ! $WIND_BASE/host; we recommend you do not overwrite it. ! Choose an installation prefix entirely outside $WIND_BASE. ! Before running configure, create the directories prefix ! and prefix/bin. Link or copy the appropriate assembler, ! linker, etc. into prefix/bin, and set your PATH to ! include that directory while running both configure and ! make. !

!

You must give configure the ! --with-headers=$WIND_BASE/target/h switch so that it can find the VxWorks system headers. Since VxWorks is a cross compilation ! target only, you must also specify --target=target. ! configure will attempt to create the directory ! prefix/target/sys-include and copy files into it; ! make sure the user running configure has sufficient privilege to do so. !

!

GCC’s exception handling runtime requires a special “configlette” ! module, contrib/gthr_supp_vxw_5x.c. Follow the instructions in that file to add the module to your kernel build. (Future versions of VxWorks will incorporate this module.) !

!
!

x86_64-*-*, amd64-*-*

GCC supports the x86-64 architecture implemented by the AMD64 processor ! (amd64-*-* is an alias for x86_64-*-*) on GNU/Linux, FreeBSD and NetBSD. On GNU/Linux the default is a bi-arch compiler which is able to generate ! both 64-bit x86-64 and 32-bit x86 code (via the -m32 switch). !

!
!

x86_64-*-solaris2.1[0-9]*

GCC also supports the x86-64 architecture implemented by the AMD64 ! processor (‘amd64-*-*’ is an alias for ‘x86_64-*-*’) on Solaris 10 or later. Unlike other systems, without special options a bi-arch compiler is built which generates 32-bit code by default, but ! can generate 64-bit x86-64 code with the -m64 switch. Since GCC 4.7, there is also configuration that defaults to 64-bit code, but ! can generate 32-bit code with -m32. To configure and build ! this way, you have to provide all support libraries like libgmp ! as 64-bit code, configure with --target=x86_64-pc-solaris2.1x ! and ‘CC=gcc -m64’. !

!
!

xtensa*-*-elf

This target is intended for embedded Xtensa systems using the ! ‘newlib’ C library. It uses ELF but does not support shared objects. Designed-defined instructions specified via the Tensilica Instruction Extension (TIE) language are only supported through inline assembly. !

!

The Xtensa configuration information must be specified prior to ! building GCC. The include/xtensa-config.h header file contains the configuration information. If you created your own Xtensa configuration with the Xtensa Processor Generator, the downloaded files include a customized copy of this header file, which you can use to replace the default header file. !

!
!

xtensa*-*-linux*

This target is for Xtensa systems running GNU/Linux. It supports ELF shared objects and the GNU C library (glibc). It also generates position-independent code (PIC) regardless of whether the ! -fpic or -fPIC options are used. In other respects, this target is the same as the ! ‘xtensa*-*-elf’ target. !

!
!

Microsoft Windows

- -

Intel 16-bit versions

The 16-bit versions of Microsoft Windows, such as Windows 3.1, are not supported. !

!

However, the 32-bit port has limited support for Microsoft Windows 3.11 in the Win32s environment, as a target only. See below. !

! !

Intel 32-bit versions

The 32-bit versions of Windows, including Windows 95, Windows NT, Windows XP, and Windows Vista, are supported by several different target platforms. These targets differ in which Windows subsystem they target and which C libraries are used. -

-
    -
  • Cygwin *-*-cygwin: Cygwin provides a user-space - Linux API emulation layer in the Win32 subsystem. -
  • Interix *-*-interix: The Interix subsystem - provides native support for POSIX. -
  • MinGW *-*-mingw32: MinGW is a native GCC port for - the Win32 subsystem that provides a subset of POSIX. -
  • MKS i386-pc-mks: NuTCracker from MKS. See - http://www.mkssoftware.com/ for more information. -
! !

Intel 64-bit versions

GCC contains support for x86-64 using the mingw-w64 ! runtime library, available from http://mingw-w64.sourceforge.net/. This library should be used with the target triple x86_64-pc-mingw32. !

!

Presently Windows for Itanium is not supported. !

! !

Windows CE

Windows CE is supported as a target only on Hitachi SuperH (sh-wince-pe), and MIPS (mips-wince-pe). !

! !

Other Windows Platforms

GCC no longer supports Windows NT on the Alpha or PowerPC. !

!

GCC no longer supports the Windows POSIX subsystem. However, it does support the Interix subsystem. See above. !

!

Old target names including *-*-winnt and *-*-windowsnt are no longer used. !

!

PW32 (i386-pc-pw32) support was never completed, and the project seems to be inactive. See http://pw32.sourceforge.net/ for more information. !

!

UWIN support has been removed due to a lack of maintenance. !

!
!

*-*-cygwin

Ports of GCC are included with the Cygwin environment. !

!

GCC will build under Cygwin without modification; it does not build ! with Microsoft’s C++ compiler and there are no plans to make it do so. !

!

The Cygwin native compiler can be configured to target any 32-bit x86 cpu architecture desired; the default is i686-pc-cygwin. It should be used with as up-to-date a version of binutils as possible; use either the latest official GNU binutils release in the Cygwin distribution, or version 2.20 or above if building your own. !

!
!

*-*-interix

The Interix target is used by OpenNT, Interix, Services For UNIX (SFU), and Subsystem for UNIX-based Applications (SUA). Applications compiled with this target run in the Interix subsystem, which is separate from the Win32 subsystem. This target was last known to work in GCC 3.3. -

-
-

*-*-mingw32

!

GCC will build with and support only MinGW runtime 3.12 and later. Earlier versions of headers are incompatible with the new default semantics of extern inline in -std=c99 and -std=gnu99 modes. !

!
!

Older systems

GCC contains support files for many older (1980s and early 1990s) Unix variants. For the most part, support for these systems has not been deliberately removed, but it has not been maintained for several years and may suffer from bitrot. !

!

Starting with GCC 3.1, each release has a list of “obsoleted” systems. Support for these systems is still present in that release, but ! configure will fail unless the --enable-obsolete option is given. Unless a maintainer steps forward, support for these systems will be removed from the next release of GCC. !

!

Support for old systems as hosts for GCC can cause problems if the workarounds for compiler, library and operating system bugs affect the cleanliness or maintainability of the rest of GCC. In some cases, to bring GCC up on such a system, if still possible with current GCC, may require first installing an old version of GCC which did work on that system, and using it to compile a more recent GCC, to avoid bugs in the vendor compiler. Old releases of GCC 1 and GCC 2 are available in the ! old-releases directory on the GCC mirror ! sites. Header bugs may generally be avoided using ! fixincludes, but bugs or deficiencies in libraries and the operating system may still cause problems. !

!

Support for older systems as targets for cross-compilation is less problematic than support for them as hosts for GCC; if an enthusiast wishes to make such a target work again (including resurrecting any of the targets that never worked with GCC 2, starting from the last --- 647,1441 ---- IZ98477 for AIX 5.3 TL11 and IZ98134 for AIX 5.3 TL12). AIX 5.3 TL11 SP8, AIX 5.3 TL12 SP5, AIX 6.1 TL04 SP11, AIX 6.1 TL05 SP7, AIX 6.1 TL06 SP6, AIX 6.1 TL07 and AIX 7.1 TL01 should include the fix. ! !

Building libstdc++.a requires a fix for an AIX Assembler bug APAR IY26685 (AIX 4.3) or APAR IY25528 (AIX 5.1). It also requires a fix for another AIX Assembler bug and a co-dependent AIX Archiver fix referenced as APAR IY53606 (AIX 5.2) or as APAR IY54774 (AIX 5.1) ! !

‘libstdc++’ in GCC 3.4 increments the major version number of the ! shared object and GCC installation places the libstdc++.a shared library in a common location which will overwrite the and GCC 3.3 version of the shared library. Applications either need to be re-linked against the new shared library or the GCC 3.1 and GCC 3.3 ! versions of the ‘libstdc++’ shared object needs to be available ! to the AIX runtime loader. The GCC 3.1 ‘libstdc++.so.4’, if ! present, and GCC 3.3 ‘libstdc++.so.5’ shared objects can be installed for runtime dynamic loading using the following steps to set ! the ‘F_LOADONLY’ flag in the shared object for each ! multilib libstdc++.a installed: !

Extract the shared objects from the currently installed ! libstdc++.a archive: ! 

     % ar -x libstdc++.a libstdc++.so.4 libstdc++.so.5
!
!

Enable the ‘F_LOADONLY’ flag so that the shared object will be available for runtime dynamic loading, but not linking: ! 

     % strip -e libstdc++.so.4 libstdc++.so.5
!
!

Archive the runtime-only shared object in the GCC 3.4 ! libstdc++.a archive: ! 

     % ar -q libstdc++.a libstdc++.so.4 libstdc++.so.5
!
!

Linking executables and shared libraries may produce warnings of duplicate symbols. The assembly files generated by GCC for AIX always have included multiple symbol definitions for certain global variable and function declarations in the original program. The warnings should not prevent the linker from producing a correct library or runnable executable. ! !

AIX 4.3 utilizes a “large format” archive to support both 32-bit and 64-bit object modules. The routines provided in AIX 4.3.0 and AIX 4.3.1 ! to parse archive libraries did not handle the new format correctly. These routines are used by GCC and result in error messages during linking such as “not a COFF file”. The version of the routines shipped ! with AIX 4.3.1 should work for a 32-bit environment. The -g option of the archive command may be used to create archives of 32-bit objects using the original “small format”. A correct version of the routines is shipped with AIX 4.3.2 and above. ! !

Some versions of the AIX binder (linker) can fail with a relocation ! overflow severe error when the -bbigtoc option is used to link GCC-produced object files into an executable that overflows the TOC. A fix for APAR IX75823 (OVERFLOW DURING LINK WHEN USING GCC AND -BBIGTOC) is available from IBM Customer Support and from its techsupport.services.ibm.com website as PTF U455193. ! !

The AIX 4.3.2.1 linker (bos.rte.bind_cmds Level 4.3.2.1) will dump core with a segmentation fault when invoked by any version of GCC. A fix for APAR IX87327 is available from IBM Customer Support and from its techsupport.services.ibm.com website as PTF U461879. This fix is incorporated in AIX 4.3.3 and above. ! !

The initial assembler shipped with AIX 4.3.0 generates incorrect object files. A fix for APAR IX74254 (64BIT DISASSEMBLED OUTPUT FROM COMPILER FAILS TO ASSEMBLE/BIND) is available from IBM Customer Support and from its techsupport.services.ibm.com website as PTF U453956. This fix is incorporated in AIX 4.3.1 and above. ! !

AIX provides National Language Support (NLS). Compilers and assemblers use NLS to support locale-specific representations of various data ! formats including floating-point numbers (e.g., ‘.’ vs ‘,’ for separating decimal fractions). There have been problems reported where GCC does not produce the same floating-point formats that the assembler ! expects. If one encounters this problem, set the LANG ! environment variable to ‘C’ or ‘En_US’. ! !

A default can be specified with the -mcpu=cpu_type ! switch and using the configure option --with-cpu-cpu_type. ! !

! !

iq2000-*-elf

!

Vitesse IQ2000 processors. These are used in embedded applications. There are no standard Unix configurations. ! !

! !

lm32-*-elf

! !

Lattice Mico32 processor. This configuration is intended for embedded systems. ! !

! !

lm32-*-uclinux

! !

Lattice Mico32 processor. This configuration is intended for embedded systems running uClinux. ! !

! !

m32c-*-elf

! !

Renesas M32C processor. This configuration is intended for embedded systems. ! !

! !

m32r-*-elf

! !

Renesas M32R processor. This configuration is intended for embedded systems. ! !

! !

m68k-*-*

!

By default, ! ‘m68k-*-elf*’, ‘m68k-*-rtems’, ‘m68k-*-uclinux’ and ! ‘m68k-*-linux’ build libraries for both M680x0 and ColdFire processors. If you only need the M680x0 libraries, you can omit the ColdFire ones by passing ! --with-arch=m68k to configure. Alternatively, you ! can omit the M680x0 libraries by passing --with-arch=cf to ! configure. These targets default to 5206 or 5475 code as appropriate for the target system when ! configured with --with-arch=cf and 68020 code otherwise. ! !

The ‘m68k-*-netbsd’ and ! ‘m68k-*-openbsd’ targets also support the --with-arch option. They will generate ColdFire CFV4e code when configured with ! --with-arch=cf and 68020 code otherwise. ! !

You can override the default processors listed above by configuring ! with --with-cpu=target. This target can either ! be a -mcpu argument or one of the following values: ! ‘m68000’, ‘m68010’, ‘m68020’, ‘m68030’, ! ‘m68040’, ‘m68060’, ‘m68020-40’ and ‘m68020-60’. ! !

GCC requires at least binutils version 2.17 on these targets. ! !

! !

m68k-*-uclinux

!

GCC 4.3 changed the uClinux configuration so that it uses the ! ‘m68k-linux-gnu’ ABI rather than the ‘m68k-elf’ ABI. It also added improved support for C++ and flat shared libraries, both of which were ABI changes. !

! !

mep-*-elf

! !

Toshiba Media embedded Processor. This configuration is intended for embedded systems. ! !

! !

microblaze-*-elf

! !

Xilinx MicroBlaze processor. This configuration is intended for embedded systems. ! !

! !

mips-*-*

!

If on a MIPS system you get an error message saying “does not have gp ! sections for all it's [sic] sectons [sic]”, don't worry about it. This happens whenever you use GAS with the MIPS linker, but there is not really anything wrong, and it is okay to use the output file. You can stop such warnings by installing the GNU linker. ! !

It would be nice to extend GAS to produce the gp tables, but they are optional, and there should not be a warning about their absence. ! !

The libstdc++ atomic locking routines for MIPS targets requires MIPS II and later. A patch went in just after the GCC 3.3 release to ! make ‘mips*-*-*’ use the generic implementation instead. You can also ! configure for ‘mipsel-elf’ as a workaround. The ! ‘mips*-*-linux*’ target continues to use the MIPS II routines. More work on this is expected in future releases. ! ! !

The built-in __sync_* functions are available on MIPS II and ! later systems and others that support the ‘ll’, ‘sc’ and ! ‘sync’ instructions. This can be overridden by passing ! --with-llsc or --without-llsc when configuring GCC. Since the Linux kernel emulates these instructions if they are ! missing, the default for ‘mips*-*-linux*’ targets is ! --with-llsc. The --with-llsc and ! --without-llsc configure options may be overridden at compile ! time by passing the -mllsc or -mno-llsc options to the compiler. ! !

MIPS systems check for division by zero (unless ! -mno-check-zero-division is passed to the compiler) by generating either a conditional trap or a break instruction. Using trap results in smaller code, but is only supported on MIPS II and later. Also, some versions of the Linux kernel have a bug that prevents trap from generating the proper signal (SIGFPE). To enable ! the use of break, use the --with-divide=breaks ! configure option when configuring GCC. The default is to use traps on systems that support them. ! !

The assembler from GNU binutils 2.17 and earlier has a bug in the way it sorts relocations for REL targets (o32, o64, EABI). This can cause bad code to be generated for simple C++ programs. Also the linker from GNU binutils versions prior to 2.17 has a bug which causes the ! runtime linker stubs in very large programs, like libgcj.so, to be incorrectly generated. GNU Binutils 2.18 and later (and snapshots made after Nov. 9, 2006) should be free from both of these problems. ! !

! !

mips-sgi-irix5

Support for IRIX 5 has been removed in GCC 4.6. ! !

! !

mips-sgi-irix6

Support for IRIX 6.5 has been removed in GCC 4.8. Support for IRIX 6 releases before 6.5 has been removed in GCC 4.6, as well as support for the O32 ABI. ! !

! !

moxie-*-elf

!

The moxie processor. !

! !

powerpc-*-*

! !

You can specify a default version for the -mcpu=cpu_type ! switch by using the configure option --with-cpu-cpu_type. ! !

You will need binutils 2.15 or newer for a working GCC. ! !

! !

powerpc-*-darwin*

!

PowerPC running Darwin (Mac OS X kernel). ! !

Pre-installed versions of Mac OS X may not include any developer tools, meaning that you will not be able to build GCC from source. Tool binaries are available at http://opensource.apple.com/. ! !

This version of GCC requires at least cctools-590.36. The cctools-590.36 package referenced from http://gcc.gnu.org/ml/gcc/2006-03/msg00507.html will not work on systems older than 10.3.9 (aka darwin7.9.0). ! !

! !

powerpc-*-elf

!

PowerPC system in big endian mode, running System V.4. ! !

! !

powerpc*-*-linux-gnu*

PowerPC system in big endian mode running Linux. ! !

! !

powerpc-*-netbsd*

!

PowerPC system in big endian mode running NetBSD. ! !

! !

powerpc-*-eabisim

!

Embedded PowerPC system in big endian mode for use in running under the PSIM simulator. ! !

! !

powerpc-*-eabi

!

Embedded PowerPC system in big endian mode. ! !

! !

powerpcle-*-elf

!

PowerPC system in little endian mode, running System V.4. ! !

! !

powerpcle-*-eabisim

!

Embedded PowerPC system in little endian mode for use in running under the PSIM simulator. ! !

! !

powerpcle-*-eabi

!

Embedded PowerPC system in little endian mode. ! !

! !

rl78-*-elf

! !

The Renesas RL78 processor. This configuration is intended for embedded systems. ! !

! !

rx-*-elf

!

The Renesas RX processor. See http://eu.renesas.com/fmwk.jsp?cnt=rx600_series_landing.jsp&fp=/products/mpumcu/rx_family/rx600_series for more information about this processor. ! !

! !

s390-*-linux*

!

S/390 system running GNU/Linux for S/390. ! !

! !

s390x-*-linux*

!

zSeries system (64-bit) running GNU/Linux for zSeries. ! !

! !

s390x-ibm-tpf*

!

zSeries system (64-bit) running TPF. This platform is supported as cross-compilation target only. ! !

! ! ! ! !

*-*-solaris2*

Support for Solaris 8 has removed in GCC 4.8. Support for Solaris 7 has been removed in GCC 4.6. ! !

Sun does not ship a C compiler with Solaris 2 before Solaris 10, though you can download the Sun Studio compilers for free. In Solaris 10 and ! 11, GCC 3.4.3 is available as /usr/sfw/bin/gcc. Solaris 11 ! also provides GCC 4.5.2 as /usr/gcc/4.5/bin/gcc. Alternatively, you can install a pre-built GCC to bootstrap and install GCC. See the binaries page for details. ! !

The Solaris 2 /bin/sh will often fail to configure ! ‘libstdc++-v3’, ‘boehm-gc’ or ‘libjava’. We therefore recommend using the following initial sequence of commands ! 

     % CONFIG_SHELL=/bin/ksh
!      % export CONFIG_SHELL
!
!

and proceed as described in the configure instructions. In addition we strongly recommend specifying an absolute path to invoke ! srcdir/configure. ! !

Solaris 2 comes with a number of optional OS packages. Some of these are needed to use GCC fully, namely SUNWarc, SUNWbtool, SUNWesu, SUNWhea, SUNWlibm, SUNWsprot, and SUNWtoo. If you did not install all optional packages when installing Solaris 2, you will need to verify that the packages that GCC needs are installed. ! !

To check whether an optional package is installed, use ! the pkginfo command. To add an optional package, use the ! pkgadd command. For further details, see the Solaris 2 documentation. ! !

Trying to use the linker and other tools in ! /usr/ucb to install GCC has been observed to cause trouble. For example, the linker may hang indefinitely. The fix is to remove ! /usr/ucb from your PATH. ! !

The build process works more smoothly with the legacy Sun tools so, if you ! have /usr/xpg4/bin in your PATH, we recommend that you place ! /usr/bin before /usr/xpg4/bin for the duration of the build. ! !

We recommend the use of the Sun assembler or the GNU assembler, in ! conjunction with the Sun linker. The GNU as versions included in Solaris 10, from GNU binutils 2.15, and Solaris 11, from GNU binutils 2.19, are known to work. They can be found in ! /usr/sfw/bin/gas. Current versions of GNU binutils (2.22) are known to work as well. Note that your mileage may vary if you use a combination of the GNU tools and the Sun tools: while the ! combination GNU as + Sun ld should reasonably work, ! the reverse combination Sun as + GNU ld may fail to ! build or cause memory corruption at runtime in some cases for C++ programs. ! ! GNU ld usually works as well, although the version included in Solaris 10 cannot be used due to several bugs. Again, the current version (2.22) is known to work, but generally lacks platform specific ! features, so better stay with Sun ld. To use the LTO linker ! plugin (-fuse-linker-plugin) with GNU ld, GNU ! binutils must be configured with --enable-largefile. ! !

To enable symbol versioning in ‘libstdc++’ with Sun ld, ! you need to have any version of GNU c++filt, which is part of ! GNU binutils. ‘libstdc++’ symbol versioning will be disabled if no ! appropriate version is found. Sun c++filt from the Sun Studio compilers does not work. ! !

Sun bug 4296832 turns up when compiling X11 headers with GCC 2.95 or ! newer: g++ will complain that types are missing. These headers assume that omitting the type means int; this assumption worked for C90 but is wrong for C++, and is now wrong for C99 also. ! !

Sun bug 4927647 sometimes causes random spurious testsuite failures ! related to missing diagnostic output. This bug doesn't affect GCC ! itself, rather it is a kernel bug triggered by the expect program which is used only by the GCC testsuite driver. When the bug ! causes the expect program to miss anticipated output, extra testsuite failures appear. ! !

There are patches for Solaris 9 (117171-11 or newer for SPARC, 117172-11 or newer for Intel) that address this problem. ! !

Thread-local storage (TLS) is supported in Solaris 9, but requires ! some patches. The ‘libthread’ patches provide the ! __tls_get_addr (SPARC, 64-bit x86) resp. ___tls_get_addr (32-bit x86) functions. On Solaris 9, the necessary support on SPARC is present since FCS, while 114432-05 or newer is required on Intel. Additionally, on Solaris 9/x86, patch 113986-02 or newer is ! required for the Sun ld and runtime linker (ld.so.1) support, while Solaris 9/SPARC works since FCS. The linker ! patches must be installed even if GNU ld is used. Sun ! as in Solaris 9 doesn't support the necessary ! relocations, so GNU as must be used. The configure script checks for those prerequisites and automatically enables TLS support if they are met. Although those minimal patch versions should work, it is recommended to use the latest patch versions which include additional bug fixes. ! !

! !

sparc*-*-*

This section contains general configuration information for all SPARC-based platforms. In addition to reading this section, please read all other sections that match your target. ! !

Newer versions of the GNU Multiple Precision Library (GMP), the MPFR library and the MPC library are known to be miscompiled by earlier versions of GCC on these platforms. We therefore recommend the use of the exact versions of these libraries listed as minimal versions in the prerequisites. ! !

! !

sparc-sun-solaris2*

When GCC is configured to use GNU binutils 2.14 or later, the binaries ! produced are smaller than the ones produced using Sun's native tools; this difference is quite significant for binaries containing debugging information. ! !

Starting with Solaris 7, the operating system is capable of executing 64-bit SPARC V9 binaries. GCC 3.1 and later properly supports ! this; the -m64 option enables 64-bit code generation. However, if all you want is code tuned for the UltraSPARC CPU, you ! should try the -mtune=ultrasparc option instead, which produces code that, unlike full 64-bit code, can still run on non-UltraSPARC machines. ! !

When configuring on a Solaris 7 or later system that is running a kernel that supports only 32-bit binaries, one must configure with ! --disable-multilib, since we will not be able to build the 64-bit target libraries. ! !

GCC 3.3 and GCC 3.4 trigger code generation bugs in earlier versions of the GNU compiler (especially GCC 3.0.x versions), which lead to the miscompilation of the stage1 compiler and the subsequent failure of the bootstrap process. A workaround is to use GCC 3.2.3 as an intermediary stage, i.e. to bootstrap that compiler with the base compiler and then use it to bootstrap the final compiler. ! !

GCC 3.4 triggers a code generation bug in versions 5.4 (Sun ONE Studio 7) and 5.5 (Sun ONE Studio 8) of the Sun compiler, which causes a bootstrap failure in form of a miscompilation of the stage1 compiler by the Sun compiler. This is Sun bug 4974440. This is fixed with patch 112760-07. ! !

GCC 3.4 changed the default debugging format from Stabs to DWARF-2 for 32-bit code on Solaris 7 and later. If you use the Sun assembler, this change apparently runs afoul of Sun bug 4910101 (which is referenced as ! an x86-only problem by Sun, probably because they do not use DWARF-2). A symptom of the problem is that you cannot compile C++ programs like ! groff 1.19.1 without getting messages similar to the following: ! 

     ld: warning: relocation error: R_SPARC_UA32: ...
!        external symbolic relocation against non-allocatable section
!        .debug_info cannot be processed at runtime: relocation ignored.
!
!

To work around this problem, compile with -gstabs+ instead of ! plain -g. ! !

When configuring the GNU Multiple Precision Library (GMP), the MPFR library or the MPC library on a Solaris 7 or later system, the canonical ! target triplet must be specified as the build parameter on the ! configure line. This target triplet can be obtained by invoking ./config.guess in the toplevel source directory of GCC (and not that of GMP or MPFR or MPC). For example on a Solaris 9 system: ! 

     % ./configure --build=sparc-sun-solaris2.9 --prefix=xxx
!
!

! !

sparc-sun-solaris2.10

There is a bug in older versions of the Sun assembler which breaks thread-local storage (TLS). A typical error message is ! 

     ld: fatal: relocation error: R_SPARC_TLS_LE_HIX22: file /var/tmp//ccamPA1v.o:
!        symbol <unknown>: bad symbol type SECT: symbol type must be TLS
!
!

This bug is fixed in Sun patch 118683-03 or later. ! !

! !

sparc-*-linux*

GCC versions 3.0 and higher require binutils 2.11.2 and glibc 2.2.4 or newer on this platform. All earlier binutils and glibc releases mishandled unaligned relocations on sparc-*-* targets. !

! !

sparc64-*-solaris2*

When configuring the GNU Multiple Precision Library (GMP), the MPFR library or the MPC library, the canonical target triplet must be specified ! as the build parameter on the configure line. For example on a Solaris 9 system: ! 

     % ./configure --build=sparc64-sun-solaris2.9 --prefix=xxx
!
!

The following compiler flags must be specified in the configure step in order to bootstrap this target with the Sun compiler: ! 

     % CC="cc -xarch=v9 -xildoff" srcdir/configure [options] [target]
!
!

-xarch=v9 specifies the SPARC-V9 architecture to the Sun toolchain ! and -xildoff turns off the incremental linker. !

! !

sparcv9-*-solaris2*

! !

This is a synonym for ‘sparc64-*-solaris2*’. ! !

! !

c6x-*-*

The C6X family of processors. This port requires binutils-2.22 or newer. ! !

! !

tilegx-*-linux*

The TILE-Gx processor running GNU/Linux. This port requires binutils-2.22 or newer. ! !

! !

tilepro-*-linux*

The TILEPro processor running GNU/Linux. This port requires binutils-2.22 or newer. ! !

! !

*-*-vxworks*

!

Support for VxWorks is in flux. At present GCC supports only the ! very recent VxWorks 5.5 (aka Tornado 2.2) release, and only on PowerPC. ! We welcome patches for other architectures supported by VxWorks 5.5. Support for VxWorks AE would also be welcome; we believe this is merely a matter of writing an appropriate “configlette” (see below). We are not interested in supporting older, a.out or COFF-based, versions of VxWorks in GCC 3. ! !

VxWorks comes with an older version of GCC installed in ! $WIND_BASE/host; we recommend you do not overwrite it. ! Choose an installation prefix entirely outside $WIND_BASE. ! Before running configure, create the directories prefix ! and prefix/bin. Link or copy the appropriate assembler, ! linker, etc. into prefix/bin, and set your PATH to ! include that directory while running both configure and ! make. ! !

You must give configure the ! --with-headers=$WIND_BASE/target/h switch so that it can find the VxWorks system headers. Since VxWorks is a cross compilation ! target only, you must also specify --target=target. ! configure will attempt to create the directory ! prefix/target/sys-include and copy files into it; ! make sure the user running configure has sufficient privilege to do so. ! !

GCC's exception handling runtime requires a special “configlette” ! module, contrib/gthr_supp_vxw_5x.c. Follow the instructions in that file to add the module to your kernel build. (Future versions of VxWorks will incorporate this module.) ! !

! !

x86_64-*-*, amd64-*-*

GCC supports the x86-64 architecture implemented by the AMD64 processor ! (amd64-*-* is an alias for x86_64-*-*) on GNU/Linux, FreeBSD and NetBSD. On GNU/Linux the default is a bi-arch compiler which is able to generate ! both 64-bit x86-64 and 32-bit x86 code (via the -m32 switch). ! !

! !

x86_64-*-solaris2.1[0-9]*

GCC also supports the x86-64 architecture implemented by the AMD64 ! processor (‘amd64-*-*’ is an alias for ‘x86_64-*-*’) on Solaris 10 or later. Unlike other systems, without special options a bi-arch compiler is built which generates 32-bit code by default, but ! can generate 64-bit x86-64 code with the -m64 switch. Since GCC 4.7, there is also configuration that defaults to 64-bit code, but ! can generate 32-bit code with -m32. To configure and build ! this way, you have to provide all support libraries like libgmp ! as 64-bit code, configure with --target=x86_64-pc-solaris2.1x ! and ‘CC=gcc -m64’. ! !

! !

xtensa*-*-elf

This target is intended for embedded Xtensa systems using the ! ‘newlib’ C library. It uses ELF but does not support shared objects. Designed-defined instructions specified via the Tensilica Instruction Extension (TIE) language are only supported through inline assembly. ! !

The Xtensa configuration information must be specified prior to ! building GCC. The include/xtensa-config.h header file contains the configuration information. If you created your own Xtensa configuration with the Xtensa Processor Generator, the downloaded files include a customized copy of this header file, which you can use to replace the default header file. ! !

! !

xtensa*-*-linux*

This target is for Xtensa systems running GNU/Linux. It supports ELF shared objects and the GNU C library (glibc). It also generates position-independent code (PIC) regardless of whether the ! -fpic or -fPIC options are used. In other respects, this target is the same as the ! ‘xtensa*-*-elf’ target. ! !

! !

Microsoft Windows

! !

Intel 16-bit versions

The 16-bit versions of Microsoft Windows, such as Windows 3.1, are not supported. ! !

However, the 32-bit port has limited support for Microsoft Windows 3.11 in the Win32s environment, as a target only. See below. ! !

Intel 32-bit versions

The 32-bit versions of Windows, including Windows 95, Windows NT, Windows XP, and Windows Vista, are supported by several different target platforms. These targets differ in which Windows subsystem they target and which C libraries are used. !

    !
  • Cygwin *-*-cygwin: Cygwin provides a user-space ! Linux API emulation layer in the Win32 subsystem. !
  • Interix *-*-interix: The Interix subsystem ! provides native support for POSIX. !
  • MinGW *-*-mingw32: MinGW is a native GCC port for ! the Win32 subsystem that provides a subset of POSIX. !
  • MKS i386-pc-mks: NuTCracker from MKS. See ! http://www.mkssoftware.com/ for more information. !
! !

Intel 64-bit versions

GCC contains support for x86-64 using the mingw-w64 ! runtime library, available from http://mingw-w64.sourceforge.net/. This library should be used with the target triple x86_64-pc-mingw32. ! !

Presently Windows for Itanium is not supported. ! !

Windows CE

Windows CE is supported as a target only on Hitachi SuperH (sh-wince-pe), and MIPS (mips-wince-pe). ! !

Other Windows Platforms

GCC no longer supports Windows NT on the Alpha or PowerPC. ! !

GCC no longer supports the Windows POSIX subsystem. However, it does support the Interix subsystem. See above. ! !

Old target names including *-*-winnt and *-*-windowsnt are no longer used. ! !

PW32 (i386-pc-pw32) support was never completed, and the project seems to be inactive. See http://pw32.sourceforge.net/ for more information. ! !

UWIN support has been removed due to a lack of maintenance. ! !

! !

*-*-cygwin

Ports of GCC are included with the Cygwin environment. ! !

GCC will build under Cygwin without modification; it does not build ! with Microsoft's C++ compiler and there are no plans to make it do so. ! !

The Cygwin native compiler can be configured to target any 32-bit x86 cpu architecture desired; the default is i686-pc-cygwin. It should be used with as up-to-date a version of binutils as possible; use either the latest official GNU binutils release in the Cygwin distribution, or version 2.20 or above if building your own. ! !

! !

*-*-interix

The Interix target is used by OpenNT, Interix, Services For UNIX (SFU), and Subsystem for UNIX-based Applications (SUA). Applications compiled with this target run in the Interix subsystem, which is separate from the Win32 subsystem. This target was last known to work in GCC 3.3. !

! !

*-*-mingw32

! !

GCC will build with and support only MinGW runtime 3.12 and later. Earlier versions of headers are incompatible with the new default semantics of extern inline in -std=c99 and -std=gnu99 modes. ! !

! !

Older systems

GCC contains support files for many older (1980s and early 1990s) Unix variants. For the most part, support for these systems has not been deliberately removed, but it has not been maintained for several years and may suffer from bitrot. ! !

Starting with GCC 3.1, each release has a list of “obsoleted” systems. Support for these systems is still present in that release, but ! configure will fail unless the --enable-obsolete option is given. Unless a maintainer steps forward, support for these systems will be removed from the next release of GCC. ! !

Support for old systems as hosts for GCC can cause problems if the workarounds for compiler, library and operating system bugs affect the cleanliness or maintainability of the rest of GCC. In some cases, to bring GCC up on such a system, if still possible with current GCC, may require first installing an old version of GCC which did work on that system, and using it to compile a more recent GCC, to avoid bugs in the vendor compiler. Old releases of GCC 1 and GCC 2 are available in the ! old-releases directory on the GCC mirror sites. Header bugs may generally be avoided using ! fixincludes, but bugs or deficiencies in libraries and the operating system may still cause problems. ! !

Support for older systems as targets for cross-compilation is less problematic than support for them as hosts for GCC; if an enthusiast wishes to make such a target work again (including resurrecting any of the targets that never worked with GCC 2, starting from the last *************** version before they were removed), patch *** 1420,1452 **** following the usual requirements would be likely to be accepted, since they should not affect the support for more modern targets. !

!

For some systems, old versions of GNU binutils may also be useful, ! and are available from pub/binutils/old-releases on sourceware.org mirror sites. !

!

Some of the information on specific systems above relates to such older systems, but much of the information about GCC on such systems (which may no longer be applicable to current GCC) is to be found in the GCC texinfo manual. !

!
!

all ELF targets (SVR4, Solaris 2, etc.)

C++ support is significantly better on ELF targets if you use the GNU linker; duplicate copies of inlines, vtables and template instantiations will be discarded automatically. -

- -
-

Return to the GCC Installation page -

- - - - - --- 1443,1473 ---- following the usual requirements would be likely to be accepted, since they should not affect the support for more modern targets. ! !

For some systems, old versions of GNU binutils may also be useful, ! and are available from pub/binutils/old-releases on sourceware.org mirror sites. ! !

Some of the information on specific systems above relates to such older systems, but much of the information about GCC on such systems (which may no longer be applicable to current GCC) is to be found in the GCC texinfo manual. ! !

! !

all ELF targets (SVR4, Solaris 2, etc.)

C++ support is significantly better on ELF targets if you use the GNU linker; duplicate copies of inlines, vtables and template instantiations will be discarded automatically. +

+

Return to the GCC Installation page + + + + + diff -Nrcpad gcc-4.8.2/INSTALL/test.html gcc-4.8.3/INSTALL/test.html *** gcc-4.8.2/INSTALL/test.html Wed Oct 16 07:28:03 2013 --- gcc-4.8.3/INSTALL/test.html Thu May 22 09:13:50 2014 *************** *** 1,315 **** ! ! ! ! ! ! Installing GCC ! ! ! ! ! ! ! ! ! ! ! ! !

Installing GCC

! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

Before you install GCC, we encourage you to run the testsuites and to compare your results with results from a similar configuration that have been submitted to the ! gcc-testresults mailing list. Some of these archived results are linked from the build status lists at http://gcc.gnu.org/buildstat.html, although not everyone who ! reports a successful build runs the testsuites and submits the results. This step is optional and may require you to download additional software, but it can give you confidence in your new GCC installation or point out problems before you install and start using your new GCC. !

!

First, you must have downloaded the testsuites. These are part of the full distribution, but if you downloaded the “core” compiler plus any front ends, you must download the testsuites separately. !

!

Second, you must have the testing tools installed. This includes DejaGnu, Tcl, and Expect; the DejaGnu site has links to these. !

!

If the directories where runtest and expect were ! installed are not in the PATH, you may need to set the following environment variables appropriately, as in the following example (which ! assumes that DejaGnu has been installed under /usr/local): !

!
! 
TCL_LIBRARY = /usr/local/share/tcl8.0
! DEJAGNULIBS = /usr/local/share/dejagnu
!
!

(On systems such as Cygwin, these paths are required to be actual paths, not mounts or links; presumably this is due to some lack of portability in the DejaGnu code.) -

- -

Finally, you can run the testsuite (which may take a long time): -

- 
cd objdir; make -k check
-
!

This will test various components of GCC, such as compiler front ends and runtime libraries. While running the testsuite, DejaGnu might emit some harmless messages resembling ! ‘WARNING: Couldn't find the global config file.’ or ! ‘WARNING: Couldn't find tool init file’ that can be ignored. !

!

If you are testing a cross-compiler, you may want to run the testsuite on a simulator as described at http://gcc.gnu.org/simtest-howto.html. !

! !

How can you run the testsuite on selected tests?

In order to run sets of tests selectively, there are targets ! ‘make check-gcc’ and language specific ‘make check-c’, ! ‘make check-c++’, ‘make check-fortran’, ‘make check-java’, ! ‘make check-ada’, ‘make check-objc’, ‘make check-obj-c++’, ! ‘make check-lto’ ! in the gcc subdirectory of the object directory. You can also ! just run ‘make check’ in a subdirectory of the object directory. !

!

A more selective way to just run all gcc execute tests in the testsuite is to use -

-
- 
make check-gcc RUNTESTFLAGS="execute.exp other-options"
-
!

Likewise, in order to run only the g++ “old-deja” tests in ! the testsuite with filenames matching ‘9805*’, you would use !

!
! 
make check-g++ RUNTESTFLAGS="old-deja.exp=9805* other-options"
!
!

The *.exp files are located in the testsuite directories of the GCC ! source, the most important ones being compile.exp, ! execute.exp, dg.exp and old-deja.exp. ! To get a list of the possible *.exp files, pipe the ! output of ‘make check’ into a file and look at the ! ‘Running … .exp’ lines. !

! !

Passing options and running multiple testsuites

You can pass multiple options to the testsuite using the ! ‘--target_board’ option of DejaGNU, either passed as part of ! ‘RUNTESTFLAGS’, or directly to runtest if you prefer to work outside the makefiles. For example, -

-
- 
make check-g++ RUNTESTFLAGS="--target_board=unix/-O3/-fmerge-constants"
-
!

will run the standard g++ testsuites (“unix” is the target name for a standard native testsuite situation), passing ! ‘-O3 -fmerge-constants’ to the compiler on every test, i.e., slashes separate options. !

!

You can run the testsuites multiple times using combinations of options with a syntax similar to the brace expansion of popular shells: -

-
- 
…"--target_board=arm-sim\{-mhard-float,-msoft-float\}\{-O1,-O2,-O3,\}"
-
!

(Note the empty option caused by the trailing comma in the final group.) ! The following will run each testsuite eight times using the ‘arm-sim’ target, as if you had specified all possible combinations yourself: -

-
- 
--target_board='arm-sim/-mhard-float/-O1 \
-                 arm-sim/-mhard-float/-O2 \
-                 arm-sim/-mhard-float/-O3 \
-                 arm-sim/-mhard-float \
-                 arm-sim/-msoft-float/-O1 \
-                 arm-sim/-msoft-float/-O2 \
-                 arm-sim/-msoft-float/-O3 \
-                 arm-sim/-msoft-float'
-
!

They can be combined as many times as you wish, in arbitrary ways. This list: -

-
- 
…"--target_board=unix/-Wextra\{-O3,-fno-strength\}\{-fomit-frame,\}"
-
!

will generate four combinations, all involving ‘-Wextra’. !

!

The disadvantage to this method is that the testsuites are run in serial, which is a waste on multiprocessor systems. For users with GNU Make and a shell which performs brace expansion, you can run the testsuites in ! parallel by having the shell perform the combinations and make ! do the parallel runs. Instead of using ‘--target_board’, use a special makefile target: -

-
- 
make -jN check-testsuite//test-target/option1/option2/…
-
!

For example, !

!
! 
make -j3 check-gcc//sh-hms-sim/{-m1,-m2,-m3,-m3e,-m4}/{,-nofpu}
!
!

will run three concurrent “make-gcc” testsuites, eventually testing all ten combinations as described above. Note that this is currently only ! supported in the gcc subdirectory. (To see how this works, try ! typing echo before the example given here.) !

! !

Additional testing for Java Class Libraries

!

The Java runtime tests can be executed via ‘make check’ ! in the target/libjava/testsuite directory in the build tree. !

!

The Mauve Project provides a suite of tests for the Java Class Libraries. This suite can be run as part of libgcj testing by placing the Mauve tree within the libjava ! testsuite at libjava/testsuite/libjava.mauve/mauve, or by ! specifying the location of that tree when invoking ‘make’, as in ! ‘make MAUVEDIR=~/mauve check’. !

! !

How to interpret test results

!

The result of running the testsuite are various *.sum and *.log ! files in the testsuite subdirectories. The *.log files contain a detailed log of the compiler invocations and the corresponding ! results, the *.sum files summarize the results. These summaries contain status codes for all tests: -

-
    -
  • PASS: the test passed as expected -
  • XPASS: the test unexpectedly passed -
  • FAIL: the test unexpectedly failed -
  • XFAIL: the test failed as expected -
  • UNSUPPORTED: the test is not supported on this platform -
  • ERROR: the testsuite detected an error -
  • WARNING: the testsuite detected a possible problem -
!

It is normal for some tests to report unexpected failures. At the current time the testing harness does not allow fine grained control over whether or not a test is expected to fail. This problem should be fixed in future releases. -

! !

Submitting test results

If you want to report the results to the GCC project, use the ! contrib/test_summary shell script. Start it in the objdir with !

!
! 
srcdir/contrib/test_summary -p your_commentary.txt \
!     -m gcc-testresults@gcc.gnu.org |sh
!
!

This script uses the Mail program to send the results, so ! make sure it is in your PATH. The file your_commentary.txt is prepended to the testsuite summary and should contain any special remarks you have on your results or your build environment. Please do not edit the testsuite result block or the subject line, as these messages may be automatically processed. -

-
-

Return to the GCC Installation page -

- - - - - - -
- - --- 1,234 ---- ! ! ! Installing GCC: Testing ! ! ! ! ! ! ! ! ! !

Installing GCC: Testing

! ! Before you install GCC, we encourage you to run the testsuites and to compare your results with results from a similar configuration that have been submitted to the ! gcc-testresults mailing list. Some of these archived results are linked from the build status lists at http://gcc.gnu.org/buildstat.html, although not everyone who ! reports a successful build runs the testsuites and submits the results. This step is optional and may require you to download additional software, but it can give you confidence in your new GCC installation or point out problems before you install and start using your new GCC. ! !

First, you must have downloaded the testsuites. These are part of the full distribution, but if you downloaded the “core” compiler plus any front ends, you must download the testsuites separately. ! !

Second, you must have the testing tools installed. This includes DejaGnu, Tcl, and Expect; the DejaGnu site has links to these. ! !

If the directories where runtest and expect were ! installed are not in the PATH, you may need to set the following environment variables appropriately, as in the following example (which ! assumes that DejaGnu has been installed under /usr/local): ! 

     TCL_LIBRARY = /usr/local/share/tcl8.0
!      DEJAGNULIBS = /usr/local/share/dejagnu
!
!

(On systems such as Cygwin, these paths are required to be actual paths, not mounts or links; presumably this is due to some lack of portability in the DejaGnu code.) !

Finally, you can run the testsuite (which may take a long time): ! 

     cd objdir; make -k check
!
!

This will test various components of GCC, such as compiler front ends and runtime libraries. While running the testsuite, DejaGnu might emit some harmless messages resembling ! ‘WARNING: Couldn't find the global config file.’ or ! ‘WARNING: Couldn't find tool init file’ that can be ignored. ! !

If you are testing a cross-compiler, you may want to run the testsuite on a simulator as described at http://gcc.gnu.org/simtest-howto.html. ! !

How can you run the testsuite on selected tests?

In order to run sets of tests selectively, there are targets ! ‘make check-gcc’ and language specific ‘make check-c’, ! ‘make check-c++’, ‘make check-fortran’, ‘make check-java’, ! ‘make check-ada’, ‘make check-objc’, ‘make check-obj-c++’, ! ‘make check-lto’ ! in the gcc subdirectory of the object directory. You can also ! just run ‘make check’ in a subdirectory of the object directory. !

A more selective way to just run all gcc execute tests in the testsuite is to use ! 

     make check-gcc RUNTESTFLAGS="execute.exp other-options"
!
!

Likewise, in order to run only the g++ “old-deja” tests in ! the testsuite with filenames matching ‘9805*’, you would use ! 

     make check-g++ RUNTESTFLAGS="old-deja.exp=9805* other-options"
!
!

The *.exp files are located in the testsuite directories of the GCC ! source, the most important ones being compile.exp, ! execute.exp, dg.exp and old-deja.exp. ! To get a list of the possible *.exp files, pipe the ! output of ‘make check’ into a file and look at the ! ‘Running ... .exp’ lines. ! !

Passing options and running multiple testsuites

You can pass multiple options to the testsuite using the ! ‘--target_board’ option of DejaGNU, either passed as part of ! ‘RUNTESTFLAGS’, or directly to runtest if you prefer to work outside the makefiles. For example, ! 

     make check-g++ RUNTESTFLAGS="--target_board=unix/-O3/-fmerge-constants"
!
!

will run the standard g++ testsuites (“unix” is the target name for a standard native testsuite situation), passing ! ‘-O3 -fmerge-constants’ to the compiler on every test, i.e., slashes separate options. ! !

You can run the testsuites multiple times using combinations of options with a syntax similar to the brace expansion of popular shells: ! 

     ..."--target_board=arm-sim\{-mhard-float,-msoft-float\}\{-O1,-O2,-O3,\}"
!
!

(Note the empty option caused by the trailing comma in the final group.) ! The following will run each testsuite eight times using the ‘arm-sim’ target, as if you had specified all possible combinations yourself: ! 

     --target_board='arm-sim/-mhard-float/-O1 \
!                      arm-sim/-mhard-float/-O2 \
!                      arm-sim/-mhard-float/-O3 \
!                      arm-sim/-mhard-float \
!                      arm-sim/-msoft-float/-O1 \
!                      arm-sim/-msoft-float/-O2 \
!                      arm-sim/-msoft-float/-O3 \
!                      arm-sim/-msoft-float'
!
!

They can be combined as many times as you wish, in arbitrary ways. This list: ! 

     ..."--target_board=unix/-Wextra\{-O3,-fno-strength\}\{-fomit-frame,\}"
!
!

will generate four combinations, all involving ‘-Wextra’. ! !

The disadvantage to this method is that the testsuites are run in serial, which is a waste on multiprocessor systems. For users with GNU Make and a shell which performs brace expansion, you can run the testsuites in ! parallel by having the shell perform the combinations and make ! do the parallel runs. Instead of using ‘--target_board’, use a special makefile target: ! 

     make -jN check-testsuite//test-target/option1/option2/...
!
!

For example, ! 

     make -j3 check-gcc//sh-hms-sim/{-m1,-m2,-m3,-m3e,-m4}/{,-nofpu}
!
!

will run three concurrent “make-gcc” testsuites, eventually testing all ten combinations as described above. Note that this is currently only ! supported in the gcc subdirectory. (To see how this works, try ! typing echo before the example given here.) !

Additional testing for Java Class Libraries

!

The Java runtime tests can be executed via ‘make check’ ! in the target/libjava/testsuite directory in the build tree. ! !

The Mauve Project provides a suite of tests for the Java Class Libraries. This suite can be run as part of libgcj testing by placing the Mauve tree within the libjava ! testsuite at libjava/testsuite/libjava.mauve/mauve, or by ! specifying the location of that tree when invoking ‘make’, as in ! ‘make MAUVEDIR=~/mauve check’. !

How to interpret test results

! !

The result of running the testsuite are various *.sum and *.log ! files in the testsuite subdirectories. The *.log files contain a detailed log of the compiler invocations and the corresponding ! results, the *.sum files summarize the results. These summaries contain status codes for all tests: !

    !
  • PASS: the test passed as expected !
  • XPASS: the test unexpectedly passed !
  • FAIL: the test unexpectedly failed !
  • XFAIL: the test failed as expected !
  • UNSUPPORTED: the test is not supported on this platform !
  • ERROR: the testsuite detected an error !
  • WARNING: the testsuite detected a possible problem !
! !

It is normal for some tests to report unexpected failures. At the current time the testing harness does not allow fine grained control over whether or not a test is expected to fail. This problem should be fixed in future releases. !

Submitting test results

If you want to report the results to the GCC project, use the ! contrib/test_summary shell script. Start it in the objdir with ! 

     srcdir/contrib/test_summary -p your_commentary.txt \
!          -m gcc-testresults@gcc.gnu.org |sh
!
!

This script uses the Mail program to send the results, so ! make sure it is in your PATH. The file your_commentary.txt is prepended to the testsuite summary and should contain any special remarks you have on your results or your build environment. Please do not edit the testsuite result block or the subject line, as these messages may be automatically processed. +

+

Return to the GCC Installation page + + + + + + + + diff -Nrcpad gcc-4.8.2/LAST_UPDATED gcc-4.8.3/LAST_UPDATED *** gcc-4.8.2/LAST_UPDATED Wed Oct 16 07:27:59 2013 --- gcc-4.8.3/LAST_UPDATED Thu May 22 09:13:50 2014 *************** *** 1 **** ! Obtained from SVN: tags/gcc_4_8_2_release revision 203690 --- 1 ---- ! Obtained from SVN: tags/gcc_4_8_3_release revision 210800 diff -Nrcpad gcc-4.8.2/MD5SUMS gcc-4.8.3/MD5SUMS *** gcc-4.8.2/MD5SUMS Wed Oct 16 08:30:10 2013 --- gcc-4.8.3/MD5SUMS Thu May 22 10:36:34 2014 *************** *** 1,5 **** # This file contains the MD5 checksums of the files in the ! # gcc-4.8.2.tar.bz2 tarball. # # Besides verifying that all files in the tarball were correctly expanded, # it also can be used to determine if any files have changed since the --- 1,5 ---- # This file contains the MD5 checksums of the files in the ! # gcc-4.8.3.tar.bz2 tarball. # # Besides verifying that all files in the tarball were correctly expanded, # it also can be used to determine if any files have changed since the *************** *** 7,13 **** # # Suggested usage: # md5sum -c MD5SUMS | grep -v "OK$" ! 1340a34b2615eff0c668e888f4539b82 .gitignore 8c00452ef1e298846493ec8b239f93e2 ABOUT-NLS 59530bdf33659b29e73d4adb9f9f6552 COPYING --- 7,13 ---- # # Suggested usage: # md5sum -c MD5SUMS | grep -v "OK$" ! # 1340a34b2615eff0c668e888f4539b82 .gitignore 8c00452ef1e298846493ec8b239f93e2 ABOUT-NLS 59530bdf33659b29e73d4adb9f9f6552 COPYING *************** *** 15,44 **** fe60d87048567d4fe8c8a0ed2448bcc8 COPYING.RUNTIME d32239bcb673463ab874e80d47fae504 COPYING3 6a6a8e020838b23406c81b19c1d46df6 COPYING3.LIB ! c2eeb53662831fb4b8f57d5d14415ade ChangeLog 09538b708302f1735f6fa05b622ecf5e ChangeLog.tree-ssa 79ef16e405f5873970e04cee49091ff8 INSTALL/README ! 5702e2c21728eb13d5fbafc8820451f3 INSTALL/binaries.html ! 5bf577945064322e27c1a09068a5db39 INSTALL/build.html ! 3118c247ea89aefdceedca0891204b42 INSTALL/configure.html ! 2bb5514c2c5fe5584bda3090c91ee3a7 INSTALL/download.html ! 98ae902bd66b297e34b24bac93bb999b INSTALL/finalinstall.html ! 3b4eca14d955a9049334393fb142d70b INSTALL/gfdl.html ! 1e4538eec627577de5636e36e006d5f0 INSTALL/index.html ! f04fba7e32b5623c40555f3156644385 INSTALL/old.html ! c7c6c2d30bc9ba50366e6e2f21c533ea INSTALL/prerequisites.html ! b63b8132101c07046f24f21e2ef2a630 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2caafacabf758bb76a9dfce1fc544b97 boehm-gc/BCC_MAKEFILE ! a4967175d1b1f1bf84d483aeff581f20 boehm-gc/ChangeLog c18075e3729cd116028480307a8e845d boehm-gc/EMX_MAKEFILE 3b7cc3be9ed3c2135bbda990e8a69303 boehm-gc/MacOS.c 5cf7764626b7dd7272b2fe11403d1b6a boehm-gc/MacProjects.sit.hqx *************** ccc4e9a52aa294110431eb9aead00666 boehm- *** 68,74 **** a2ed02a22235b4f27ab644ce4f3a9268 boehm-gc/blacklst.c b19b7b67bff97d0bceba827fedb07d32 boehm-gc/callprocs 32e4857b7b4dbc4bc68e321f70f65dd4 boehm-gc/checksums.c ! 9455269d820372c27a1def271bfd45db boehm-gc/configure 142143dc0570c46cdaa2c26a9208b324 boehm-gc/configure.ac 56328341fbfbe66715779252aa61943e boehm-gc/configure.host 61ccb6486d45cc6d99201cc19f3c579c boehm-gc/cord/cordbscs.c --- 68,74 ---- a2ed02a22235b4f27ab644ce4f3a9268 boehm-gc/blacklst.c b19b7b67bff97d0bceba827fedb07d32 boehm-gc/callprocs 32e4857b7b4dbc4bc68e321f70f65dd4 boehm-gc/checksums.c ! 818ba4dc5de904ce6e9502e023178a0f boehm-gc/configure 142143dc0570c46cdaa2c26a9208b324 boehm-gc/configure.ac 56328341fbfbe66715779252aa61943e boehm-gc/configure.host 61ccb6486d45cc6d99201cc19f3c579c boehm-gc/cord/cordbscs.c *************** deb33a288bb6bee23ac46c1e0717708e boehm- *** 162,168 **** b68061acdca5298c1308c16bd0c14d3b boehm-gc/include/private/gc_locks.h 4f7c11f389c4b9cc843d53da0534fc0e boehm-gc/include/private/gc_pmark.h 770d2b9d5645f6eed368674166dfca96 boehm-gc/include/private/gc_priv.h ! b9d67bc203e6502254d4d0461ac3a978 boehm-gc/include/private/gcconfig.h 5549846c2f7dcd83f8550fd307f86c25 boehm-gc/include/private/pthread_stop_world.h c6d1a299be177e91e40ec5a8c3de616b boehm-gc/include/private/pthread_support.h a60de8578b76b4e565780c5ea9173bfc boehm-gc/include/private/specific.h --- 162,168 ---- b68061acdca5298c1308c16bd0c14d3b boehm-gc/include/private/gc_locks.h 4f7c11f389c4b9cc843d53da0534fc0e boehm-gc/include/private/gc_pmark.h 770d2b9d5645f6eed368674166dfca96 boehm-gc/include/private/gc_priv.h ! 505f3a6e48ef91c7ae74099ca247f06c boehm-gc/include/private/gcconfig.h 5549846c2f7dcd83f8550fd307f86c25 boehm-gc/include/private/pthread_stop_world.h c6d1a299be177e91e40ec5a8c3de616b boehm-gc/include/private/pthread_support.h a60de8578b76b4e565780c5ea9173bfc boehm-gc/include/private/specific.h *************** b04a1232318128ebd7c630fca10d02e5 boehm- *** 214,223 **** 507b81a9cd1207556ad38357327dbeb9 boehm-gc/win32_threads.c 0d3c238b02b9d0c1c32347dea7fc490d compile 4adca919c67d00b948bf581991b79bbf config-ml.in ! 9cd4b6d4d78c745db41c485daef7c56c config.guess 040359150cf11493f973a46d8a25b06b config.rpath ! 3cb710e658354c2f7e93ecd437c54a53 config.sub ! 7d484b5e1b8a819004ca5b9d2308a5c4 config/ChangeLog 0fcd4badfe2a2191778bdf5ab94aa40c config/acinclude.m4 9238d23c68259d195b332db71892d242 config/acx.m4 6b030f5cf640bdd401ea739f54a667f8 config/asmcfi.m4 --- 214,223 ---- 507b81a9cd1207556ad38357327dbeb9 boehm-gc/win32_threads.c 0d3c238b02b9d0c1c32347dea7fc490d compile 4adca919c67d00b948bf581991b79bbf config-ml.in ! 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gcc/config/avr/builtins.def *************** b16986d198166b6ae3ff2909d5ade5db gcc/co *** 3062,3073 **** acac0a55719bae4c1f29e52ec320e52d gcc/config/cris/cris-protos.h 9e1c52f3cb76fd0520db80091c154458 gcc/config/cris/cris.c b25d43b01c3a64089d4b56527e79ac60 gcc/config/cris/cris.h ! fceaa97634c5e8ee50b5fe5f600acdde gcc/config/cris/cris.md c154ea299cdb35ba117ff171de527cae gcc/config/cris/cris.opt 7ae7f770a36e631d19b05982519054bd gcc/config/cris/elf.opt 3d238378f5fe1c8df8c04ae847304864 gcc/config/cris/linux.h 8dc37db8287694af3be334eeca3b76b7 gcc/config/cris/linux.opt ! 4eee2207c3b8d6b038004a2b8e472c2a gcc/config/cris/predicates.md 7a374576115cdcbb648f2d6661466c50 gcc/config/cris/sync.md 9be329859b272e9b6217c99cd5e11048 gcc/config/cris/t-cris 0377d4bfc893ab7b92e464367a24e639 gcc/config/cris/t-elfmulti --- 3063,3074 ---- acac0a55719bae4c1f29e52ec320e52d gcc/config/cris/cris-protos.h 9e1c52f3cb76fd0520db80091c154458 gcc/config/cris/cris.c b25d43b01c3a64089d4b56527e79ac60 gcc/config/cris/cris.h ! 3d06aef9721736b1fac57372fa0513e8 gcc/config/cris/cris.md c154ea299cdb35ba117ff171de527cae gcc/config/cris/cris.opt 7ae7f770a36e631d19b05982519054bd gcc/config/cris/elf.opt 3d238378f5fe1c8df8c04ae847304864 gcc/config/cris/linux.h 8dc37db8287694af3be334eeca3b76b7 gcc/config/cris/linux.opt ! b8f85a5f15f5bd264e5ecf9891c2e840 gcc/config/cris/predicates.md 7a374576115cdcbb648f2d6661466c50 gcc/config/cris/sync.md 9be329859b272e9b6217c99cd5e11048 gcc/config/cris/t-cris 0377d4bfc893ab7b92e464367a24e639 gcc/config/cris/t-elfmulti *************** c606cc01ca984ed0b47214c469cb1dcf gcc/co *** 3078,3084 **** 2603254c641b884801faee6075bc20c1 gcc/config/darwin-ppc-ldouble-patch.def d3310030788b3ed1fe3acec81d41b527 gcc/config/darwin-protos.h 5e536d2b4a91688c1cbcdc2429e07780 gcc/config/darwin-sections.def ! 68c0dcffa5688a038a89a17b9857f4d0 gcc/config/darwin.c 26a2f9c449f7294a56013bf7b62c9bd3 gcc/config/darwin.h a2f9c51feaa2cd2cc16bc9db4223fe91 gcc/config/darwin.opt 4525380607e9883a09de919ef082d632 gcc/config/darwin10.h --- 3079,3085 ---- 2603254c641b884801faee6075bc20c1 gcc/config/darwin-ppc-ldouble-patch.def d3310030788b3ed1fe3acec81d41b527 gcc/config/darwin-protos.h 5e536d2b4a91688c1cbcdc2429e07780 gcc/config/darwin-sections.def ! 8f7320e96149248b7681f850804d6f52 gcc/config/darwin.c 26a2f9c449f7294a56013bf7b62c9bd3 gcc/config/darwin.h a2f9c51feaa2cd2cc16bc9db4223fe91 gcc/config/darwin.opt 4525380607e9883a09de919ef082d632 gcc/config/darwin10.h *************** c568b4759b79c17cb4d8e8d4568ef39e gcc/co *** 3186,3194 **** 4785ccfc47eaaaa7c62dbfc05f9d8b86 gcc/config/i386/djgpp-stdint.h dd1eaefa2553dd1e555c2733ef551527 gcc/config/i386/djgpp.h d1586a91e8a2175dd88e5511afe55d0e gcc/config/i386/djgpp.opt ! 13a87faf7db869b24190dadbce5f7796 gcc/config/i386/driver-i386.c fb06e2d9664a39db5db3c6c0679de0ce gcc/config/i386/emmintrin.h ! c88535fbf132c1f278c15394aef3340b gcc/config/i386/f16cintrin.h 2ba04392850cfd19dd7c92d443455ed2 gcc/config/i386/fma4intrin.h aadb69eb747a6b9a98e674121ea755d1 gcc/config/i386/fmaintrin.h cd09d0f29fb9a36bfada4b5e277d7e1e gcc/config/i386/freebsd.h --- 3187,3195 ---- 4785ccfc47eaaaa7c62dbfc05f9d8b86 gcc/config/i386/djgpp-stdint.h dd1eaefa2553dd1e555c2733ef551527 gcc/config/i386/djgpp.h d1586a91e8a2175dd88e5511afe55d0e gcc/config/i386/djgpp.opt ! 5853e26330fed17895b66ddbd24e16a5 gcc/config/i386/driver-i386.c fb06e2d9664a39db5db3c6c0679de0ce gcc/config/i386/emmintrin.h ! 8203f3ff24f2449720ad7f3511355689 gcc/config/i386/f16cintrin.h 2ba04392850cfd19dd7c92d443455ed2 gcc/config/i386/fma4intrin.h aadb69eb747a6b9a98e674121ea755d1 gcc/config/i386/fmaintrin.h cd09d0f29fb9a36bfada4b5e277d7e1e gcc/config/i386/freebsd.h *************** be3b23219ebac7970d1f9b1d5f82e4de gcc/co *** 3212,3220 **** 2ba789f83c27d255333f01d514c1592f gcc/config/i386/i386-modes.def 00be754e0e6424cf60e02acf796f5819 gcc/config/i386/i386-opts.h e68f96b9008364ea0d5eabe9de379b54 gcc/config/i386/i386-protos.h ! 6b15923536cf29692d0c02c1f7715e56 gcc/config/i386/i386.c ! 5d7fdc81fdfd7ebcb48f93872a3cd80b gcc/config/i386/i386.h ! fab075e6624539644c091d9d2a2d77d6 gcc/config/i386/i386.md b7e49bcb9fea7b61eab73988a17ee919 gcc/config/i386/i386.opt 58bbfa9b8ce4fd4126c4ab71d0bd9476 gcc/config/i386/i386elf.h 155007e2bb73902c958d03bbebf517ce gcc/config/i386/ia32intrin.h --- 3213,3221 ---- 2ba789f83c27d255333f01d514c1592f gcc/config/i386/i386-modes.def 00be754e0e6424cf60e02acf796f5819 gcc/config/i386/i386-opts.h e68f96b9008364ea0d5eabe9de379b54 gcc/config/i386/i386-protos.h ! 5f6c712512dc22173a93cdffb3e61050 gcc/config/i386/i386.c ! 25843c182210819f1d2167e7b98b3ead gcc/config/i386/i386.h ! bf06bd34cd2289e3d8a6548083a71c3b gcc/config/i386/i386.md b7e49bcb9fea7b61eab73988a17ee919 gcc/config/i386/i386.opt 58bbfa9b8ce4fd4126c4ab71d0bd9476 gcc/config/i386/i386elf.h 155007e2bb73902c958d03bbebf517ce gcc/config/i386/ia32intrin.h *************** d6d0b9740afd348fc7288a251b6c7ecb gcc/co *** 3263,3269 **** c7dbf91cae1df04f0c69d17bdb9eb739 gcc/config/i386/smmintrin.h 356c9d5cf06fc52a905dc4ba4b8d1dd1 gcc/config/i386/sol2-bi.h a0c6c5a1327e7aa2252656a0bd72921a gcc/config/i386/sol2.h ! 52497d401e248e7cee306ee81319fc2a gcc/config/i386/sse.md 133ed82593d2dcb4ebd649ccae429e2f gcc/config/i386/ssemath.h 779935bb416cf8724ffb3fa38dc4459b gcc/config/i386/sync.md 6c77cea4e52de21183c1ef931d6fce32 gcc/config/i386/sysv4.h --- 3264,3270 ---- c7dbf91cae1df04f0c69d17bdb9eb739 gcc/config/i386/smmintrin.h 356c9d5cf06fc52a905dc4ba4b8d1dd1 gcc/config/i386/sol2-bi.h a0c6c5a1327e7aa2252656a0bd72921a gcc/config/i386/sol2.h ! 147fe75f4ddba9c2fd3387f9dad4fc74 gcc/config/i386/sse.md 133ed82593d2dcb4ebd649ccae429e2f gcc/config/i386/ssemath.h 779935bb416cf8724ffb3fa38dc4459b gcc/config/i386/sync.md 6c77cea4e52de21183c1ef931d6fce32 gcc/config/i386/sysv4.h *************** cd662e746e08a18749e8272fa759278e gcc/co *** 3281,3287 **** 67bcf41f125bbec93a13ad3bd98abaee gcc/config/i386/t-mingw-w64 813c980909a4848e5aed5faeca6fe2bd gcc/config/i386/t-openbsd 12a68576d3577a8da82089f18d60c613 gcc/config/i386/t-pmm_malloc ! f38be182f71917b73561a90a02be3b48 gcc/config/i386/t-rtems 5caaadac91232f1132b9eda067d2ed21 gcc/config/i386/t-sol2-64 af24a4211ecc5bef39097e175d346788 gcc/config/i386/t-vxworks b80a5a4a8c8fc32ca318158abc98dc20 gcc/config/i386/t-vxworksae --- 3282,3288 ---- 67bcf41f125bbec93a13ad3bd98abaee gcc/config/i386/t-mingw-w64 813c980909a4848e5aed5faeca6fe2bd gcc/config/i386/t-openbsd 12a68576d3577a8da82089f18d60c613 gcc/config/i386/t-pmm_malloc ! b00d2c1b3a5cb385706cd1ba330452f7 gcc/config/i386/t-rtems 5caaadac91232f1132b9eda067d2ed21 gcc/config/i386/t-sol2-64 af24a4211ecc5bef39097e175d346788 gcc/config/i386/t-vxworks b80a5a4a8c8fc32ca318158abc98dc20 gcc/config/i386/t-vxworksae *************** a883796a6a71f16f70589a90c24fe01a gcc/co *** 3293,3299 **** 81192abfa622aa58e7fd2fa476520751 gcc/config/i386/vxworksae.h ac803092fce09cef5f39fbf0bd1ee56d gcc/config/i386/winnt-cxx.c 4264fba32264f2088d4573a3628209eb gcc/config/i386/winnt-stubs.c ! 8f479412e4c144166c5d0ebbe36848e5 gcc/config/i386/winnt.c 2c7e3fdc55a855f8ddfe352fa1fe4354 gcc/config/i386/wmmintrin.h 627c3e925a142fb6d2a14368fb637f28 gcc/config/i386/x-cygwin 58a984112f85a94b6be59817a4c57d48 gcc/config/i386/x-darwin --- 3294,3300 ---- 81192abfa622aa58e7fd2fa476520751 gcc/config/i386/vxworksae.h ac803092fce09cef5f39fbf0bd1ee56d gcc/config/i386/winnt-cxx.c 4264fba32264f2088d4573a3628209eb gcc/config/i386/winnt-stubs.c ! 2dedc478d4c5940e569c8424424d3634 gcc/config/i386/winnt.c 2c7e3fdc55a855f8ddfe352fa1fe4354 gcc/config/i386/wmmintrin.h 627c3e925a142fb6d2a14368fb637f28 gcc/config/i386/x-cygwin 58a984112f85a94b6be59817a4c57d48 gcc/config/i386/x-darwin *************** ac803092fce09cef5f39fbf0bd1ee56d gcc/co *** 3305,3311 **** 3685fb0714327699396f20c9a0fbbd83 gcc/config/i386/xm-djgpp.h 718bd13fe9636803ee1b1caf5c8acf00 gcc/config/i386/xm-mingw32.h 05355c40ad0c4f0c8d712ba10f192197 gcc/config/i386/xmmintrin.h ! e472d3e7d17c23e2701763c9d4162396 gcc/config/i386/xopintrin.h d83f66040bd1c13b082f5ea32679ee0f gcc/config/i386/xsaveintrin.h 53bed82e6204286a81d8ef4e955671b6 gcc/config/i386/xsaveoptintrin.h bc50ddbe10ecf319da222ffa4865a1ca gcc/config/i386/xtestintrin.h --- 3306,3312 ---- 3685fb0714327699396f20c9a0fbbd83 gcc/config/i386/xm-djgpp.h 718bd13fe9636803ee1b1caf5c8acf00 gcc/config/i386/xm-mingw32.h 05355c40ad0c4f0c8d712ba10f192197 gcc/config/i386/xmmintrin.h ! 981c21fc07009a451cbc8570b5cdf2b4 gcc/config/i386/xopintrin.h d83f66040bd1c13b082f5ea32679ee0f gcc/config/i386/xsaveintrin.h 53bed82e6204286a81d8ef4e955671b6 gcc/config/i386/xsaveoptintrin.h bc50ddbe10ecf319da222ffa4865a1ca gcc/config/i386/xtestintrin.h *************** bff081c2e48aafde8a9457ddef6e58e7 gcc/co *** 3415,3421 **** 193b5d9804ffc73434f71a4c9f7194ba gcc/config/m68k/m68k-opts.h 4b0d5954a15f19b6177fed0e997a897b gcc/config/m68k/m68k-protos.h b0e6f80caec611c986a6e6f37b7b42ab gcc/config/m68k/m68k-tables.opt ! d856111de28972caead193456a40c8ab gcc/config/m68k/m68k.c edb1453ecb1a2be7107d27b300641599 gcc/config/m68k/m68k.h ee19da648459674f9a8016d1420b1372 gcc/config/m68k/m68k.md fc4a372d659d121ec6365516ecd21a91 gcc/config/m68k/m68k.opt --- 3416,3422 ---- 193b5d9804ffc73434f71a4c9f7194ba gcc/config/m68k/m68k-opts.h 4b0d5954a15f19b6177fed0e997a897b gcc/config/m68k/m68k-protos.h b0e6f80caec611c986a6e6f37b7b42ab gcc/config/m68k/m68k-tables.opt ! 298d13253b444580b26d950f26618d02 gcc/config/m68k/m68k.c edb1453ecb1a2be7107d27b300641599 gcc/config/m68k/m68k.h ee19da648459674f9a8016d1420b1372 gcc/config/m68k/m68k.md fc4a372d659d121ec6365516ecd21a91 gcc/config/m68k/m68k.opt *************** a21124435021085ec6e511d258f9c6db gcc/co *** 3472,3482 **** e9a9df0e98a2a744bbc2fc01e1c8535f gcc/config/microblaze/linux.h 8bd33a6b733edfe38b314f85fc45dde7 gcc/config/microblaze/microblaze-c.c 67f74479946bf6e946698e0c56c2f4ce gcc/config/microblaze/microblaze-protos.h ! cbdb60d1e1fb2d69cfd62e4fbdee7cb3 gcc/config/microblaze/microblaze.c ! 43b034509ede51ebd060aa5017202681 gcc/config/microblaze/microblaze.h ! a1a3072d5557c848d2341e9ffd16f55c gcc/config/microblaze/microblaze.md 4ed279d05619ce925a8de2d57c6a7207 gcc/config/microblaze/microblaze.opt ! 060eefecceb2cf8901fc929100f90230 gcc/config/microblaze/predicates.md 5e45a221d83a64728ff2bd46743c631b gcc/config/microblaze/rtems.h 17818a25ae3112098cd91d698e37f0f7 gcc/config/microblaze/t-microblaze 63ccba4e7f745d36609d7c129bac6288 gcc/config/microblaze/t-microblaze-linux --- 3473,3483 ---- e9a9df0e98a2a744bbc2fc01e1c8535f gcc/config/microblaze/linux.h 8bd33a6b733edfe38b314f85fc45dde7 gcc/config/microblaze/microblaze-c.c 67f74479946bf6e946698e0c56c2f4ce gcc/config/microblaze/microblaze-protos.h ! 78e0400bc62a472b13a23781fc2a1fcc gcc/config/microblaze/microblaze.c ! 5324229be892e782b8c75ce2176906d0 gcc/config/microblaze/microblaze.h ! 2d43c56bbf52358a37e9c7bd1e8316bf gcc/config/microblaze/microblaze.md 4ed279d05619ce925a8de2d57c6a7207 gcc/config/microblaze/microblaze.opt ! 7167298b8adb1d13f25c51ad8e464bb1 gcc/config/microblaze/predicates.md 5e45a221d83a64728ff2bd46743c631b gcc/config/microblaze/rtems.h 17818a25ae3112098cd91d698e37f0f7 gcc/config/microblaze/t-microblaze 63ccba4e7f745d36609d7c129bac6288 gcc/config/microblaze/t-microblaze-linux *************** e93bfde35bb7b6efdf5cbcc267c70a91 gcc/co *** 3500,3506 **** 0d29345530e843294cabaa328bfb9e6e gcc/config/mips/74k.md 9ed8ece6c42743c43ec26c2ac7db6650 gcc/config/mips/9000.md 2543d141c10f176375bc4ee5ac2f54d4 gcc/config/mips/constraints.md ! 069ede8acb9aac9d6bb6a2bb943eaa3a gcc/config/mips/driver-native.c de39c31281151a929212cec4dc286d8c gcc/config/mips/elf.h 950ddf382880576f284ccf64fe30e6c9 gcc/config/mips/elfoabi.h f1231bbf2e6eee613b0791cdff5a8697 gcc/config/mips/elforion.h --- 3501,3507 ---- 0d29345530e843294cabaa328bfb9e6e gcc/config/mips/74k.md 9ed8ece6c42743c43ec26c2ac7db6650 gcc/config/mips/9000.md 2543d141c10f176375bc4ee5ac2f54d4 gcc/config/mips/constraints.md ! 68d71ddeb1c8fdeaa478724c17f1159b gcc/config/mips/driver-native.c de39c31281151a929212cec4dc286d8c gcc/config/mips/elf.h 950ddf382880576f284ccf64fe30e6c9 gcc/config/mips/elfoabi.h f1231bbf2e6eee613b0791cdff5a8697 gcc/config/mips/elforion.h *************** cf30f1fae4d8ba91de7729b46e7d296d gcc/co *** 3526,3534 **** ffcf73d9f64036b802fa047155289fac gcc/config/mips/mips-protos.h 56e4e147e889863e96add52a8170521a gcc/config/mips/mips-ps-3d.md 3dbb845857ce3922656be599dd8b9441 gcc/config/mips/mips-tables.opt ! f85efba5ec6000d796d1d088d8455372 gcc/config/mips/mips.c ! f3f37ddb5d704ccd136eb331cb54c805 gcc/config/mips/mips.h ! b30960462ef573c18271e500df60bffb gcc/config/mips/mips.md baeea74917c42edc6a00aea5aae0c311 gcc/config/mips/mips.opt a37e38e49611bd674168dcff6aea0739 gcc/config/mips/mti-elf.h 253f6b24866b248b2f8ce9ea8c056926 gcc/config/mips/mti-linux.h --- 3527,3535 ---- ffcf73d9f64036b802fa047155289fac gcc/config/mips/mips-protos.h 56e4e147e889863e96add52a8170521a gcc/config/mips/mips-ps-3d.md 3dbb845857ce3922656be599dd8b9441 gcc/config/mips/mips-tables.opt ! fefcc939519aa672bb77bc51a7ebbdc0 gcc/config/mips/mips.c ! 48e81ea61d0e87f81217b3d8b47f07a6 gcc/config/mips/mips.h ! 2e034c3c1126402726843dc511d82545 gcc/config/mips/mips.md baeea74917c42edc6a00aea5aae0c311 gcc/config/mips/mips.opt a37e38e49611bd674168dcff6aea0739 gcc/config/mips/mti-elf.h 253f6b24866b248b2f8ce9ea8c056926 gcc/config/mips/mti-linux.h *************** f6ece491057229f3a7db89a70039abbd gcc/co *** 3624,3631 **** 134a862333cd36aa9be58272c66ef672 gcc/config/pa/pa-openbsd.h 03fdc2c22864cbd070b6e87110142e0d gcc/config/pa/pa-opts.h e2fc4a1737dbed493a8abc267b7764c4 gcc/config/pa/pa-protos.h ! 05ee13c14a9fc7c69630704a72025755 gcc/config/pa/pa.c ! aac106ded96613868c7b978f31ba4146 gcc/config/pa/pa.h 1e689ba950a9dcff7946d1a638aa0897 gcc/config/pa/pa.md 4da312d74afa896f8ad580f2d13c7995 gcc/config/pa/pa.opt 307965ddc82931797f2c18d014fd9545 gcc/config/pa/pa32-linux.h --- 3625,3632 ---- 134a862333cd36aa9be58272c66ef672 gcc/config/pa/pa-openbsd.h 03fdc2c22864cbd070b6e87110142e0d gcc/config/pa/pa-opts.h e2fc4a1737dbed493a8abc267b7764c4 gcc/config/pa/pa-protos.h ! 4d65aeac4e9db1afbed772a747e6ab08 gcc/config/pa/pa.c ! 5a887ec04d19d55393e82b9ebb978973 gcc/config/pa/pa.h 1e689ba950a9dcff7946d1a638aa0897 gcc/config/pa/pa.md 4da312d74afa896f8ad580f2d13c7995 gcc/config/pa/pa.opt 307965ddc82931797f2c18d014fd9545 gcc/config/pa/pa32-linux.h *************** c3cc007b9d4d1bc1257a4579ff4b6a30 gcc/co *** 3695,3713 **** 7039c7de191d6589f7467fb9541e94d1 gcc/config/rs6000/aix53.h c74d992c22cd4c77eef6467bffb151b2 gcc/config/rs6000/aix61.h 08c5560a95c96722616c024a02b45015 gcc/config/rs6000/aix64.opt ! 64c94f078cc748e550d37246b7bf9883 gcc/config/rs6000/altivec.h ! bf329217f37e5dc3c5e54d7f9e782f2e gcc/config/rs6000/altivec.md 88fc51fa326caf24fe73a92078ff985c gcc/config/rs6000/biarch64.h 817c296ec0ab30ac42b9b7fb3bead44d gcc/config/rs6000/cell.md ! bfe3112e1e2013f04d3a8b82c5746919 gcc/config/rs6000/constraints.md ! 9b7ea4fad8c2d5410c9a9fbe112d8fe7 gcc/config/rs6000/darwin.h 6f3698b10847c1e351f178071c387fc4 gcc/config/rs6000/darwin.md 25a9ba5371a7d5a4922f66b90309f78b gcc/config/rs6000/darwin.opt de1e58e023126d18861ecd6bf950be44 gcc/config/rs6000/darwin64.h 274a1a4679ee4d763744361d947515d0 gcc/config/rs6000/darwin7.h 502c371891710ae9a4526980a5d99ab7 gcc/config/rs6000/darwin8.h 1ba3379bafb9241886a65a9413900250 gcc/config/rs6000/default64.h ! aa49932c10047c9e55094e79e082393d gcc/config/rs6000/dfp.md 518da3fd76509f1214bf541cd37fa721 gcc/config/rs6000/driver-rs6000.c 647c9512f8e2b1e7b9aaaa0bcfbe8eba gcc/config/rs6000/e300c2c3.md 20c280571996373aeda564375e7b8c6b gcc/config/rs6000/e500.h --- 3696,3715 ---- 7039c7de191d6589f7467fb9541e94d1 gcc/config/rs6000/aix53.h c74d992c22cd4c77eef6467bffb151b2 gcc/config/rs6000/aix61.h 08c5560a95c96722616c024a02b45015 gcc/config/rs6000/aix64.opt ! fee5ba9f209f8817e17ac181a132fc39 gcc/config/rs6000/altivec.h ! df154a26bc13f5952eb448af335773ea gcc/config/rs6000/altivec.md 88fc51fa326caf24fe73a92078ff985c gcc/config/rs6000/biarch64.h 817c296ec0ab30ac42b9b7fb3bead44d gcc/config/rs6000/cell.md ! 7fdf76ee77bc5eb2bb723c6c8c31aed9 gcc/config/rs6000/constraints.md ! aacbcedb1a719159dcfa8ebf6b1a4c79 gcc/config/rs6000/crypto.md ! 59ce100a248546e3a70cb997be057efc gcc/config/rs6000/darwin.h 6f3698b10847c1e351f178071c387fc4 gcc/config/rs6000/darwin.md 25a9ba5371a7d5a4922f66b90309f78b gcc/config/rs6000/darwin.opt de1e58e023126d18861ecd6bf950be44 gcc/config/rs6000/darwin64.h 274a1a4679ee4d763744361d947515d0 gcc/config/rs6000/darwin7.h 502c371891710ae9a4526980a5d99ab7 gcc/config/rs6000/darwin8.h 1ba3379bafb9241886a65a9413900250 gcc/config/rs6000/default64.h ! 78e6d68d65c3ad282401ee5f76745774 gcc/config/rs6000/dfp.md 518da3fd76509f1214bf541cd37fa721 gcc/config/rs6000/driver-rs6000.c 647c9512f8e2b1e7b9aaaa0bcfbe8eba gcc/config/rs6000/e300c2c3.md 20c280571996373aeda564375e7b8c6b gcc/config/rs6000/e500.h *************** c9164c6d1f0780efca921dd6473e896a gcc/co *** 3724,3731 **** 2dd91d7170e843afa16ce9773a0402f9 gcc/config/rs6000/genopt.sh 2d6e470d61d40f02ed935702b8656702 gcc/config/rs6000/host-darwin.c 15da2c30dd5e1822354f016081aa22f1 gcc/config/rs6000/host-ppc64-darwin.c 4737b441859039ee14ec15323413eccd gcc/config/rs6000/linux.h ! 135b9781f17fdf76b3c025759afd0763 gcc/config/rs6000/linux64.h 8234299aeb4439357d76de9db97babad gcc/config/rs6000/linux64.opt c050ce5476e06a291aa23a8cdd84935b gcc/config/rs6000/linuxaltivec.h 67560fa80452cf101107f94c34a67013 gcc/config/rs6000/linuxspe.h --- 3726,3736 ---- 2dd91d7170e843afa16ce9773a0402f9 gcc/config/rs6000/genopt.sh 2d6e470d61d40f02ed935702b8656702 gcc/config/rs6000/host-darwin.c 15da2c30dd5e1822354f016081aa22f1 gcc/config/rs6000/host-ppc64-darwin.c + d081d7afc70df0ef42c0d6e65217b125 gcc/config/rs6000/htm.md + cb085d898b2542e95e63a04f2061284f gcc/config/rs6000/htmintrin.h + 0c9088bc4c7e9448dfb659d06c8f9be2 gcc/config/rs6000/htmxlintrin.h 4737b441859039ee14ec15323413eccd gcc/config/rs6000/linux.h ! f6c28b43569c4fafb93f1ddad72dd917 gcc/config/rs6000/linux64.h 8234299aeb4439357d76de9db97babad gcc/config/rs6000/linux64.opt c050ce5476e06a291aa23a8cdd84935b gcc/config/rs6000/linuxaltivec.h 67560fa80452cf101107f94c34a67013 gcc/config/rs6000/linuxspe.h *************** ca1700694d7046be612275378c4200e5 gcc/co *** 3733,3759 **** 0cc3c5f9101501b8253ce3176c3ffce4 gcc/config/rs6000/milli.exp b129a9ba5a810466224e0a535b3198a7 gcc/config/rs6000/mpc.md 426e58886d784136c8d6c7f607bd9595 gcc/config/rs6000/netbsd.h ! 0258c6636e58ef31dfc50cd09ccd05c4 gcc/config/rs6000/option-defaults.h 95b063713d06e8f125af283a10770ed0 gcc/config/rs6000/paired.h b82a620cefdb9cf11c7b9141d3fab251 gcc/config/rs6000/paired.md 413c20b1e1c3fe973f3bbf2a33503a74 gcc/config/rs6000/power4.md 0dca1d8d6f56bcc8e84e40145cc8977e gcc/config/rs6000/power5.md fe39ced9a340b2083ec767453b517ce3 gcc/config/rs6000/power6.md ffc3754101a9853c46e39826585bc448 gcc/config/rs6000/power7.md ! aeb3fafb226082ace5572c5a6bc2c12f gcc/config/rs6000/ppc-asm.h 47e26b4e2997e1eb1fa323fb7f83cb35 gcc/config/rs6000/ppu_intrinsics.h ! d30b2099e564babfca0211dae4442b29 gcc/config/rs6000/predicates.md ! 8d935aff549ffe3c866f9dcfa9d9a276 gcc/config/rs6000/rs6000-builtin.def ! fd14a2221437963677c27841ec0dd8d8 gcc/config/rs6000/rs6000-c.c ! 9675b0b5128d596388c45798ff833082 gcc/config/rs6000/rs6000-cpus.def ! 54330971ce8f62b47f68f31d153478c4 gcc/config/rs6000/rs6000-modes.def ! da00f6c375e270a80467643901085b7a gcc/config/rs6000/rs6000-opts.h ! 8f6568fd06b952b2aebd50c12ded676e gcc/config/rs6000/rs6000-protos.h 3d464892d4463d95ff027607410640cb gcc/config/rs6000/rs6000-tables.opt ! 4193ef7063f16e67fa7ad1b7c19728ee gcc/config/rs6000/rs6000.c ! 7be233a5f94f3dc0572dde43efdbf221 gcc/config/rs6000/rs6000.h ! 0bb472c9e7c6d3dd18fc2c4a52f7792c gcc/config/rs6000/rs6000.md ! e6e84f1bc31399685617cf4a1a97e37e gcc/config/rs6000/rs6000.opt e1d48528802143c9fde5076eb841eea6 gcc/config/rs6000/rs64.md cffe153c5a922082f3e53a9f72f76cf0 gcc/config/rs6000/rtems.h 053e158620d93e03e5cca4dfb9fdb5c7 gcc/config/rs6000/secureplt.h --- 3738,3765 ---- 0cc3c5f9101501b8253ce3176c3ffce4 gcc/config/rs6000/milli.exp b129a9ba5a810466224e0a535b3198a7 gcc/config/rs6000/mpc.md 426e58886d784136c8d6c7f607bd9595 gcc/config/rs6000/netbsd.h ! d54bbc7ae5087ecf83d520cef66eca92 gcc/config/rs6000/option-defaults.h 95b063713d06e8f125af283a10770ed0 gcc/config/rs6000/paired.h b82a620cefdb9cf11c7b9141d3fab251 gcc/config/rs6000/paired.md 413c20b1e1c3fe973f3bbf2a33503a74 gcc/config/rs6000/power4.md 0dca1d8d6f56bcc8e84e40145cc8977e gcc/config/rs6000/power5.md fe39ced9a340b2083ec767453b517ce3 gcc/config/rs6000/power6.md ffc3754101a9853c46e39826585bc448 gcc/config/rs6000/power7.md ! 478c3c4338191d71972ab2f7bde1f421 gcc/config/rs6000/power8.md ! 8a5505035f44eb07bbc9e05702e37d3e gcc/config/rs6000/ppc-asm.h 47e26b4e2997e1eb1fa323fb7f83cb35 gcc/config/rs6000/ppu_intrinsics.h ! a1ef868a4b4f4023ca201a99efa4034f gcc/config/rs6000/predicates.md ! 2a81ede6340a9badead8d2ced3c0ea5d gcc/config/rs6000/rs6000-builtin.def ! 4682f2c7e1614d72e05f7b669ea9689d gcc/config/rs6000/rs6000-c.c ! c5bdbffe6aa3ff8c4c116c21f46a06a2 gcc/config/rs6000/rs6000-cpus.def ! c6b59ba16925d7ffdc7796dfeb8854e2 gcc/config/rs6000/rs6000-modes.def ! 33f78371b44ec32ce0515476e9e5875e gcc/config/rs6000/rs6000-opts.h ! 66c1c3ecaa0fa52af799c62a772ed12d gcc/config/rs6000/rs6000-protos.h 3d464892d4463d95ff027607410640cb gcc/config/rs6000/rs6000-tables.opt ! 7a5048de1f305f71c320d32d5e03337f gcc/config/rs6000/rs6000.c ! 4e3ca38b4127c51c5f1e79c37b245404 gcc/config/rs6000/rs6000.h ! 04fd9cffec5d547c9269934578d1f2c6 gcc/config/rs6000/rs6000.md ! 0371f2a1342d3fcb5d6215ac34bdc155 gcc/config/rs6000/rs6000.opt e1d48528802143c9fde5076eb841eea6 gcc/config/rs6000/rs64.md cffe153c5a922082f3e53a9f72f76cf0 gcc/config/rs6000/rtems.h 053e158620d93e03e5cca4dfb9fdb5c7 gcc/config/rs6000/secureplt.h *************** d41abb901c584de2a35db0a208e96360 gcc/co *** 3762,3771 **** 03636ed5c6dcefbc165211cb0cefb0e7 gcc/config/rs6000/spe.h 899ac44192250defa16c95d920330158 gcc/config/rs6000/spe.md 11b78241f26ad456c4c24d2e301d6cae gcc/config/rs6000/spu2vmx.h ! 49f419bf96b5c0f1eefbaa88b9f0bf68 gcc/config/rs6000/sync.md ! b7b731f89b911c70249b4727833bbc22 gcc/config/rs6000/sysv4.h 1a2f919a3dce90c9bd0c032097e9c929 gcc/config/rs6000/sysv4.opt ! 6e8dceb30250da47780ede6ed5ff1caf gcc/config/rs6000/sysv4le.h a487a9ff3cef979e51c91d36df02ae31 gcc/config/rs6000/t-aix43 302e3b21256a57e0053542a3bf992006 gcc/config/rs6000/t-aix52 f3250b9720d1149346f1ef8e21b52ea9 gcc/config/rs6000/t-darwin64 --- 3768,3777 ---- 03636ed5c6dcefbc165211cb0cefb0e7 gcc/config/rs6000/spe.h 899ac44192250defa16c95d920330158 gcc/config/rs6000/spe.md 11b78241f26ad456c4c24d2e301d6cae gcc/config/rs6000/spu2vmx.h ! 9fe56a1b3a317020951bd2e0794de7b6 gcc/config/rs6000/sync.md ! 48d27b8a272993fe2c66592eff01cc5c gcc/config/rs6000/sysv4.h 1a2f919a3dce90c9bd0c032097e9c929 gcc/config/rs6000/sysv4.opt ! 32ee71c067eb6d9cf41f1dc855948d44 gcc/config/rs6000/sysv4le.h a487a9ff3cef979e51c91d36df02ae31 gcc/config/rs6000/t-aix43 302e3b21256a57e0053542a3bf992006 gcc/config/rs6000/t-aix52 f3250b9720d1149346f1ef8e21b52ea9 gcc/config/rs6000/t-darwin64 *************** f3250b9720d1149346f1ef8e21b52ea9 gcc/co *** 3773,3786 **** 24d9232649e7e5455be729d3c232a9df gcc/config/rs6000/t-fprules ccad11982467f2d70b841bec7efd2f67 gcc/config/rs6000/t-freebsd64 4b73ff6971b1c8fbbe683358e74e1991 gcc/config/rs6000/t-linux ! 328dd4b8c3f86335d8d594079c79f220 gcc/config/rs6000/t-linux64 58ac6a560d7101a7c69616edc41677e8 gcc/config/rs6000/t-lynx 33bb6ce3044f98e729ce9eab1ce18242 gcc/config/rs6000/t-netbsd cd75d3393ef7ce491f9639d531ebc962 gcc/config/rs6000/t-ppccomm a01d22497a6dfaf19f1b51c7051b913d gcc/config/rs6000/t-ppcendian 998ff807301c8f5c9a99eca62a2d0db5 gcc/config/rs6000/t-ppcgas 1b8aba690a39464c4ea9c647d73d6983 gcc/config/rs6000/t-ppcos ! 9685261ed8eac071cd8c5ed265415a3f gcc/config/rs6000/t-rs6000 15f67be5f7dde11d1fe83ad15ced4faf gcc/config/rs6000/t-rtems 3876c4ad6239f10d9f17b7b34228981e gcc/config/rs6000/t-spe ceba16be300b12ac9ad7f7921506443a gcc/config/rs6000/t-vxworks --- 3779,3795 ---- 24d9232649e7e5455be729d3c232a9df gcc/config/rs6000/t-fprules ccad11982467f2d70b841bec7efd2f67 gcc/config/rs6000/t-freebsd64 4b73ff6971b1c8fbbe683358e74e1991 gcc/config/rs6000/t-linux ! 537890d1fe6a6e86f5b8a121fe01f4b9 gcc/config/rs6000/t-linux64 ! 71c0a0470047f0171a3bb4c483eb2b72 gcc/config/rs6000/t-linux64bele ! 489699b655594f05bae0b429fd261edb gcc/config/rs6000/t-linux64le ! 60f26523152f6a061a12cb17e987de12 gcc/config/rs6000/t-linux64lebe 58ac6a560d7101a7c69616edc41677e8 gcc/config/rs6000/t-lynx 33bb6ce3044f98e729ce9eab1ce18242 gcc/config/rs6000/t-netbsd cd75d3393ef7ce491f9639d531ebc962 gcc/config/rs6000/t-ppccomm a01d22497a6dfaf19f1b51c7051b913d gcc/config/rs6000/t-ppcendian 998ff807301c8f5c9a99eca62a2d0db5 gcc/config/rs6000/t-ppcgas 1b8aba690a39464c4ea9c647d73d6983 gcc/config/rs6000/t-ppcos ! 0612b5d2e65e131061de927d8c2d7dba gcc/config/rs6000/t-rs6000 15f67be5f7dde11d1fe83ad15ced4faf gcc/config/rs6000/t-rtems 3876c4ad6239f10d9f17b7b34228981e gcc/config/rs6000/t-spe ceba16be300b12ac9ad7f7921506443a gcc/config/rs6000/t-vxworks *************** f11925c88524d2fd457bf77944da1302 gcc/co *** 3788,3795 **** 1a8b6df4282e327608b394813a85fc7b gcc/config/rs6000/t-xilinx 937c4bf81c7314b8fbbaf1b02d8f6905 gcc/config/rs6000/titan.md 0455ba4aa9ce1d9f7175cbbaf86d5837 gcc/config/rs6000/vec_types.h ! 95f4ce10f19d8a92b487d874ac0384be gcc/config/rs6000/vector.md ! be55af772bc642c7a5f199c58d9ba382 gcc/config/rs6000/vsx.md 55ee4632428151775a486a916c1aff61 gcc/config/rs6000/vxworks.h 5c2f724024335c015d76fe32d3da6de9 gcc/config/rs6000/x-aix e6e0b24a5b8f8228e16c465d96dc1003 gcc/config/rs6000/x-darwin --- 3797,3804 ---- 1a8b6df4282e327608b394813a85fc7b gcc/config/rs6000/t-xilinx 937c4bf81c7314b8fbbaf1b02d8f6905 gcc/config/rs6000/titan.md 0455ba4aa9ce1d9f7175cbbaf86d5837 gcc/config/rs6000/vec_types.h ! 623a9d751ace9788bd3875a6e89b5fd6 gcc/config/rs6000/vector.md ! a7cffa7d81fba77070f2b78a3d016907 gcc/config/rs6000/vsx.md 55ee4632428151775a486a916c1aff61 gcc/config/rs6000/vxworks.h 5c2f724024335c015d76fe32d3da6de9 gcc/config/rs6000/x-aix e6e0b24a5b8f8228e16c465d96dc1003 gcc/config/rs6000/x-darwin *************** fb146efd086d9001c0d468a92e9f03ee gcc/co *** 3820,3835 **** 2162edbc9ce1aea7e5dd777928f486ff gcc/config/s390/2827.md aad75e9cfee7b4a3ae7452e8321e3ecf gcc/config/s390/constraints.md 70904ee44e0e3149fa54d9adb8f7ada6 gcc/config/s390/htmintrin.h ! dfc9851f6abd0415adb8857f29e7a462 gcc/config/s390/htmxlintrin.h 92a52bb44cb2ebf7e6fb7c8dea5af752 gcc/config/s390/linux.h 6d4923ef6a6131547fce4df327193407 gcc/config/s390/predicates.md 90bd21ef575e0643d65569d1a4f9aad9 gcc/config/s390/s390-modes.def 609500eb4414e9e848d3804134bfa79e gcc/config/s390/s390-opts.h ! d8aa92406ebc55249f2b8a00785f318a gcc/config/s390/s390-protos.h ! 048044ccfbc8a81feab6b0a57b37ba69 gcc/config/s390/s390.c ! 01afd5c43ece4c467203727c3f1cb6bc gcc/config/s390/s390.h ! f778fea72386d9dc1e51a21816c8cd92 gcc/config/s390/s390.md ! d0816bab7ca11354dc110095c5fb3077 gcc/config/s390/s390.opt a6413643c6a352ed2a285f593cc2f96d gcc/config/s390/s390intrin.h 1f405766a3e2d465229b0197ef1a6107 gcc/config/s390/s390x.h 551847ee4c38fa1a7e95fd93cdb32f17 gcc/config/s390/t-linux64 --- 3829,3844 ---- 2162edbc9ce1aea7e5dd777928f486ff gcc/config/s390/2827.md aad75e9cfee7b4a3ae7452e8321e3ecf gcc/config/s390/constraints.md 70904ee44e0e3149fa54d9adb8f7ada6 gcc/config/s390/htmintrin.h ! 797f6696543598b5c94e1c4422794cb9 gcc/config/s390/htmxlintrin.h 92a52bb44cb2ebf7e6fb7c8dea5af752 gcc/config/s390/linux.h 6d4923ef6a6131547fce4df327193407 gcc/config/s390/predicates.md 90bd21ef575e0643d65569d1a4f9aad9 gcc/config/s390/s390-modes.def 609500eb4414e9e848d3804134bfa79e gcc/config/s390/s390-opts.h ! f8f19a8c18a096764d26229eeae665ae gcc/config/s390/s390-protos.h ! 1248fec075015cf9a3639618bd335dac gcc/config/s390/s390.c ! 5b6bf091210451b5008a27d870abaf47 gcc/config/s390/s390.h ! 610ff5cffe636515f9461422f0a13bd8 gcc/config/s390/s390.md ! 237b28c4996f7ed5b424f7458ca52c5e gcc/config/s390/s390.opt a6413643c6a352ed2a285f593cc2f96d gcc/config/s390/s390intrin.h 1f405766a3e2d465229b0197ef1a6107 gcc/config/s390/s390x.h 551847ee4c38fa1a7e95fd93cdb32f17 gcc/config/s390/t-linux64 *************** c747af0360c8be518256b4b6cf5ec7e7 gcc/co *** 3847,3853 **** 3e991ad81d6eed806bcdfe7b6946db8d gcc/config/score/score.h 18880faf762788575ad101304d769438 gcc/config/score/score.md c8b8c25c17cf5e839f8ce93052fd0b21 gcc/config/score/score.opt ! 5960be83666a9cc6c617fdd0d705a12f gcc/config/sh/constraints.md d7ac9c886e9f407b86a33f4456396bc6 gcc/config/sh/divcost-analysis 862ad3aef49b4651fd77aaf83360ca0a gcc/config/sh/divtab-sh4-300.c 3333c4044a9455d56b6630c1e29e750c gcc/config/sh/divtab-sh4.c --- 3856,3862 ---- 3e991ad81d6eed806bcdfe7b6946db8d gcc/config/score/score.h 18880faf762788575ad101304d769438 gcc/config/score/score.md c8b8c25c17cf5e839f8ce93052fd0b21 gcc/config/score/score.opt ! ab89e2703d5fbf561e92af23400b5547 gcc/config/sh/constraints.md d7ac9c886e9f407b86a33f4456396bc6 gcc/config/sh/divcost-analysis 862ad3aef49b4651fd77aaf83360ca0a gcc/config/sh/divtab-sh4-300.c 3333c4044a9455d56b6630c1e29e750c gcc/config/sh/divtab-sh4.c *************** e018506f9d2836d561b720e484279b34 gcc/co *** 3859,3874 **** e5548c78703bb80a78213be560217e34 gcc/config/sh/little.h 03bb06cc7a728ac0925dec045e1abda5 gcc/config/sh/netbsd-elf.h 9969d0d0de1c69fd419a2e31e04864d4 gcc/config/sh/newlib.h ! 46f96612ab3a3727bc7b356758c3783b gcc/config/sh/predicates.md 54b2dbce026e04e4454a2e40e844a099 gcc/config/sh/rtems.h bde213ebbaee311cfdec4ae74a0a1504 gcc/config/sh/rtemself.h 478a949a555ded6891dcc98dafa592f2 gcc/config/sh/sh-c.c 981b6ec4b47c23da8b367105db12ab79 gcc/config/sh/sh-modes.def ! 9257eb3435a01969664ba8d20b35c44b gcc/config/sh/sh-protos.h ! 40b4f0cb9123b3cf3369a21bd5bd2229 gcc/config/sh/sh.c 43b4250562a6c95b5e25a336154bde1d gcc/config/sh/sh.h ! ea89771d7600e8fc20f410cdfb949c97 gcc/config/sh/sh.md ! f870631f7d199a77aee8c89b424d1c1d gcc/config/sh/sh.opt 1263fa72b2e5f7cbdf81a98d33bf721d gcc/config/sh/sh1.md c546660841ebe9ce572a566753eca775 gcc/config/sh/sh4-300.md 37fb2d37b97ff3859b60e83455c7d37e gcc/config/sh/sh4.md --- 3868,3883 ---- e5548c78703bb80a78213be560217e34 gcc/config/sh/little.h 03bb06cc7a728ac0925dec045e1abda5 gcc/config/sh/netbsd-elf.h 9969d0d0de1c69fd419a2e31e04864d4 gcc/config/sh/newlib.h ! aea8b9a2ebd754b960329a73b118ab07 gcc/config/sh/predicates.md 54b2dbce026e04e4454a2e40e844a099 gcc/config/sh/rtems.h bde213ebbaee311cfdec4ae74a0a1504 gcc/config/sh/rtemself.h 478a949a555ded6891dcc98dafa592f2 gcc/config/sh/sh-c.c 981b6ec4b47c23da8b367105db12ab79 gcc/config/sh/sh-modes.def ! 920320800240ca093fb61b7b2de8e677 gcc/config/sh/sh-protos.h ! fec33e4e6bdcc74232c73f39d5888fc1 gcc/config/sh/sh.c 43b4250562a6c95b5e25a336154bde1d gcc/config/sh/sh.h ! e2fa7620de8478f7830306271486b89e gcc/config/sh/sh.md ! 0ee1ff36ae1410876f042e70aeba351e gcc/config/sh/sh.opt 1263fa72b2e5f7cbdf81a98d33bf721d gcc/config/sh/sh1.md c546660841ebe9ce572a566753eca775 gcc/config/sh/sh4-300.md 37fb2d37b97ff3859b60e83455c7d37e gcc/config/sh/sh4.md *************** fa71ec60c7d509ba506b07a396ae88ba gcc/co *** 3904,3910 **** 75280f2acefb40bc22f8220c41c11da0 gcc/config/sparc/driver-sparc.c 252d2589f2835388424f649a726febab gcc/config/sparc/freebsd.h 9169b21ce0e85d63bde44cf2efbb4e65 gcc/config/sparc/hypersparc.md ! cbf1cc6b395c13a0efa0d7c5681d0894 gcc/config/sparc/leon.md a5a0061777c2c1da281f688a5e19eec4 gcc/config/sparc/linux.h 093ff99b24363952c35674ad16f5b4fb gcc/config/sparc/linux64.h 2bef0ee7b23cafb5e9621bea6bb75e98 gcc/config/sparc/long-double-switch.opt --- 3913,3919 ---- 75280f2acefb40bc22f8220c41c11da0 gcc/config/sparc/driver-sparc.c 252d2589f2835388424f649a726febab gcc/config/sparc/freebsd.h 9169b21ce0e85d63bde44cf2efbb4e65 gcc/config/sparc/hypersparc.md ! 2f565efc7e7d18654acb47ce1dee9dc5 gcc/config/sparc/leon.md a5a0061777c2c1da281f688a5e19eec4 gcc/config/sparc/linux.h 093ff99b24363952c35674ad16f5b4fb gcc/config/sparc/linux64.h 2bef0ee7b23cafb5e9621bea6bb75e98 gcc/config/sparc/long-double-switch.opt *************** d004f9a3eaebfaf8c55b760890d447bd gcc/co *** 3921,3935 **** 4782cc3ccf1bf5decb2fa3f665cc96f5 gcc/config/sparc/sp64-elf.h b75e22d37c9c2f8ad66d81fc06b17f8c gcc/config/sparc/sparc-c.c 02e826fd35d286ee705e2897332381f1 gcc/config/sparc/sparc-modes.def ! a63218af70abc2688f35e13614930208 gcc/config/sparc/sparc-opts.h ! 79c4b40cafeb9e3e0f6bac420c81ea13 gcc/config/sparc/sparc-protos.h ! b40f408b47766dccbdba7023d92b2a94 gcc/config/sparc/sparc.c ! c43cef8b1ff14eb630e7ef69268baa37 gcc/config/sparc/sparc.h ! e22b95ffb78b46d132719ac69055a7fe gcc/config/sparc/sparc.md ! 4a7396c3931f8e1b4b161cef5c3b3eab gcc/config/sparc/sparc.opt 4d6cb72fa0b635c160177d0e310af6a8 gcc/config/sparc/sparclet.md a333cb7df463e2e0d1a3d6484f2a8fcb gcc/config/sparc/supersparc.md ! b9ddb062d96fe3866e36ebd74548d8b5 gcc/config/sparc/sync.md 432bf1dc230feec03fb4b278c9b44240 gcc/config/sparc/sysv4.h 5c5bb64a3a720ba26e17499e52069315 gcc/config/sparc/t-elf 48f511ffae2603df921d13ce2cc38f4d gcc/config/sparc/t-leon --- 3930,3944 ---- 4782cc3ccf1bf5decb2fa3f665cc96f5 gcc/config/sparc/sp64-elf.h b75e22d37c9c2f8ad66d81fc06b17f8c gcc/config/sparc/sparc-c.c 02e826fd35d286ee705e2897332381f1 gcc/config/sparc/sparc-modes.def ! 6ac72e8972c90aa6919551fa2c61dda0 gcc/config/sparc/sparc-opts.h ! 6e921dbab76e82074f07450f33d791dc gcc/config/sparc/sparc-protos.h ! adc7aa7cd9b2efbdab5593c101c243aa gcc/config/sparc/sparc.c ! e16df148c254e989317aeab889eb23c5 gcc/config/sparc/sparc.h ! 9ba9f976ad900e7c1b00103bd6d6ccc6 gcc/config/sparc/sparc.md ! 183248f701c0160176b55a290b499b74 gcc/config/sparc/sparc.opt 4d6cb72fa0b635c160177d0e310af6a8 gcc/config/sparc/sparclet.md a333cb7df463e2e0d1a3d6484f2a8fcb gcc/config/sparc/supersparc.md ! 87e242c68165af872c79e4b96f42afdd gcc/config/sparc/sync.md 432bf1dc230feec03fb4b278c9b44240 gcc/config/sparc/sysv4.h 5c5bb64a3a720ba26e17499e52069315 gcc/config/sparc/t-elf 48f511ffae2603df921d13ce2cc38f4d gcc/config/sparc/t-leon *************** c3cf074012369004d33351087af8fea8 gcc/co *** 3937,3946 **** 4a7d3f368a24d549fabaafbe44fcb134 gcc/config/sparc/t-linux 6fea7e8cffd255398bc2386a77b28cf0 gcc/config/sparc/t-linux64 75987b7fdc6fa9c9ff2108ff1003e6d2 gcc/config/sparc/t-netbsd64 ! 6b0cf2769c3d3e9d9e1b997ff0faa938 gcc/config/sparc/t-rtems 016674912d270b254d697426c1dab9d9 gcc/config/sparc/t-rtems-64 511770bb20c2707fabd4f231ce8b83cf gcc/config/sparc/t-sol2-64 ! f44f86d61d6f74675e30f41a11e08a60 gcc/config/sparc/t-sparc b04597637b0c08dd3e6d1a40c43e76b4 gcc/config/sparc/t-vxworks b3fa3a5d1a3157fda7e6516df50a8223 gcc/config/sparc/tso.h c27670f15f58b2e0475df7587cf9a6bd gcc/config/sparc/ultra1_2.md --- 3946,3955 ---- 4a7d3f368a24d549fabaafbe44fcb134 gcc/config/sparc/t-linux 6fea7e8cffd255398bc2386a77b28cf0 gcc/config/sparc/t-linux64 75987b7fdc6fa9c9ff2108ff1003e6d2 gcc/config/sparc/t-netbsd64 ! bbcf8d830c02487bc0cf93b576238ac2 gcc/config/sparc/t-rtems 016674912d270b254d697426c1dab9d9 gcc/config/sparc/t-rtems-64 511770bb20c2707fabd4f231ce8b83cf gcc/config/sparc/t-sol2-64 ! 68e90f6783d11c0214cd7bd73c6e3589 gcc/config/sparc/t-sparc b04597637b0c08dd3e6d1a40c43e76b4 gcc/config/sparc/t-vxworks b3fa3a5d1a3157fda7e6516df50a8223 gcc/config/sparc/tso.h c27670f15f58b2e0475df7587cf9a6bd gcc/config/sparc/ultra1_2.md *************** f62347fb17ffdccf93a30b860f9f4dc2 gcc/co *** 3991,4008 **** 9ce0e91fe77023ea088c2ef2ecf4c11b gcc/config/tilegx/linux.h f9feaf0a320438636fdd5c0b7cb9b9a6 gcc/config/tilegx/mul-tables.c 60a01c79a6edc2f080956be9aaec1614 gcc/config/tilegx/predicates.md ! 57576a68c815cc90aa280ea12340e198 gcc/config/tilegx/sync.md 7bf5713be56996f566a86927d32ac67b gcc/config/tilegx/t-tilegx f4e30558c131f948951b7f6ad2bce237 gcc/config/tilegx/tilegx-builtins.h ! 00d613fc87c170fc6464419cecc36e14 gcc/config/tilegx/tilegx-c.c e114b40e7bb23ee50d8e216ef751fe5b gcc/config/tilegx/tilegx-generic.md 9e765b8f3a308d77b279e9564f93dede gcc/config/tilegx/tilegx-modes.def ea41683402be9e3caa9f21abf2437d65 gcc/config/tilegx/tilegx-multiply.h 6aea463bc58500d1cc0137f65b1d58f9 gcc/config/tilegx/tilegx-opts.h f83850fbb29e4a921fe9bfdcd5802ca0 gcc/config/tilegx/tilegx-protos.h ! df10642a748accc3743d0743f729077e gcc/config/tilegx/tilegx.c 9103fc4cfb2774454c296fc2951a387d gcc/config/tilegx/tilegx.h ! 2fd1c8a2047f6eb591a55e62caaffc39 gcc/config/tilegx/tilegx.md 36dac282ca58905798310e998ae97794 gcc/config/tilegx/tilegx.opt bc176ed3cf54ea95cbcd8c10ec59e51d gcc/config/tilepro/constraints.md f62347fb17ffdccf93a30b860f9f4dc2 gcc/config/tilepro/feedback.h --- 4000,4017 ---- 9ce0e91fe77023ea088c2ef2ecf4c11b gcc/config/tilegx/linux.h f9feaf0a320438636fdd5c0b7cb9b9a6 gcc/config/tilegx/mul-tables.c 60a01c79a6edc2f080956be9aaec1614 gcc/config/tilegx/predicates.md ! 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gcc/testsuite/g++.dg/eh/unwind1.C a758dbc649ac4070d4dbe5fa7130d1e5 gcc/testsuite/g++.dg/eh/unwind2.C *************** ce7b6234ca0490c5f395644574322ca2 gcc/te *** 9995,10001 **** 47ee2e9f4d1f4caaa66273c534a05700 gcc/testsuite/g++.dg/expr/call5.C 2ef606c671097dddd5d5000c30530ba5 gcc/testsuite/g++.dg/expr/cast1.C 234b04abbf4ba798c38bda66394b82a7 gcc/testsuite/g++.dg/expr/cast10.C ! 0e456a0f4355cca0f4c5d2b05dc17f38 gcc/testsuite/g++.dg/expr/cast2.C 43b3f0cf8dc0665f8a82af5379392da1 gcc/testsuite/g++.dg/expr/cast3.C ed8e65f6a9fb8340f4d8881b00bc8a62 gcc/testsuite/g++.dg/expr/cast4.C 0c73fdd0b381eed7e392d54723abee36 gcc/testsuite/g++.dg/expr/cast6.C --- 10054,10060 ---- 47ee2e9f4d1f4caaa66273c534a05700 gcc/testsuite/g++.dg/expr/call5.C 2ef606c671097dddd5d5000c30530ba5 gcc/testsuite/g++.dg/expr/cast1.C 234b04abbf4ba798c38bda66394b82a7 gcc/testsuite/g++.dg/expr/cast10.C ! 87cf1e986278e73844d707b2ae5abd5f gcc/testsuite/g++.dg/expr/cast2.C 43b3f0cf8dc0665f8a82af5379392da1 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gcc/testsuite/gcc.target/x86_64/abi/test_3_element_struct_and_unions.c --- 35774,35795 ---- d02989c16f0d1cd0951fe435483c550e gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_unions.c 20fc692838521190fafccf16cce89482 gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.exp b52212e25b4fe43a1bda56b50d2cc914 gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.h ! fc248ef3133a3ca9a3703d90b71facc6 gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c ! 14252515c7db45468bb0d595f7f35533 gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c ! bf9625ebc9705fa5db6ee3fe57f799f6 gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c ! 4aaf2e837c6569916e1ab83e57ff11e4 gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c ! 6cb133e3aec8323bc0956a7fac2745cb gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c ! 2060f8f935b5f4a10cd993867a85d9e0 gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c ! 75f54a7e57d8a432e50fa00e40618c72 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gcc/tree-nomudflap.c 04aaee354b75f1449e2380f44ce6983d gcc/tree-nrv.c ! f022abac96ef0eb7e9c43e73793bc0cf gcc/tree-object-size.c 455978c94f31394ec28e886d0cfab05d gcc/tree-optimize.c 356e8f99c98122df8e188147ee88b405 gcc/tree-outof-ssa.c 8fd50142b0fa437a55185de9e002ad28 gcc/tree-parloops.c 47f1231c6cdfdb103d2ff831d2c27d41 gcc/tree-pass.h bd460d2caaeb01469c672ef3221eef18 gcc/tree-phinodes.c ! 898c8f01096591fe53ddd55b623c5e7d gcc/tree-predcom.c dddf038e7a240a18586c3fcb1683d30d gcc/tree-pretty-print.c 1f619536d0b2d8e9ff93c951fc7e88ab gcc/tree-pretty-print.h 91161ffd17ef85c8a099d7dd5fcdc659 gcc/tree-profile.c 03ac00b80fa4c73e9a1a24e495342a6b gcc/tree-scalar-evolution.c 7a423ea0669b0af23fb01196fec57dad gcc/tree-scalar-evolution.h ! fb3aaa38bcc808fc2141b6408faa37ca gcc/tree-sra.c ad49186a0a84fbac461b01b3030c1e44 gcc/tree-ssa-address.c 3826ea88f246b7013040944483a2e833 gcc/tree-ssa-alias.c db1587e6eb45bf71279bd5efa5ee185f gcc/tree-ssa-alias.h --- 43545,43563 ---- dfa7692d33439e94364d634ec6be44bb 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cd14a97dd8a0613bb1244a68c0c764d6 zlib/contrib/ada/buffer_demo.adb diff -Nrcpad gcc-4.8.2/NEWS gcc-4.8.3/NEWS *** gcc-4.8.2/NEWS Wed Oct 16 07:28:43 2013 --- gcc-4.8.3/NEWS Thu May 22 09:14:32 2014 *************** see ONEWS. *** 6,31 **** ====================================================================== http://gcc.gnu.org/gcc-4.8/index.html GCC 4.8 Release Series ! October 16, 2013 The [1]GNU project and the GCC developers are pleased to announce the ! release of GCC 4.8.2. This release is a bug-fix release, containing fixes for regressions in ! GCC 4.8.1 relative to previous releases of GCC. Release History GCC 4.8.2 ! October 16, 2013 ([2]changes, [3]documentation) GCC 4.8.1 ! May 31, 2013 ([4]changes, [5]documentation) GCC 4.8.0 ! March 22, 2013 ([6]changes, [7]documentation) References and Acknowledgements --- 6,35 ---- ====================================================================== http://gcc.gnu.org/gcc-4.8/index.html + GCC 4.8 Release Series ! May 22, 2014 The [1]GNU project and the GCC developers are pleased to announce the ! release of GCC 4.8.3. This release is a bug-fix release, containing fixes for regressions in ! GCC 4.8.2 relative to previous releases of GCC. Release History + GCC 4.8.3 + May 22, 2014 ([2]changes, [3]documentation) + GCC 4.8.2 ! October 16, 2013 ([4]changes, [5]documentation) GCC 4.8.1 ! May 31, 2013 ([6]changes, [7]documentation) GCC 4.8.0 ! March 22, 2013 ([8]changes, [9]documentation) References and Acknowledgements *************** References and Acknowledgements *** 33,90 **** supports several other languages aside from C, it now stands for the GNU Compiler Collection. ! A list of [8]successful builds is updated as new information becomes available. The GCC developers would like to thank the numerous people that have contributed new features, improvements, bug fixes, and other changes as ! well as test results to GCC. This [9]amazing group of volunteers is what makes GCC successful. ! For additional information about GCC please refer to the [10]GCC ! project web site or contact the [11]GCC development mailing list. ! To obtain GCC please use [12]our mirror sites or [13]our SVN server. For questions related to the use of GCC, please consult these web ! pages and the [14]GCC manuals. If that fails, the ! [15]gcc-help@gcc.gnu.org mailing list might help. Comments on these web pages and the development of GCC are welcome on our developer ! list at [16]gcc@gcc.gnu.org. All of [17]our lists have public archives. ! Copyright (C) [18]Free Software Foundation, Inc. Verbatim copying and distribution of this entire article is permitted in any medium, provided this notice is preserved. ! These pages are [19]maintained by the GCC team. Last modified ! 2013-10-16[20]. References 1. http://www.gnu.org/ 2. http://gcc.gnu.org/gcc-4.8/changes.html ! 3. http://gcc.gnu.org/onlinedocs/4.8.2/ 4. http://gcc.gnu.org/gcc-4.8/changes.html ! 5. http://gcc.gnu.org/onlinedocs/4.8.1/ 6. http://gcc.gnu.org/gcc-4.8/changes.html ! 7. http://gcc.gnu.org/onlinedocs/4.8.0/ ! 8. http://gcc.gnu.org/gcc-4.8/buildstat.html ! 9. http://gcc.gnu.org/onlinedocs/gcc/Contributors.html ! 10. http://gcc.gnu.org/index.html ! 11. mailto:gcc@gcc.gnu.org ! 12. http://gcc.gnu.org/mirrors.html ! 13. http://gcc.gnu.org/svn.html ! 14. http://gcc.gnu.org/onlinedocs/ ! 15. mailto:gcc-help@gcc.gnu.org ! 16. mailto:gcc@gcc.gnu.org ! 17. http://gcc.gnu.org/lists.html ! 18. http://www.fsf.org/ ! 19. http://gcc.gnu.org/about.html ! 20. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.8/changes.html GCC 4.8 Release Series Changes, New Features, and Fixes --- 37,97 ---- supports several other languages aside from C, it now stands for the GNU Compiler Collection. ! A list of [10]successful builds is updated as new information becomes available. The GCC developers would like to thank the numerous people that have contributed new features, improvements, bug fixes, and other changes as ! well as test results to GCC. This [11]amazing group of volunteers is what makes GCC successful. ! For additional information about GCC please refer to the [12]GCC ! project web site or contact the [13]GCC development mailing list. ! To obtain GCC please use [14]our mirror sites or [15]our SVN server. For questions related to the use of GCC, please consult these web ! pages and the [16]GCC manuals. If that fails, the ! [17]gcc-help@gcc.gnu.org mailing list might help. Comments on these web pages and the development of GCC are welcome on our developer ! list at [18]gcc@gcc.gnu.org. All of [19]our lists have public archives. ! Copyright (C) [20]Free Software Foundation, Inc. Verbatim copying and distribution of this entire article is permitted in any medium, provided this notice is preserved. ! These pages are [21]maintained by the GCC team. Last modified ! 2014-05-22[22]. References 1. http://www.gnu.org/ 2. http://gcc.gnu.org/gcc-4.8/changes.html ! 3. http://gcc.gnu.org/onlinedocs/4.8.3/ 4. http://gcc.gnu.org/gcc-4.8/changes.html ! 5. http://gcc.gnu.org/onlinedocs/4.8.2/ 6. http://gcc.gnu.org/gcc-4.8/changes.html ! 7. http://gcc.gnu.org/onlinedocs/4.8.1/ ! 8. http://gcc.gnu.org/gcc-4.8/changes.html ! 9. http://gcc.gnu.org/onlinedocs/4.8.0/ ! 10. http://gcc.gnu.org/gcc-4.8/buildstat.html ! 11. http://gcc.gnu.org/onlinedocs/gcc/Contributors.html ! 12. http://gcc.gnu.org/index.html ! 13. mailto:gcc@gcc.gnu.org ! 14. http://gcc.gnu.org/mirrors.html ! 15. http://gcc.gnu.org/svn.html ! 16. http://gcc.gnu.org/onlinedocs/ ! 17. mailto:gcc-help@gcc.gnu.org ! 18. mailto:gcc@gcc.gnu.org ! 19. http://gcc.gnu.org/lists.html ! 20. http://www.fsf.org/ ! 21. http://gcc.gnu.org/about.html ! 22. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.8/changes.html + GCC 4.8 Release Series Changes, New Features, and Fixes *************** General Optimizer Improvements (and Chan *** 196,204 **** races. The ThreadSanitizer is available on x86-64 GNU/Linux. * A new local register allocator (LRA) has been implemented, which replaces the 26 year old reload pass and improves generated code ! quality. For now it is active on the ia32 and x86-64 targets. * Support for transactional memory has been implemented on the ! following architectures: IA-32/x86-64, ARM, PowerPC, SH, Sparc, and Alpha. New Languages and Language specific improvements --- 203,211 ---- races. The ThreadSanitizer is available on x86-64 GNU/Linux. * A new local register allocator (LRA) has been implemented, which replaces the 26 year old reload pass and improves generated code ! quality. For now it is active on the IA-32 and x86-64 targets. * Support for transactional memory has been implemented on the ! following architectures: IA-32/x86-64, ARM, PowerPC, SH, SPARC, and Alpha. New Languages and Language specific improvements *************** int i = A().f(); // error, f() requires *** 366,372 **** * The [21]-Wcompare-reals command-line option has been added. When this is set, warnings are issued when comparing REAL or COMPLEX types for equality and inequality; consider replacing a == b by ! abs(a-b) < eps with a suitable eps. -Wcompare-reals is enabled by -Wextra. * The [22]-Wtarget-lifetime command-line option has been added (enabled with -Wall), which warns if the pointer in a pointer --- 373,379 ---- * The [21]-Wcompare-reals command-line option has been added. When this is set, warnings are issued when comparing REAL or COMPLEX types for equality and inequality; consider replacing a == b by ! abs(a -b) < eps with a suitable eps. -Wcompare-reals is enabled by -Wextra. * The [22]-Wtarget-lifetime command-line option has been added (enabled with -Wall), which warns if the pointer in a pointer *************** int i = A().f(); // error, f() requires *** 400,405 **** --- 407,414 ---- Go + * GCC 4.8.2 provides a complete implementation of the Go 1.1.2 + release. * GCC 4.8.0 and 4.8.1 implement a preliminary version of the Go 1.1 release. The library support is not quite complete. * Go has been tested on GNU/Linux and Solaris platforms for various *************** New Targets and Target Specific Improvem *** 556,562 **** } Please refer to this [32]wiki for more information. ! * The x86 backend has been improved to allow option -fschedule-insns to work reliably. This option can be used to schedule instructions better and leads to improved performace in certain cases. * Windows MinGW-w64 targets (*-w64-mingw*) require at least r5437 --- 565,571 ---- } Please refer to this [32]wiki for more information. ! * The x86 back end has been improved to allow option -fschedule-insns to work reliably. This option can be used to schedule instructions better and leads to improved performace in certain cases. * Windows MinGW-w64 targets (*-w64-mingw*) require at least r5437 *************** GCC 4.8.2 *** 759,778 **** not be complete (that is, it is possible that some PRs that have been fixed are not listed here). For questions related to the use of GCC, please consult these web ! pages and the [35]GCC manuals. If that fails, the ! [36]gcc-help@gcc.gnu.org mailing list might help. Comments on these web pages and the development of GCC are welcome on our developer ! list at [37]gcc@gcc.gnu.org. All of [38]our lists have public archives. ! Copyright (C) [39]Free Software Foundation, Inc. Verbatim copying and distribution of this entire article is permitted in any medium, provided this notice is preserved. ! These pages are [40]maintained by the GCC team. Last modified ! 2013-10-16[41]. References --- 768,797 ---- not be complete (that is, it is possible that some PRs that have been fixed are not listed here). + GCC 4.8.3 + + This is the [35]list of problem reports (PRs) from GCC's bug tracking + system that are known to be fixed in the 4.8.3 release. This list might + not be complete (that is, it is possible that some PRs that have been + fixed are not listed here). + + Support for the new powerpc64le-linux platform has been added. It + defaults to generating code that conforms to the ELFV2 ABI. + For questions related to the use of GCC, please consult these web ! pages and the [36]GCC manuals. If that fails, the ! [37]gcc-help@gcc.gnu.org mailing list might help. Comments on these web pages and the development of GCC are welcome on our developer ! list at [38]gcc@gcc.gnu.org. All of [39]our lists have public archives. ! Copyright (C) [40]Free Software Foundation, Inc. Verbatim copying and distribution of this entire article is permitted in any medium, provided this notice is preserved. ! These pages are [41]maintained by the GCC team. Last modified ! 2014-05-22[42]. References *************** References *** 810,824 **** 32. http://gcc.gnu.org/wiki/FunctionMultiVersioning 33. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.8.1 34. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.8.2 ! 35. http://gcc.gnu.org/onlinedocs/ ! 36. mailto:gcc-help@gcc.gnu.org ! 37. mailto:gcc@gcc.gnu.org ! 38. http://gcc.gnu.org/lists.html ! 39. http://www.fsf.org/ ! 40. http://gcc.gnu.org/about.html ! 41. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.7/index.html GCC 4.7 Release Series April 11, 2013 --- 829,845 ---- 32. http://gcc.gnu.org/wiki/FunctionMultiVersioning 33. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.8.1 34. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.8.2 ! 35. http://gcc.gnu.org/bugzilla/buglist.cgi?bug_status=RESOLVED&resolution=FIXED&target_milestone=4.8.3 ! 36. http://gcc.gnu.org/onlinedocs/ ! 37. mailto:gcc-help@gcc.gnu.org ! 38. mailto:gcc@gcc.gnu.org ! 39. http://gcc.gnu.org/lists.html ! 40. http://www.fsf.org/ ! 41. http://gcc.gnu.org/about.html ! 42. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.7/index.html + GCC 4.7 Release Series April 11, 2013 *************** References *** 903,908 **** --- 924,930 ---- 22. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.7/changes.html + GCC 4.7 Release Series Changes, New Features, and Fixes *************** References *** 1748,1753 **** --- 1770,1776 ---- 55. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.6/index.html + GCC 4.6 Release Series April 12, 2013 *************** References *** 1837,1842 **** --- 1860,1866 ---- 24. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.6/changes.html + GCC 4.6 Release Series Changes, New Features, and Fixes *************** References *** 2767,2772 **** --- 2791,2797 ---- 30. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.5/index.html + GCC 4.5 Release Series Jul 2, 2012 *************** References *** 2851,2856 **** --- 2876,2882 ---- 19. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.5/changes.html + GCC 4.5 Release Series Changes, New Features, and Fixes *************** References *** 3538,3543 **** --- 3564,3570 ---- 35. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.4/index.html + GCC 4.4 Release Series March 13, 2012 *************** References *** 3634,3639 **** --- 3661,3667 ---- 22. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.4/changes.html + GCC 4.4 Release Series Changes, New Features, and Fixes *************** References *** 4268,4273 **** --- 4296,4302 ---- 26. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.3/index.html + GCC 4.3 Release Series Jun 27, 2011 *************** References *** 4360,4365 **** --- 4389,4395 ---- 21. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.3/changes.html + GCC 4.3 Release Series Changes, New Features, and Fixes *************** References *** 5181,5186 **** --- 5211,5217 ---- 37. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.2/index.html + GCC 4.2 Release Series May 19, 2008 *************** References *** 5265,5270 **** --- 5296,5302 ---- 19. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.2/changes.html + GCC 4.2 Release Series Changes, New Features, and Fixes *************** References *** 5588,5593 **** --- 5620,5626 ---- 13. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.1/index.html + GCC 4.1 Release Series February 13, 2007 *************** References *** 5664,5669 **** --- 5697,5703 ---- 17. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.1/changes.html + GCC 4.1 Release Series Changes, New Features, and Fixes *************** References *** 6223,6228 **** --- 6257,6263 ---- 13. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.0/index.html + GCC 4.0 Release Series January 31, 2007 *************** References *** 6307,6312 **** --- 6342,6348 ---- 19. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-4.0/changes.html + GCC 4.0 Release Series Changes, New Features, and Fixes *************** References *** 6836,6841 **** --- 6872,6878 ---- 22. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-3.4/index.html + GCC 3.4 Release Series May 26, 2006 *************** References *** 6935,6940 **** --- 6972,6978 ---- 23. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-3.4/changes.html + GCC 3.4 Release Series Changes, New Features, and Fixes *************** References *** 9118,9123 **** --- 9156,9162 ---- 418. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-3.3/index.html + GCC 3.3 Release Series May 03, 2005 *************** References *** 9217,9222 **** --- 9256,9262 ---- 22. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-3.3/changes.html + GCC 3.3 Release Series Changes, New Features, and Fixes *************** GCC 3.3.6 *** 10564,10570 **** provided this notice is preserved. These pages are [558]maintained by the GCC team. Last modified ! 2012-11-02[559]. References --- 10604,10610 ---- provided this notice is preserved. These pages are [558]maintained by the GCC team. Last modified ! 2013-10-31[559]. References *************** References *** 10573,10579 **** 3. http://gcc.gnu.org/gcc-3.3/changes.html#obsolete_systems 4. http://gcc.gnu.org/gcc-3.3/changes.html#nonnull_attribute 5. http://gcc.gnu.org/news/dfa.html ! 6. http://gcc.gnu.org/gcc-3.3/c99status.html 7. http://gcc.gnu.org/onlinedocs/gcc-3.3.6/g77/News.html 8. http://gcc.gnu.org/PR10140 9. http://gcc.gnu.org/PR10198 --- 10613,10619 ---- 3. http://gcc.gnu.org/gcc-3.3/changes.html#obsolete_systems 4. http://gcc.gnu.org/gcc-3.3/changes.html#nonnull_attribute 5. http://gcc.gnu.org/news/dfa.html ! 6. http://gcc.gnu.org/c99status.html 7. http://gcc.gnu.org/onlinedocs/gcc-3.3.6/g77/News.html 8. http://gcc.gnu.org/PR10140 9. http://gcc.gnu.org/PR10198 *************** References *** 11129,11134 **** --- 11169,11175 ---- 559. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-3.2/index.html + GCC 3.2 Release Series April 25, 2003 *************** References *** 11218,11223 **** --- 11259,11265 ---- 18. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-3.2/changes.html + GCC 3.2 Release Series Changes, New Features, and Fixes *************** References *** 12075,12080 **** --- 12117,12123 ---- 252. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-3.1/index.html + GCC 3.1 July 27, 2002 *************** References *** 12141,12146 **** --- 12184,12190 ---- 15. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-3.1/changes.html + GCC 3.1 Release Series Changes, New Features, and Fixes *************** Documentation improvements *** 12475,12488 **** provided this notice is preserved. These pages are [18]maintained by the GCC team. Last modified ! 2012-11-02[19]. References 1. http://gcc.gnu.org/ml/gcc/2002-07/msg01208.html 2. http://gcc.gnu.org/news/profiledriven.html 3. http://gcc.gnu.org/benchmarks/ ! 4. http://gcc.gnu.org/gcc-3.1/c99status.html 5. http://gcc.gnu.org/onlinedocs/libstdc++/faq.html 6. http://gcc.gnu.org/onlinedocs/gcc-3.1.1/g77/News.html 7. http://www.adacore.com/ --- 12519,12532 ---- provided this notice is preserved. These pages are [18]maintained by the GCC team. Last modified ! 2013-10-31[19]. References 1. http://gcc.gnu.org/ml/gcc/2002-07/msg01208.html 2. http://gcc.gnu.org/news/profiledriven.html 3. http://gcc.gnu.org/benchmarks/ ! 4. http://gcc.gnu.org/c99status.html 5. http://gcc.gnu.org/onlinedocs/libstdc++/faq.html 6. http://gcc.gnu.org/onlinedocs/gcc-3.1.1/g77/News.html 7. http://www.adacore.com/ *************** References *** 12500,12505 **** --- 12544,12550 ---- 19. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-3.0/gcc-3.0.html + GCC 3.0.4 February 20, 2002 *************** References *** 12573,12578 **** --- 12618,12624 ---- 15. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-3.0/features.html + GCC 3.0 New Features Additional changes in GCC 3.0.4 *************** New Languages and Language specific impr *** 12672,12678 **** New Targets and Target Specific Improvements ! * New x86 back-end, generating much improved code. * Support for a generic i386-elf target contributed. * New option to emit x86 assembly code using Intel style syntax (-mintel-syntax). --- 12718,12724 ---- New Targets and Target Specific Improvements ! * New x86 back end, generating much improved code. * Support for a generic i386-elf target contributed. * New option to emit x86 assembly code using Intel style syntax (-mintel-syntax). *************** Other significant improvements *** 12743,12749 **** provided this notice is preserved. These pages are [19]maintained by the GCC team. Last modified ! 2012-11-02[20]. References --- 12789,12795 ---- provided this notice is preserved. These pages are [19]maintained by the GCC team. Last modified ! 2013-12-03[20]. References *************** References *** 12756,12762 **** 7. http://gcc.gnu.org/libstdc++/ 8. http://gcc.gnu.org/news/inlining.html 9. http://gcc.gnu.org/news/dependencies.html ! 10. http://gcc.gnu.org/gcc-3.0/c99status.html 11. http://gcc.gnu.org/onlinedocs/gcc-3.4.6/g77/News.html 12. http://gcc.gnu.org/gcc-3.0/libgcc.html 13. http://gcc.gnu.org/gcc-2.95/features.html --- 12802,12808 ---- 7. http://gcc.gnu.org/libstdc++/ 8. http://gcc.gnu.org/news/inlining.html 9. http://gcc.gnu.org/news/dependencies.html ! 10. http://gcc.gnu.org/c99status.html 11. http://gcc.gnu.org/onlinedocs/gcc-3.4.6/g77/News.html 12. http://gcc.gnu.org/gcc-3.0/libgcc.html 13. http://gcc.gnu.org/gcc-2.95/features.html *************** References *** 12769,12774 **** --- 12815,12821 ---- 20. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-3.0/caveats.html + GCC 3.0 Caveats * -fstrict-aliasing is now part of -O2 and higher optimization *************** References *** 12829,12834 **** --- 12876,12882 ---- 8. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-2.95/index.html + GCC 2.95 March 16, 2001: The GNU project and the GCC developers are pleased to *************** References *** 12918,12923 **** --- 12966,12972 ---- 17. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-2.95/features.html + GCC 2.95 New Features * General Optimizer Improvements: *************** References *** 13190,13195 **** --- 13239,13245 ---- 23. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/gcc-2.95/caveats.html + GCC 2.95 Caveats * GCC 2.95 will issue an error for invalid asm statements that had *************** References *** 13258,13263 **** --- 13308,13314 ---- 8. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/egcs-1.1/index.html + EGCS 1.1 September 3, 1998: We are pleased to announce the release of EGCS 1.1. *************** References *** 13488,13493 **** --- 13539,13545 ---- 17. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/egcs-1.1/features.html + EGCS 1.1 new features * Integrated GNU Fortran (g77) compiler and runtime library with *************** References *** 13582,13587 **** --- 13634,13640 ---- 11. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/egcs-1.1/caveats.html + EGCS 1.1 Caveats * EGCS has an integrated libstdc++, but does not have an integrated *************** References *** 13632,13637 **** --- 13685,13691 ---- 7. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/egcs-1.0/index.html + EGCS 1.0 December 3, 1997: We are pleased to announce the release of EGCS 1.0. *************** http://gcc.gnu.org/egcs-1.0/index.html *** 13697,13703 **** "official", so to avoid future compatibility problems we recommend against distributing any shared libraries built by EGCS 1.0 that contain C++ code (upgrade to 1.0.1 and use that). ! * Various bugfixes in the x86, hppa, mips, and rs6000/ppc backends. The x86 changes fix code generation errors exposed when building glibc2 and the usual GNU/Linux dynamic linker (ld.so). The hppa change fixes a compiler abort when configured for use with --- 13751,13757 ---- "official", so to avoid future compatibility problems we recommend against distributing any shared libraries built by EGCS 1.0 that contain C++ code (upgrade to 1.0.1 and use that). ! * Various bugfixes in the x86, hppa, mips, and rs6000/ppc back ends. The x86 changes fix code generation errors exposed when building glibc2 and the usual GNU/Linux dynamic linker (ld.so). The hppa change fixes a compiler abort when configured for use with *************** http://gcc.gnu.org/egcs-1.0/index.html *** 13815,13821 **** provided this notice is preserved. These pages are [11]maintained by the GCC team. Last modified ! 2012-11-02[12]. References --- 13869,13875 ---- provided this notice is preserved. These pages are [11]maintained by the GCC team. Last modified ! 2013-12-03[12]. References *************** References *** 13833,13838 **** --- 13887,13893 ---- 12. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/egcs-1.0/features.html + EGCS 1.0 features * Core compiler is based on the gcc2 development tree from Aug 2, *************** References *** 13897,13902 **** --- 13952,13958 ---- 9. http://validator.w3.org/check/referer ====================================================================== http://gcc.gnu.org/egcs-1.0/caveats.html + EGCS 1.0 Caveats * EGCS has an integrated libstdc++, but does not have an integrated diff -Nrcpad gcc-4.8.2/boehm-gc/ChangeLog gcc-4.8.3/boehm-gc/ChangeLog *** gcc-4.8.2/boehm-gc/ChangeLog Wed Oct 16 07:19:20 2013 --- gcc-4.8.3/boehm-gc/ChangeLog Thu May 22 09:08:15 2014 *************** *** 1,3 **** --- 1,19 ---- + 2014-05-22 Release Manager + + * GCC 4.8.3 released. + + 2014-04-04 Bill Schmidt + + Backport from mainline + 2013-11-15 Ulrich Weigand + + * configure: Regenerate. + + 2013-12-29 Andreas Tobler + + Merge from trunk: + * include/private/gcconfig.h: Add FreeBSD powerpc64 defines. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff -Nrcpad gcc-4.8.2/boehm-gc/configure gcc-4.8.3/boehm-gc/configure *** gcc-4.8.2/boehm-gc/configure Wed Oct 16 07:27:58 2013 --- gcc-4.8.3/boehm-gc/configure Thu May 22 09:13:48 2014 *************** ia64-*-hpux*) *** 6770,6776 **** rm -rf conftest* ;; ! x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ s390*-*linux*|s390*-*tpf*|sparc*-*linux*) # Find out which ABI we are using. echo 'int i;' > conftest.$ac_ext --- 6770,6776 ---- rm -rf conftest* ;; ! x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ s390*-*linux*|s390*-*tpf*|sparc*-*linux*) # Find out which ABI we are using. echo 'int i;' > conftest.$ac_ext *************** s390*-*linux*|s390*-*tpf*|sparc*-*linux* *** 6795,6801 **** ;; esac ;; ! ppc64-*linux*|powerpc64-*linux*) LD="${LD-ld} -m elf32ppclinux" ;; s390x-*linux*) --- 6795,6804 ---- ;; esac ;; ! powerpc64le-*linux*) ! LD="${LD-ld} -m elf32lppclinux" ! ;; ! powerpc64-*linux*) LD="${LD-ld} -m elf32ppclinux" ;; s390x-*linux*) *************** s390*-*linux*|s390*-*tpf*|sparc*-*linux* *** 6814,6820 **** x86_64-*linux*) LD="${LD-ld} -m elf_x86_64" ;; ! ppc*-*linux*|powerpc*-*linux*) LD="${LD-ld} -m elf64ppc" ;; s390*-*linux*|s390*-*tpf*) --- 6817,6826 ---- x86_64-*linux*) LD="${LD-ld} -m elf_x86_64" ;; ! powerpcle-*linux*) ! LD="${LD-ld} -m elf64lppc" ! ;; ! powerpc-*linux*) LD="${LD-ld} -m elf64ppc" ;; s390*-*linux*|s390*-*tpf*) *************** else *** 11312,11318 **** lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF ! #line 11315 "configure" #include "confdefs.h" #if HAVE_DLFCN_H --- 11318,11324 ---- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF ! #line 11321 "configure" #include "confdefs.h" #if HAVE_DLFCN_H *************** else *** 11418,11424 **** lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF ! #line 11421 "configure" #include "confdefs.h" #if HAVE_DLFCN_H --- 11424,11430 ---- lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF ! #line 11427 "configure" #include "confdefs.h" #if HAVE_DLFCN_H diff -Nrcpad gcc-4.8.2/boehm-gc/include/private/gcconfig.h gcc-4.8.3/boehm-gc/include/private/gcconfig.h *** gcc-4.8.2/boehm-gc/include/private/gcconfig.h Wed Mar 6 15:08:58 2013 --- gcc-4.8.3/boehm-gc/include/private/gcconfig.h Sun Dec 29 22:42:08 2013 *************** *** 837,843 **** --- 837,851 ---- # define NO_PTHREAD_TRYLOCK # endif # ifdef FREEBSD + # if defined(__powerpc64__) + # define ALIGNMENT 8 + # define CPP_WORDSZ 64 + # ifndef HBLKSIZE + # define HBLKSIZE 4096 + # endif + # else # define ALIGNMENT 4 + # endif # define OS_TYPE "FREEBSD" # ifndef GC_FREEBSD_THREADS # define MPROTECT_VDB diff -Nrcpad gcc-4.8.2/config/ChangeLog gcc-4.8.3/config/ChangeLog *** gcc-4.8.2/config/ChangeLog Wed Oct 16 07:17:49 2013 --- gcc-4.8.3/config/ChangeLog Thu May 22 09:09:37 2014 *************** *** 1,3 **** --- 1,7 ---- + 2014-05-22 Release Manager + + * GCC 4.8.3 released. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff -Nrcpad gcc-4.8.2/config.guess gcc-4.8.3/config.guess *** gcc-4.8.2/config.guess Tue Jan 8 22:46:38 2013 --- gcc-4.8.3/config.guess Fri Apr 4 13:48:08 2014 *************** *** 1,10 **** #! /bin/sh # Attempt to guess a canonical system name. ! # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, ! # 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, ! # 2011, 2012, 2013 Free Software Foundation, Inc. ! timestamp='2012-12-30' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by --- 1,8 ---- #! /bin/sh # Attempt to guess a canonical system name. ! # Copyright 1992-2013 Free Software Foundation, Inc. ! timestamp='2013-06-10' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by *************** version="\ *** 52,60 **** GNU config.guess ($timestamp) Originally written by Per Bothner. ! Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, ! 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, ! 2012, 2013 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." --- 50,56 ---- GNU config.guess ($timestamp) Originally written by Per Bothner. ! Copyright 1992-2013 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." *************** UNAME_RELEASE=`(uname -r) 2>/dev/null` | *** 136,141 **** --- 132,158 ---- UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown + case "${UNAME_SYSTEM}" in + Linux|GNU|GNU/*) + # If the system lacks a compiler, then just pick glibc. + # We could probably try harder. + LIBC=gnu + + eval $set_cc_for_build + cat <<-EOF > $dummy.c + #include + #if defined(__UCLIBC__) + LIBC=uclibc + #elif defined(__dietlibc__) + LIBC=dietlibc + #else + LIBC=gnu + #endif + EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'` + ;; + esac + # Note: order is significant - the case branches are not exclusive. case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in *************** EOF *** 857,877 **** exit ;; *:GNU:*:*) # the GNU system ! echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` exit ;; *:GNU/*:*:*) # other systems with GNU libc and userland ! echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu exit ;; i*86:Minix:*:*) echo ${UNAME_MACHINE}-pc-minix exit ;; aarch64:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; aarch64_be:Linux:*:*) UNAME_MACHINE=aarch64_be ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; alpha:Linux:*:*) case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in --- 874,894 ---- exit ;; *:GNU:*:*) # the GNU system ! echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` exit ;; *:GNU/*:*:*) # other systems with GNU libc and userland ! echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC} exit ;; i*86:Minix:*:*) echo ${UNAME_MACHINE}-pc-minix exit ;; aarch64:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; aarch64_be:Linux:*:*) UNAME_MACHINE=aarch64_be ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; alpha:Linux:*:*) case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in *************** EOF *** 884,942 **** EV68*) UNAME_MACHINE=alphaev68 ;; esac objdump --private-headers /bin/sh | grep -q ld.so.1 ! if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi ! echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} exit ;; arm*:Linux:*:*) eval $set_cc_for_build if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ | grep -q __ARM_EABI__ then ! echo ${UNAME_MACHINE}-unknown-linux-gnu else if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \ | grep -q __ARM_PCS_VFP then ! echo ${UNAME_MACHINE}-unknown-linux-gnueabi else ! echo ${UNAME_MACHINE}-unknown-linux-gnueabihf fi fi exit ;; avr32*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; cris:Linux:*:*) ! echo ${UNAME_MACHINE}-axis-linux-gnu exit ;; crisv32:Linux:*:*) ! echo ${UNAME_MACHINE}-axis-linux-gnu exit ;; frv:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; hexagon:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; i*86:Linux:*:*) ! LIBC=gnu ! eval $set_cc_for_build ! sed 's/^ //' << EOF >$dummy.c ! #ifdef __dietlibc__ ! LIBC=dietlibc ! #endif ! EOF ! eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'` ! echo "${UNAME_MACHINE}-pc-linux-${LIBC}" exit ;; ia64:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; m32r*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; m68*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; mips:Linux:*:* | mips64:Linux:*:*) eval $set_cc_for_build --- 901,954 ---- EV68*) UNAME_MACHINE=alphaev68 ;; esac objdump --private-headers /bin/sh | grep -q ld.so.1 ! if test "$?" = 0 ; then LIBC="gnulibc1" ; fi ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ! exit ;; ! arc:Linux:*:* | arceb:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; arm*:Linux:*:*) eval $set_cc_for_build if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ | grep -q __ARM_EABI__ then ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} else if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \ | grep -q __ARM_PCS_VFP then ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi else ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf fi fi exit ;; avr32*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; cris:Linux:*:*) ! echo ${UNAME_MACHINE}-axis-linux-${LIBC} exit ;; crisv32:Linux:*:*) ! echo ${UNAME_MACHINE}-axis-linux-${LIBC} exit ;; frv:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; hexagon:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; i*86:Linux:*:*) ! echo ${UNAME_MACHINE}-pc-linux-${LIBC} exit ;; ia64:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; m32r*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; m68*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; mips:Linux:*:* | mips64:Linux:*:*) eval $set_cc_for_build *************** EOF *** 955,1008 **** #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'` ! test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } ;; or32:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; padre:Linux:*:*) ! echo sparc-unknown-linux-gnu exit ;; parisc64:Linux:*:* | hppa64:Linux:*:*) ! echo hppa64-unknown-linux-gnu exit ;; parisc:Linux:*:* | hppa:Linux:*:*) # Look for CPU level case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in ! PA7*) echo hppa1.1-unknown-linux-gnu ;; ! PA8*) echo hppa2.0-unknown-linux-gnu ;; ! *) echo hppa-unknown-linux-gnu ;; esac exit ;; ppc64:Linux:*:*) ! echo powerpc64-unknown-linux-gnu exit ;; ppc:Linux:*:*) ! echo powerpc-unknown-linux-gnu exit ;; s390:Linux:*:* | s390x:Linux:*:*) ! echo ${UNAME_MACHINE}-ibm-linux exit ;; sh64*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; sh*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; sparc:Linux:*:* | sparc64:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; tile*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; vax:Linux:*:*) ! echo ${UNAME_MACHINE}-dec-linux-gnu exit ;; x86_64:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; xtensa*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; i*86:DYNIX/ptx:4*:*) # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. --- 967,1029 ---- #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'` ! test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; } ;; + or1k:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; or32:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; padre:Linux:*:*) ! echo sparc-unknown-linux-${LIBC} exit ;; parisc64:Linux:*:* | hppa64:Linux:*:*) ! echo hppa64-unknown-linux-${LIBC} exit ;; parisc:Linux:*:* | hppa:Linux:*:*) # Look for CPU level case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in ! PA7*) echo hppa1.1-unknown-linux-${LIBC} ;; ! PA8*) echo hppa2.0-unknown-linux-${LIBC} ;; ! *) echo hppa-unknown-linux-${LIBC} ;; esac exit ;; ppc64:Linux:*:*) ! echo powerpc64-unknown-linux-${LIBC} exit ;; ppc:Linux:*:*) ! echo powerpc-unknown-linux-${LIBC} ! exit ;; ! ppc64le:Linux:*:*) ! echo powerpc64le-unknown-linux-${LIBC} ! exit ;; ! ppcle:Linux:*:*) ! echo powerpcle-unknown-linux-${LIBC} exit ;; s390:Linux:*:* | s390x:Linux:*:*) ! echo ${UNAME_MACHINE}-ibm-linux-${LIBC} exit ;; sh64*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; sh*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; sparc:Linux:*:* | sparc64:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; tile*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; vax:Linux:*:*) ! echo ${UNAME_MACHINE}-dec-linux-${LIBC} exit ;; x86_64:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; xtensa*:Linux:*:*) ! echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; i*86:DYNIX/ptx:4*:*) # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. *************** EOF *** 1235,1253 **** exit ;; *:Darwin:*:*) UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown ! case $UNAME_PROCESSOR in ! i386) ! eval $set_cc_for_build ! if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then ! if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ ! (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ ! grep IS_64BIT_ARCH >/dev/null ! then ! UNAME_PROCESSOR="x86_64" ! fi ! fi ;; ! unknown) UNAME_PROCESSOR=powerpc ;; ! esac echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} exit ;; *:procnto*:*:* | *:QNX:[0123456789]*:*) --- 1256,1276 ---- exit ;; *:Darwin:*:*) UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown ! eval $set_cc_for_build ! if test "$UNAME_PROCESSOR" = unknown ; then ! UNAME_PROCESSOR=powerpc ! fi ! if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then ! if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ ! (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ ! grep IS_64BIT_ARCH >/dev/null ! then ! case $UNAME_PROCESSOR in ! i386) UNAME_PROCESSOR=x86_64 ;; ! powerpc) UNAME_PROCESSOR=powerpc64 ;; ! esac ! fi ! fi echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} exit ;; *:procnto*:*:* | *:QNX:[0123456789]*:*) diff -Nrcpad gcc-4.8.2/config.sub gcc-4.8.3/config.sub *** gcc-4.8.2/config.sub Fri Jan 11 13:02:58 2013 --- gcc-4.8.3/config.sub Fri Apr 4 13:48:08 2014 *************** *** 1,10 **** #! /bin/sh # Configuration validation subroutine script. ! # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, ! # 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, ! # 2011, 2012, 2013 Free Software Foundation, Inc. ! timestamp='2013-01-11' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by --- 1,8 ---- #! /bin/sh # Configuration validation subroutine script. ! # Copyright 1992-2013 Free Software Foundation, Inc. ! timestamp='2013-10-01' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by *************** Report bugs and patches to + + * gcc_update (configure): Update to handle svn 1.8.1. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff -Nrcpad gcc-4.8.2/contrib/gcc_update gcc-4.8.3/contrib/gcc_update *** gcc-4.8.2/contrib/gcc_update Wed Nov 14 11:09:00 2012 --- gcc-4.8.3/contrib/gcc_update Mon Oct 21 10:38:03 2013 *************** case $vcs_type in *** 382,388 **** fi revision=`$GCC_SVN info | awk '/Revision:/ { print $2 }'` ! branch=`$GCC_SVN info | sed -ne "/URL:/ { s,.*/trunk,trunk, s,.*/branches/,, s,.*/tags/,, --- 382,388 ---- fi revision=`$GCC_SVN info | awk '/Revision:/ { print $2 }'` ! branch=`$GCC_SVN info | sed -ne "/^URL:/ { s,.*/trunk,trunk, s,.*/branches/,, s,.*/tags/,, diff -Nrcpad gcc-4.8.2/contrib/reghunt/ChangeLog gcc-4.8.3/contrib/reghunt/ChangeLog *** gcc-4.8.2/contrib/reghunt/ChangeLog Wed Oct 16 07:19:38 2013 --- gcc-4.8.3/contrib/reghunt/ChangeLog Thu May 22 09:07:04 2014 *************** *** 1,3 **** --- 1,7 ---- + 2014-05-22 Release Manager + + * GCC 4.8.3 released. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff -Nrcpad gcc-4.8.2/contrib/regression/ChangeLog gcc-4.8.3/contrib/regression/ChangeLog *** gcc-4.8.2/contrib/regression/ChangeLog Wed Oct 16 07:19:45 2013 --- gcc-4.8.3/contrib/regression/ChangeLog Thu May 22 09:06:54 2014 *************** *** 1,3 **** --- 1,7 ---- + 2014-05-22 Release Manager + + * GCC 4.8.3 released. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff -Nrcpad gcc-4.8.2/fixincludes/ChangeLog gcc-4.8.3/fixincludes/ChangeLog *** gcc-4.8.2/fixincludes/ChangeLog Wed Oct 16 07:17:59 2013 --- gcc-4.8.3/fixincludes/ChangeLog Thu May 22 09:08:00 2014 *************** *** 1,3 **** --- 1,7 ---- + 2014-05-22 Release Manager + + * GCC 4.8.3 released. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff -Nrcpad gcc-4.8.2/gcc/BASE-VER gcc-4.8.3/gcc/BASE-VER *** gcc-4.8.2/gcc/BASE-VER Fri May 31 10:44:33 2013 --- gcc-4.8.3/gcc/BASE-VER Wed Oct 16 09:33:10 2013 *************** *** 1 **** ! 4.8.2 --- 1 ---- ! 4.8.3 diff -Nrcpad gcc-4.8.2/gcc/ChangeLog gcc-4.8.3/gcc/ChangeLog *** gcc-4.8.2/gcc/ChangeLog Wed Oct 16 07:20:05 2013 --- gcc-4.8.3/gcc/ChangeLog Thu May 22 09:09:59 2014 *************** *** 1,3 **** --- 1,5483 ---- + 2014-05-22 Release Manager + + * GCC 4.8.3 released. + + 2014-05-15 Peter Bergner + + Backport from mainline + 2014-05-15 Peter Bergner + + PR target/61193 + * config/rs6000/htmxlintrin.h (_HTM_TBEGIN_STARTED): New define. + (__TM_simple_begin): Use it. + (__TM_begin): Likewise. + + 2014-05-14 Eric Botcazou + + * config/sparc/sparc-protos.h (sparc_absnegfloat_split_legitimate): + Delete. + * config/sparc/sparc.c (sparc_absnegfloat_split_legitimate): Likewise. + * config/sparc/sparc.md (fptype_ut699): New attribute. + (in_branch_delay): Return false if -mfix-ut699 is specified and + fptype_ut699 is set to single. + (truncdfsf2): Add fptype_ut699 attribute. + (fix_truncdfsi2): Likewise. + (floatsisf2): Change fptype attribute. + (fix_truncsfsi2): Likewise. + (negtf2_notv9): Delete. + (negtf2_v9): Likewise. + (negtf2_hq): New instruction. + (negtf2): New instruction and splitter. + (negdf2_notv9): Rewrite. + (abstf2_notv9): Delete. + (abstf2_hq_v9): Likewise. + (abstf2_v9): Likewise. + (abstf2_hq): New instruction. + (abstf2): New instruction and splitter. + (absdf2_notv9): Rewrite. + + 2014-05-14 Matthias Klose + + Revert: + 2014-05-08 Manuel López-Ibáñez + Matthias Klose + + PR driver/61106 + * optc-gen.awk: Fix option handling for -Wunused-parameter. + + 2014-05-13 Peter Bergner + + * doc/sourcebuild.texi: (dfp_hw): Document. + (p8vector_hw): Likewise. + (powerpc_eabi_ok): Likewise. + (powerpc_elfv2): Likewise. + (powerpc_htm_ok): Likewise. + (ppc_recip_hw): Likewise. + (vsx_hw): Likewise. + + 2014-05-12 Senthil Kumar Selvaraj + + Backport from mainline + 2014-05-12 Senthil Kumar Selvaraj + + PR target/60991 + * config/avr/avr.c (avr_out_store_psi): Use correct constant + to restore Y. + + 2014-05-09 Georg-Johann Lay + + Backport from 2014-05-09 trunk r210267 + + PR target/61055 + * config/avr/avr.md (cc): Add new attribute set_vzn. + (addqi3, addqq3, adduqq3, subqi3, subqq3, subuqq3, negqi2) [cc]: + Set cc insn attribute to set_vzn instead of set_zn for alternatives + with INC, DEC or NEG. + * config/avr/avr.c (avr_notice_update_cc): Handle SET_VZN. + (avr_out_plus_1): ADIW sets cc0 to CC_SET_CZN. + INC, DEC and ADD+ADC set cc0 to CC_CLOBBER. + + 2014-05-09 Richard Sandiford + + * builtins.c (expand_builtin_setjmp_receiver): Emit a use of + the hard frame pointer. Synchronize commentary with mainline. + * cse.c (cse_insn): Only check for volatile asms. + * cselib.c (cselib_process_insn): Likewise. + * dse.c (scan_insn): Likewise. + * stmt.c (expand_nl_goto_receiver): Emit a use and a clobber of + the hard frame pointer. + + 2014-05-08 Manuel López-Ibáñez + Matthias Klose + + PR driver/61106 + * optc-gen.awk: Fix option handling for -Wunused-parameter. + + 2014-05-08 Uros Bizjak + + PR target/59952 + * config/i386/i386.c (ix86_option_override_internal): Remove PTA_RTM + from core-avx2. + + 2014-05-08 Charles Baylis + + Backport from mainline + 2014-04-07 Charles Baylis + + PR target/60609 + * config/arm/arm.h (ASM_OUTPUT_CASE_END): Remove. + (LABEL_ALIGN_AFTER_BARRIER): Align barriers which occur after + ADDR_DIFF_VEC. + + 2014-05-06 Kyrylo Tkachov + + * config.gcc (aarch64*-*-*): Use ISA flags from aarch64-arches.def. + Do not define target_cpu_default2 to generic. + + 2014-05-06 Richard Biener + + Backport from mainline + 2014-04-14 Richard Biener + + PR middle-end/55022 + * fold-const.c (negate_expr_p): Don't negate directional rounding + division. + (fold_negate_expr): Likewise. + + 2014-05-06 Richard Biener + + Backport from mainline + 2014-04-17 Richard Biener + + PR middle-end/60849 + * tree-ssa-propagate.c (valid_gimple_rhs_p): Only allow effective + boolean results for comparisons. + + 2014-04-07 Richard Biener + + PR tree-optimization/60766 + * tree-ssa-loop-ivopts.c (cand_value_at): Compute in an + unsigned type. + (may_eliminate_iv): Convert cand_value_at result to desired + type. + + 2014-04-23 Richard Biener + + PR tree-optimization/60903 + * tree-ssa-loop-im.c (execute_sm_if_changed): Properly apply + IRREDUCIBLE_LOOP loop flags to newly created BBs and edges. + + 2014-05-05 Richard Biener + + Backport from mainline + 2014-04-23 Richard Biener + + PR middle-end/60895 + * tree-inline.c (declare_return_variable): Use mark_addressable. + + 2014-04-07 Richard Biener + + PR middle-end/60750 + * tree-ssa-operands.c (maybe_add_call_vops): Also add VDEFs + for noreturn calls. + * tree-cfgcleanup.c (fixup_noreturn_call): Do not remove VDEFs. + + 2014-04-14 Richard Biener + + PR tree-optimization/59817 + PR tree-optimization/60453 + * graphite-scop-detection.c (graphite_can_represent_scev): Complete + recursion to catch all CHRECs in the scalar evolution and restrict + the predicate for the remains appropriately. + + 2014-04-17 Richard Biener + + PR tree-optimization/60836 + * tree-vect-loop.c (vect_create_epilog_for_reduction): Force + initial PHI args to be gimple values. + + 2014-05-05 Jakub Jelinek + + Backported from mainline + 2014-04-25 Jakub Jelinek + + PR tree-optimization/60960 + * tree-vect-generic.c (expand_vector_operation): Only call + expand_vector_divmod if type's mode satisfies VECTOR_MODE_P. + + 2014-05-04 Peter Bergner + + * config/rs6000/rs6000.h (RS6000_BTM_HARD_FLOAT): New define. + (RS6000_BTM_COMMON): Add RS6000_BTM_HARD_FLOAT. + (TARGET_EXTRA_BUILTINS): Add TARGET_HARD_FLOAT. + * config/rs6000/rs6000-builtin.def (BU_MISC_1): + Use RS6000_BTM_HARD_FLOAT. + (BU_MISC_2): Likewise. + * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Handle + RS6000_BTM_HARD_FLOAT. + (rs6000_option_override_internal): Enforce -mhard-float if -mhard-dfp + is explicitly used. + (rs6000_invalid_builtin): Add hard floating builtin support. + (rs6000_expand_builtin): Relax the gcc_assert to allow the new + hard float builtins. + (rs6000_builtin_mask_names): Add RS6000_BTM_HARD_FLOAT. + + 2014-05-03 Joey Ye + + Backport from mainline r209463 + 2014-04-17 Joey Ye + + * opts.c (OPT_fif_conversion, OPT_fif_conversion2): Disable for Og. + + 2014-05-03 Oleg Endo + + Back port from mainline + PR target/61026 + * config/sh/sh.c: Include stdlib headers before everything else. + + 2014-05-02 Bill Schmidt + + PR tree-optimization/60930 + * gimple-ssa-strength-reduction.c (create_mul_imm_cand): Reject + creating a multiply candidate by folding two constant + multiplicands when the result overflows. + + 2014-05-02 Kyrylo Tkachov + + * config/aarch64/aarch64.h (TARGET_SIMD): Take AARCH64_ISA_SIMD + into account. + (TARGET_FLOAT): Take AARCH64_ISA_FP into account. + + 2014-04-30 Michael Meissner + + Back port from mainline + 2014-04-24 Michael Meissner + + * doc/extend.texi (PowerPC Built-in Functions): Document new + powerpc extended divide, bcd, pack/unpack 128-bit, builtin + functions. + (PowerPC AltiVec/VSX Built-in Functions): Likewise. + + * config/rs6000/predicates.md (const_0_to_3_operand): New + predicate to match 0..3 integer constants. + + * config/rs6000/rs6000-builtin.def (BU_DFP_MISC_1): Add new macros + to support adding miscellaneous builtin functions. + (BU_DFP_MISC_2): Likewise. + (BU_P7_MISC_1): Likewise. + (BU_P7_MISC_2): Likewise. + (BU_P8V_MISC_3): Likewise. + (BU_MISC_1): Likewise. + (BU_MISC_2): Likewise. + (DIVWE): Add extended divide builtin functions. + (DIVWEO): Likewise. + (DIVWEU): Likewise. + (DIVWEUO): Likewise. + (DIVDE): Likewise. + (DIVDEO): Likewise. + (DIVDEU): Likewise. + (DIVDEUO): Likewise. + (DXEX): Add decimal floating-point builtin functions. + (DXEXQ): Likewise. + (DDEDPD): Likewise. + (DDEDPDQ): Likewise. + (DENBCD): Likewise. + (DENBCDQ): Likewise. + (DIEX): Likewise. + (DIEXQ): Likewise. + (DSCLI): Likewise. + (DSCLIQ): Likewise. + (DSCRI): Likewise. + (DSCRIQ): Likewise. + (CDTBCD): Add new BCD builtin functions. + (CBCDTD): Likewise. + (ADDG6S): Likewise. + (BCDADD): Likewise. + (BCDADD_LT): Likewise. + (BCDADD_EQ): Likewise. + (BCDADD_GT): Likewise. + (BCDADD_OV): Likewise. + (BCDSUB): Likewise. + (BCDSUB_LT): Likewise. + (BCDSUB_EQ): Likewise. + (BCDSUB_GT): Likewise. + (BCDSUB_OV): Likewise. + (PACK_TD): Add new pack/unpack 128-bit type builtin functions. + (UNPACK_TD): Likewise. + (PACK_TF): Likewise. + (UNPACK_TF): Likewise. + (UNPACK_TF_0): Likewise. + (UNPACK_TF_1): Likewise. + (PACK_V1TI): Likewise. + (UNPACK_V1TI): Likewise. + + * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add + support for decimal floating point builtin functions. + (rs6000_expand_ternop_builtin): Add checks for the new builtin + functions that take constant arguments. + (rs6000_invalid_builtin): Add decimal floating point builtin + support. + (rs6000_init_builtins): Setup long double, _Decimal64, and + _Decimal128 types for new builtin functions. + (builtin_function_type): Set the unsigned flags appropriately for + the new builtin functions. + (rs6000_opt_masks): Add support for decimal floating point builtin + functions. + + * config/rs6000/rs6000.h (RS6000_BTM_DFP): Add support for decimal + floating point builtin functions. + (RS6000_BTM_COMMON): Likewise. + (RS6000_BTI_long_double): Likewise. + (RS6000_BTI_dfloat64): Likewise. + (RS6000_BTI_dfloat128): Likewise. + (long_double_type_internal_node): Likewise. + (dfloat64_type_internal_node): Likewise. + (dfloat128_type_internal_node): Likewise. + + * config/rs6000/altivec.h (UNSPEC_BCDADD): Add support for ISA + 2.07 bcd arithmetic instructions. + (UNSPEC_BCDSUB): Likewise. + (UNSPEC_BCD_OVERFLOW): Likewise. + (UNSPEC_BCD_ADD_SUB): Likewise. + (bcd_add_sub): Likewise. + (BCD_TEST): Likewise. + (bcd): Likewise. + (bcd_test): Likewise. + (bcd_test2): Likewise. + (bcd_): Likewise. + (peephole2 for combined bcd ops): Likewise. + + * config/rs6000/dfp.md (UNSPEC_DDEDPD): Add support for new + decimal floating point builtin functions. + (UNSPEC_DENBCD): Likewise. + (UNSPEC_DXEX): Likewise. + (UNSPEC_DIEX): Likewise. + (UNSPEC_DSCLI): Likewise. + (UNSPEC_DSCRI): Likewise. + (D64_D128): Likewise. + (dfp_suffix): Likewise. + (dfp_ddedpd_): Likewise. + (dfp_denbcd_): Likewise. + (dfp_dxex_): Likewise. + (dfp_diex_): Likewise. + (dfp_dscli_): Likewise. + (dfp_dscri_): Likewise. + + * config/rs6000/rs6000.md (UNSPEC_ADDG6S): Add support for new BCD + builtin functions. + (UNSPEC_CDTBCD): Likewise. + (UNSPEC_CBCDTD): Likewise. + (UNSPEC_DIVE): Add support for new extended divide builtin + functions. + (UNSPEC_DIVEO): Likewise. + (UNSPEC_DIVEU): Likewise. + (UNSPEC_DIVEUO): Likewise. + (UNSPEC_UNPACK_128BIT): Add support for new builtin functions to + pack/unpack 128-bit types. + (UNSPEC_PACK_128BIT): Likewise. + (idiv_ldiv): New mode attribute to set the 32/64-bit divide type. + (udiv3): Use idiv_ldiv mode attribute. + (div3): Likewise. + (addg6s): Add new BCD builtin functions. + (cdtbcd): Likewise. + (cbcdtd): Likewise. + (UNSPEC_DIV_EXTEND): Add support for new extended divide + instructions. + (div_extend): Likewise. + (div_"): Likewise. + (FP128_64): Add support for new builtin functions to pack/unpack + 128-bit types. + (unpack): Likewise. + (unpacktf_0): Likewise. + (unpacktf_1): Likewise. + (unpack_dm): Likewise. + (unpack_nodm): Likewise. + (pack): Likewise. + (unpackv1ti): Likewise. + (packv1ti): Likewise. + + 2014-04-29 Pat Haugen + + Backport from mainline + 2014-04-17 Pat Haugen + + * config/rs6000/rs6000.md (addti3, subti3): New. + + 2014-04-28 Pat Haugen + + Backport from mainline + 2014-04-28 Pat Haugen + + * config/rs6000/sync.md (AINT mode_iterator): Move definition. + (loadsync_): Change mode. + (load_quadpti, store_quadpti): New. + (atomic_load, atomic_store): Add support for TI mode. + * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. + + 2014-04-28 Eric Botcazou + + * configure.ac: Tweak GAS check for LEON instructions on SPARC. + * configure: Regenerate. + * config/sparc/sparc.opt (muser-mode): New option. + * config/sparc/sync.md (atomic_compare_and_swap_1): Do not enable + for LEON3. + (atomic_compare_and_swap_leon3_1): New instruction for LEON3. + * doc/invoke.texi (SPARC options): Document -muser-mode. + + 2014-04-25 Eric Botcazou + + PR target/60941 + * config/sparc/sparc.md (ashlsi3_extend): Delete. + + 2014-04-22 Michael Meissner + + Back port from main line: + 2014-03-27 Michael Meissner + + * config/rs6000/rs6000-builtins.def (VBPERMQ): Add vbpermq builtin + for ISA 2.07. + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + vbpermq builtins. + + * config/rs6000/altivec.md (UNSPEC_VBPERMQ): Add support for the + vbpermq instruction. + (altivec_vbpermq): Likewise. + + PR target/60672 + * config/rs6000/altivec.h (vec_xxsldwi): Add missing define to + enable use of xxsldwi and xxpermdi builtin functions. + (vec_xxpermdi): Likewise. + + * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): + Document use of vec_xxsldwi and vec_xxpermdi builtins. + + 2014-04-23 Uros Bizjak + + Backport from mainline + 2014-04-21 Uros Bizjak + + PR target/60909 + * config/i386/i386.c (ix86_expand_builtin) + : Use temporary + register for target RTX. + : Ditto. + + 2014-04-23 Richard Biener + + Backport from mainline + 2014-04-02 Richard Biener + + PR middle-end/60729 + * optabs.c (expand_abs_nojump): Honor flag_trapv only for + MODE_INTs. Properly use negv_optab. + (expand_abs): Likewise. + + 2014-04-03 Richard Biener + + PR tree-optimization/60740 + * graphite-scop-detection.c (stmt_simple_for_scop_p): Iterate + over all GIMPLE_COND operands. + + 2014-04-23 Richard Biener + + PR middle-end/60635 + * gimplify.c (gimple_regimplify_operands): Update the + re-gimplifed stmt. + + 2014-04-21 Michael Meissner + + Back port from the trunk, subversion id 209546. + + 2014-04-21 Michael Meissner + + PR target/60735 + * config/rs6000/rs6000.md (mov_softfloat32, FMOVE64 case): + If mode is DDmode and TARGET_E500_DOUBLE allow move. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print some + more debug information for E500 if -mdebug=reg. + + 2014-04-18 Richard Henderson + + * config/aarch64/aarch64.c (aarch64_register_move_cost): Pass a mode + to GET_MODE_SIZE, not a reg_class_t. + + 2014-04-17 Bill Schmidt + + * config/rs6000/vsx.md (vsx_xxmrghw_): Adjust for + little-endian. + (vsx_xxmrglw_): Likewise. + + 2014-04-15 Bill Schmidt + + PR target/60839 + Revert the following patch + + 2014-04-04 Bill Schmidt + + Back port mainline subversion id 209025. + 2014-04-02 Michael Meissner + + PR target/60735 + * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have + software floating point or no floating point registers, do not + allow any type in the FPRs. Eliminate a test for SPE SIMD types + in GPRs that occurs after we tested for GPRs that would never be + true. + + * config/rs6000/rs6000.md (mov_softfloat32, FMOVE64): + Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE, + since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE, + specifically allow DDmode, since that does not use the SPE SIMD + instructions. + + 2014-04-10 Vladimir Makarov + + PR rtl-optimization/60769 + * lra-constraints.c (simplify_operand_subreg): Force reload of + paradoxical subreg if it is not in the class contents. + + 2014-04-10 Jakub Jelinek + + Backport from mainline + 2014-03-12 Jakub Jelinek + Marc Glisse + + PR tree-optimization/60502 + * tree-ssa-reassoc.c (eliminate_not_pairs): Use build_all_ones_cst + instead of build_low_bits_mask. + + 2013-06-13 Marc Glisse + + * tree.c (build_all_ones_cst): New function. + * tree.h (build_all_ones_cst): Declare it. + + 2013-05-10 Marc Glisse + + * tree.c (build_minus_one_cst): New function. + * tree.h (build_minus_one_cst): Declare new function. + + 2014-04-10 Jakub Jelinek + + Backport from mainline + 2014-03-28 Jakub Jelinek + + PR target/60693 + * config/i386/i386.c (ix86_copy_addr_to_reg): Call copy_addr_to_reg + also if addr has VOIDmode. + + 2014-03-17 Jakub Jelinek + + PR target/60516 + * config/i386/i386.c (ix86_expand_epilogue): Adjust REG_CFA_ADJUST_CFA + note creation for the 2010-08-31 changes. + + 2014-03-06 Jakub Jelinek + Meador Inge + + PR target/58595 + * config/arm/arm.c (arm_tls_symbol_p): Remove. + (arm_legitimize_address): Call legitimize_tls_address for any + arm_tls_referenced_p expression, handle constant addend. Call it + before testing for !TARGET_ARM. + (thumb_legitimize_address): Don't handle arm_tls_symbol_p here. + + 2014-04-09 Bill Schmidt + + Backport from mainline r208750 + 2014-03-21 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_expand_vector_set): Generate a + pattern for vector nor instead of subtract from splat(-1). + (altivec_expand_vec_perm_const_le): Likewise. + + Backport from mainline r209235 + 2014-04-08 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_expand_vector_set): Use vnand + instead of vnor to exploit possible fusion opportunity in the + future. + (altivec_expand_vec_perm_const_le): Likewise. + + 2014-04-09 Bill Schmidt + + Revert following patch + 2014-04-08 Pat Haugen + + Backport from mainline + 2014-04-08 Pat Haugen + + * config/rs6000/sync.md (AINT mode_iterator): Move definition. + (loadsync_): Change mode. + (load_quadpti, store_quadpti): New. + (atomic_load, atomic_store): Add support for TI mode. + * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. + + 2014-04-09 Bill Schmidt + + Backport from mainline r202642 + 2013-09-17 Alan Modra + + PR target/57589 + * config/rs6000/driver-rs6000.c (elf_platform): Revert 2013-06-11 + patch (r199972). + + 2014-04-08 Pat Haugen + + Backport from mainline + 2014-04-08 Pat Haugen + + * config/rs6000/sync.md (AINT mode_iterator): Move definition. + (loadsync_): Change mode. + (load_quadpti, store_quadpti): New. + (atomic_load, atomic_store): Add support for TI mode. + * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. + + 2014-04-07 Martin Jambor + + PR ipa/60640 + * ipa-cp.c (propagate_constants_accross_call): Do not propagate + accross thunks. + + 2014-04-07 Dominique d'Humieres + + Backport from mainline + 2013-09-14 Iain Sandoe + + PR target/48094 + * config/darwin.c (darwin_objc2_section): Note if ObjC Metadata + is seen. + (darwin_objc1_section): Likewise. + (darwin_file_end): Emit Image Info section when required. + + 2014-04-05 Alan Modra + + Apply from mainline + 2014-01-28 Alan Modra + * Makefile.in (BUILD_CPPFLAGS): Do not use ALL_CPPFLAGS. + * configure.ac : Define + GENERATOR_FILE. Comment. Use CXX_FOR_BUILD, CXXFLAGS_FOR_BUILD + and LD_FOR_BUILD too. + * configure: Regenerate. + + 2014-04-04 Ulrich Weigand + + Backport from mainline r208895: + 2014-03-28 Ulrich Weigand + + * config/rs6000/rs6000.c (fusion_gpr_load_p): Refuse optimization + if it would clobber the stack pointer, even temporarily. + + 2014-04-04 Bill Schmidt + + Back port from main line: + 2014-04-01 Michael Meissner + + * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): + Document vec_vgbbd. + + 2014-04-04 Bill Schmidt + + Back port mainline subversion id 209025. + 2014-04-02 Michael Meissner + + PR target/60735 + * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have + software floating point or no floating point registers, do not + allow any type in the FPRs. Eliminate a test for SPE SIMD types + in GPRs that occurs after we tested for GPRs that would never be + true. + + * config/rs6000/rs6000.md (mov_softfloat32, FMOVE64): + Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE, + since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE, + specifically allow DDmode, since that does not use the SPE SIMD + instructions. + + 2014-04-04 Bill Schmidt + + Backport from mainline r205308 + 2013-11-23 David Edelsohn + + * config/rs6000/rs6000.c (IN_NAMED_SECTION): New macro. + (rs6000_xcoff_select_section): Place decls with stricter alignment + into named sections. + (rs6000_xcoff_unique_section): Allow unique sections for + uninitialized data with strict alignment. + + 2014-04-04 Bill Schmidt + + Backport from mainline + 2013-11-15 Ulrich Weigand + + * gcc/configure: Regenerate. + + 2014-04-04 Bill Schmidt + + Back port from trunk + 2013-04-25 Alan Modra + + PR target/57052 + * config/rs6000/rs6000.md (rotlsi3_internal7): Rename to + rotlsi3_internal7le and condition on !BYTES_BIG_ENDIAN. + (rotlsi3_internal8be): New BYTES_BIG_ENDIAN insn. + Repeat for many other rotate/shift and mask patterns using subregs. + Name lshiftrt insns. + (ashrdisi3_noppc64): Rename to ashrdisi3_noppc64be and condition + on WORDS_BIG_ENDIAN. + + 2013-06-07 Alan Modra + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't + override user -mfp-in-toc. + (offsettable_ok_by_alignment): Consider just the current access + rather than the whole object, unless BLKmode. Handle + CONSTANT_POOL_ADDRESS_P constants that lack a decl too. + (use_toc_relative_ref): Allow CONSTANT_POOL_ADDRESS_P constants + for -mcmodel=medium. + * config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Don't + override user -mfp-in-toc or -msum-in-toc. Default to + -mno-fp-in-toc for -mcmodel=medium. + + 2013-06-18 Alan Modra + + * config/rs6000/rs6000.h (enum data_align): New. + (LOCAL_ALIGNMENT, DATA_ALIGNMENT): Use rs6000_data_alignment. + (DATA_ABI_ALIGNMENT): Define. + (CONSTANT_ALIGNMENT): Correct comment. + * config/rs6000/rs6000-protos.h (rs6000_data_alignment): Declare. + * config/rs6000/rs6000.c (rs6000_data_alignment): New function. + + 2013-07-11 Ulrich Weigand + + * config/rs6000/rs6000.md (""*tls_gd_low"): + Require GOT register as additional operand in UNSPEC. + ("*tls_ld_low"): Likewise. + ("*tls_got_dtprel_low"): Likewise. + ("*tls_got_tprel_low"): Likewise. + ("*tls_gd"): Update splitter. + ("*tls_ld"): Likewise. + ("tls_got_dtprel_"): Likewise. + ("tls_got_tprel_"): Likewise. + + 2014-01-23 Pat Haugen + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't + force flag_ira_loop_pressure if set via command line. + + 2014-02-06 Alan Modra + + PR target/60032 + * config/rs6000/rs6000.c (rs6000_secondary_memory_needed_mode): Only + change SDmode to DDmode when lra_in_progress. + + 2014-04-04 Bill Schmidt + + V1TImode Support + Back port from trunk + 2014-03-12 Michael Meissner + + * config/rs6000/vector.md (VEC_L): Add V1TI mode to vector types. + (VEC_M): Likewise. + (VEC_N): Likewise. + (VEC_R): Likewise. + (VEC_base): Likewise. + (mov, VEC_M modes): If we are loading TImode into VSX + registers, we need to swap double words in little endian mode. + + * config/rs6000/rs6000-modes.def (V1TImode): Add new vector mode + to be a container mode for 128-bit integer operations added in ISA + 2.07. Unlike TImode and PTImode, the preferred register set is + the Altivec/VMX registers for the 128-bit operations. + + * config/rs6000/rs6000-protos.h (rs6000_move_128bit_ok_p): Add + declarations. + (rs6000_split_128bit_ok_p): Likewise. + + * config/rs6000/rs6000-builtin.def (BU_P8V_AV_3): Add new support + macros for creating ISA 2.07 normal and overloaded builtin + functions with 3 arguments. + (BU_P8V_OVERLOAD_3): Likewise. + (VPERM_1T): Add support for V1TImode in 128-bit vector operations + for use as overloaded functions. + (VPERM_1TI_UNS): Likewise. + (VSEL_1TI): Likewise. + (VSEL_1TI_UNS): Likewise. + (ST_INTERNAL_1ti): Likewise. + (LD_INTERNAL_1ti): Likewise. + (XXSEL_1TI): Likewise. + (XXSEL_1TI_UNS): Likewise. + (VPERM_1TI): Likewise. + (VPERM_1TI_UNS): Likewise. + (XXPERMDI_1TI): Likewise. + (SET_1TI): Likewise. + (LXVD2X_V1TI): Likewise. + (STXVD2X_V1TI): Likewise. + (VEC_INIT_V1TI): Likewise. + (VEC_SET_V1TI): Likewise. + (VEC_EXT_V1TI): Likewise. + (EQV_V1TI): Likewise. + (NAND_V1TI): Likewise. + (ORC_V1TI): Likewise. + (VADDCUQ): Add support for 128-bit integer arithmetic instructions + added in ISA 2.07. Add both normal 'altivec' builtins, and the + overloaded builtin. + (VADDUQM): Likewise. + (VSUBCUQ): Likewise. + (VADDEUQM): Likewise. + (VADDECUQ): Likewise. + (VSUBEUQM): Likewise. + (VSUBECUQ): Likewise. + + * config/rs6000/rs6000-c.c (__int128_type): New static to hold + __int128_t and __uint128_t types. + (__uint128_type): Likewise. + (altivec_categorize_keyword): Add support for vector __int128_t, + vector __uint128_t, vector __int128, and vector unsigned __int128 + as a container type for TImode operations that need to be done in + VSX/Altivec registers. + (rs6000_macro_to_expand): Likewise. + (altivec_overloaded_builtins): Add ISA 2.07 overloaded functions + to support 128-bit integer instructions vaddcuq, vadduqm, + vaddecuq, vaddeuqm, vsubcuq, vsubuqm, vsubecuq, vsubeuqm. + (altivec_resolve_overloaded_builtin): Add support for V1TImode. + + * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Add support + for V1TImode, and set up preferences to use VSX/Altivec + registers. Setup VSX reload handlers. + (rs6000_debug_reg_global): Likewise. + (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_preferred_simd_mode): Likewise. + (vspltis_constant): Do not allow V1TImode as easy altivec + constants. + (easy_altivec_constant): Likewise. + (output_vec_const_move): Likewise. + (rs6000_expand_vector_set): Convert V1TImode set and extract to + simple move. + (rs6000_expand_vector_extract): Likewise. + (reg_offset_addressing_ok_p): Setup V1TImode to use VSX reg+reg + addressing. + (rs6000_const_vec): Add support for V1TImode. + (rs6000_emit_le_vsx_load): Swap double words when loading or + storing TImode/V1TImode. + (rs6000_emit_le_vsx_store): Likewise. + (rs6000_emit_le_vsx_move): Likewise. + (rs6000_emit_move): Add support for V1TImode. + (altivec_expand_ld_builtin): Likewise. + (altivec_expand_st_builtin): Likewise. + (altivec_expand_vec_init_builtin): Likewise. + (altivec_expand_builtin): Likewise. + (rs6000_init_builtins): Add support for V1TImode type. Add + support for ISA 2.07 128-bit integer builtins. Define type names + for the VSX/Altivec vector types. + (altivec_init_builtins): Add support for overloaded vector + functions with V1TImode type. + (rs6000_preferred_reload_class): Prefer Altivec registers for + V1TImode. + (rs6000_move_128bit_ok_p): Move 128-bit move/split validation to + external function. + (rs6000_split_128bit_ok_p): Likewise. + (rs6000_handle_altivec_attribute): Create V1TImode from vector + __int128_t and vector __uint128_t. + + * config/rs6000/vsx.md (VSX_L): Add V1TImode to vector iterators + and mode attributes. + (VSX_M): Likewise. + (VSX_M2): Likewise. + (VSm): Likewise. + (VSs): Likewise. + (VSr): Likewise. + (VSv): Likewise. + (VS_scalar): Likewise. + (VS_double): Likewise. + (vsx_set_v1ti): New builtin function to create V1TImode from + TImode. + + * config/rs6000/rs6000.h (TARGET_VADDUQM): New macro to say + whether we support the ISA 2.07 128-bit integer arithmetic + instructions. + (ALTIVEC_OR_VSX_VECTOR_MODE): Add V1TImode. + (enum rs6000_builtin_type_index): Add fields to hold V1TImode + and TImode types for use with the builtin functions. + (V1TI_type_node): Likewise. + (unsigned_V1TI_type_node): Likewise. + (intTI_type_internal_node): Likewise. + (uintTI_type_internal_node): Likewise. + + * config/rs6000/altivec.md (UNSPEC_VADDCUQ): New unspecs for ISA + 2.07 128-bit builtin functions. + (UNSPEC_VADDEUQM): Likewise. + (UNSPEC_VADDECUQ): Likewise. + (UNSPEC_VSUBCUQ): Likewise. + (UNSPEC_VSUBEUQM): Likewise. + (UNSPEC_VSUBECUQ): Likewise. + (VM): Add V1TImode to vector mode iterators. + (VM2): Likewise. + (VI_unit): Likewise. + (altivec_vadduqm): Add ISA 2.07 128-bit binary builtins. + (altivec_vaddcuq): Likewise. + (altivec_vsubuqm): Likewise. + (altivec_vsubcuq): Likewise. + (altivec_vaddeuqm): Likewise. + (altivec_vaddecuq): Likewise. + (altivec_vsubeuqm): Likewise. + (altivec_vsubecuq): Likewise. + + * config/rs6000/rs6000.md (FMOVE128_GPR): Add V1TImode to vector + mode iterators. + (BOOL_128): Likewise. + (BOOL_REGS_OUTPUT): Likewise. + (BOOL_REGS_OP1): Likewise. + (BOOL_REGS_OP2): Likewise. + (BOOL_REGS_UNARY): Likewise. + (BOOL_REGS_AND_CR0): Likewise. + + * config/rs6000/altivec.h (vec_vaddcuq): Add support for ISA 2.07 + 128-bit integer builtin support. + (vec_vadduqm): Likewise. + (vec_vaddecuq): Likewise. + (vec_vaddeuqm): Likewise. + (vec_vsubecuq): Likewise. + (vec_vsubeuqm): Likewise. + (vec_vsubcuq): Likewise. + (vec_vsubuqm): Likewise. + + * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): + Document vec_vaddcuq, vec_vadduqm, vec_vaddecuq, vec_vaddeuqm, + vec_subecuq, vec_subeuqm, vec_vsubcuq, vec_vsubeqm builtins adding + 128-bit integer add/subtract to ISA 2.07. + + 2014-04-04 Bill Schmidt + + Apply mainline r207798 + 2014-02-26 Alan Modra + PR target/58675 + PR target/57935 + * config/rs6000/rs6000.c (rs6000_secondary_reload_inner): Use + find_replacement on parts of insn rtl that might be reloaded. + + Backport from mainline r208287 + 2014-03-03 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_preferred_reload_class): Disallow + reload of PLUS rtx's outside of GENERAL_REGS or BASE_REGS; relax + constraint on constants to permit them being loaded into + GENERAL_REGS or BASE_REGS. + + 2014-04-04 Bill Schmidt + + Backport from mainline r207699. + 2014-02-11 Michael Meissner + + PR target/60137 + * config/rs6000/rs6000.md (128-bit GPR splitter): Add a splitter + for VSX/Altivec vectors that land in GPR registers. + + Backport from mainline r207808. + 2014-02-15 Michael Meissner + + PR target/60203 + * config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints. + (mov_internal, TFmode/TDmode): Split TFmode/TDmode moves + into 64-bit and 32-bit moves. On 64-bit moves, add support for + using direct move instructions on ISA 2.07. Also adjust + instruction length for 64-bit. + (mov_64bit, TFmode/TDmode): Likewise. + (mov_32bit, TFmode/TDmode): Likewise. + + Backport from mainline r207868. + 2014-02-18 Michael Meissner + + PR target/60203 + * config/rs6000/rs6000.md (mov_64bit, TF/TDmode moves): + Split 64-bit moves into 2 patterns. Do not allow the use of + direct move for TDmode in little endian, since the decimal value + has little endian bytes within a word, but the 64-bit pieces are + ordered in a big endian fashion, and normal subreg's of TDmode are + not allowed. + (mov_64bit_dm): Likewise. + (movtd_64bit_nodm): Likewise. + + 2014-04-04 Bill Schmidt + + Backport from mainline r207658 + 2014-02-06 Ulrich Weigand + + * config/rs6000/sysv4.h (ENDIAN_SELECT): Do not attempt to enforce + big-endian mode for -mcall-aixdesc, -mcall-freebsd, -mcall-netbsd, + -mcall-openbsd, or -mcall-linux. + (CC1_ENDIAN_BIG_SPEC): Remove. + (CC1_ENDIAN_LITTLE_SPEC): Remove. + (CC1_ENDIAN_DEFAULT_SPEC): Remove. + (CC1_SPEC): Remove (always empty) %cc1_endian_... spec. + (SUBTARGET_EXTRA_SPECS): Remove %cc1_endian_big, %cc1_endian_little, + and %cc1_endian_default. + * config/rs6000/sysv4le.h (CC1_ENDIAN_DEFAULT_SPEC): Remove. + + 2014-04-04 Bill Schmidt + + Little Endian Vector API Support + Backport from mainline r206443 + 2014-01-08 Bill Schmidt + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Remove + two duplicate entries. + + Backport from mainline r206494 + 2014-01-09 Bill Schmidt + + * doc/invoke.texi: Add -maltivec={be,le} options, and document + default element-order behavior for -maltivec. + * config/rs6000/rs6000.opt: Add -maltivec={be,le} options. + * config/rs6000/rs6000.c (rs6000_option_override_internal): Ensure + that -maltivec={le,be} implies -maltivec; disallow -maltivec=le + when targeting big endian, at least for now. + * config/rs6000/rs6000.h: Add #define of VECTOR_ELT_ORDER_BIG. + + Backport from mainline r206541 + 2014-01-10 Bill Schmidt + + * config/rs6000/rs6000-builtin.def: Fix pasto for VPKSDUS. + + Backport from mainline r206590 + 2014-01-13 Bill Schmidt + + * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): + Implement -maltivec=be for vec_insert and vec_extract. + + Backport from mainline r206641 + 2014-01-15 Bill Schmidt + + * config/rs6000/altivec.md (mulv8hi3): Explicitly generate vmulesh + and vmulosh rather than call gen_vec_widen_smult_*. + (vec_widen_umult_even_v16qi): Test VECTOR_ELT_ORDER_BIG rather + than BYTES_BIG_ENDIAN to determine use of even or odd instruction. + (vec_widen_smult_even_v16qi): Likewise. + (vec_widen_umult_even_v8hi): Likewise. + (vec_widen_smult_even_v8hi): Likewise. + (vec_widen_umult_odd_v16qi): Likewise. + (vec_widen_smult_odd_v16qi): Likewise. + (vec_widen_umult_odd_v8hi): Likewise. + (vec_widen_smult_odd_v8hi): Likewise. + (vec_widen_umult_hi_v16qi): Explicitly generate vmuleub and + vmuloub rather than call gen_vec_widen_umult_*. + (vec_widen_umult_lo_v16qi): Likewise. + (vec_widen_smult_hi_v16qi): Explicitly generate vmulesb and + vmulosb rather than call gen_vec_widen_smult_*. + (vec_widen_smult_lo_v16qi): Likewise. + (vec_widen_umult_hi_v8hi): Explicitly generate vmuleuh and vmulouh + rather than call gen_vec_widen_umult_*. + (vec_widen_umult_lo_v8hi): Likewise. + (vec_widen_smult_hi_v8hi): Explicitly gnerate vmulesh and vmulosh + rather than call gen_vec_widen_smult_*. + (vec_widen_smult_lo_v8hi): Likewise. + + Backport from mainline r207062 + 2014-01-24 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_expand_vec_perm_const_1): Remove + correction for little endian... + * config/rs6000/vsx.md (vsx_xxpermdi2__1): ...and move it to + here. + + Backport from mainline r207262 + 2014-01-29 Bill Schmidt + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Use + CODE_FOR_altivec_vmrg*_direct rather than CODE_FOR_altivec_vmrg*. + * config/rs6000/vsx.md (vsx_mergel_): Adjust for + -maltivec=be with LE targets. + (vsx_mergeh_): Likewise. + * config/rs6000/altivec.md (UNSPEC_VMRG[HL]_DIRECT): New + unspecs. + (mulv8hi3): Use gen_altivec_vmrg[hl]w_direct. + (altivec_vmrghb): Replace with define_expand and new + *altivec_vmrghb_internal insn; adjust for -maltivec=be with LE + targets. + (altivec_vmrghb_direct): New define_insn. + (altivec_vmrghh): Replace with define_expand and new + *altivec_vmrghh_internal insn; adjust for -maltivec=be with LE + targets. + (altivec_vmrghh_direct): New define_insn. + (altivec_vmrghw): Replace with define_expand and new + *altivec_vmrghw_internal insn; adjust for -maltivec=be with LE + targets. + (altivec_vmrghw_direct): New define_insn. + (*altivec_vmrghsf): Adjust for endianness. + (altivec_vmrglb): Replace with define_expand and new + *altivec_vmrglb_internal insn; adjust for -maltivec=be with LE + targets. + (altivec_vmrglb_direct): New define_insn. + (altivec_vmrglh): Replace with define_expand and new + *altivec_vmrglh_internal insn; adjust for -maltivec=be with LE + targets. + (altivec_vmrglh_direct): New define_insn. + (altivec_vmrglw): Replace with define_expand and new + *altivec_vmrglw_internal insn; adjust for -maltivec=be with LE + targets. + (altivec_vmrglw_direct): New define_insn. + (*altivec_vmrglsf): Adjust for endianness. + (vec_widen_umult_hi_v16qi): Use gen_altivec_vmrghh_direct. + (vec_widen_umult_lo_v16qi): Use gen_altivec_vmrglh_direct. + (vec_widen_smult_hi_v16qi): Use gen_altivec_vmrghh_direct. + (vec_widen_smult_lo_v16qi): Use gen_altivec_vmrglh_direct. + (vec_widen_umult_hi_v8hi): Use gen_altivec_vmrghw_direct. + (vec_widen_umult_lo_v8hi): Use gen_altivec_vmrglw_direct. + (vec_widen_smult_hi_v8hi): Use gen_altivec_vmrghw_direct. + (vec_widen_smult_lo_v8hi): Use gen_altivec_vmrglw_direct. + + Backport from mainline r207318 + 2014-01-30 Bill Schmidt + + * gcc/config/rs6000/rs6000.c (rs6000_expand_vector_init): Use + gen_vsx_xxspltw_v4sf_direct instead of gen_vsx_xxspltw_v4sf; + remove element index adjustment for endian (now handled in vsx.md + and altivec.md). + (altivec_expand_vec_perm_const): Use + gen_altivec_vsplt[bhw]_direct instead of gen_altivec_vsplt[bhw]. + * gcc/config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTW): New unspec. + (vsx_xxspltw_): Adjust element index for little endian. + * gcc/config/rs6000/altivec.md (altivec_vspltb): Divide into a + define_expand and a new define_insn *altivec_vspltb_internal; + adjust for -maltivec=be on a little endian target. + (altivec_vspltb_direct): New. + (altivec_vsplth): Divide into a define_expand and a new + define_insn *altivec_vsplth_internal; adjust for -maltivec=be on a + little endian target. + (altivec_vsplth_direct): New. + (altivec_vspltw): Divide into a define_expand and a new + define_insn *altivec_vspltw_internal; adjust for -maltivec=be on a + little endian target. + (altivec_vspltw_direct): New. + (altivec_vspltsf): Divide into a define_expand and a new + define_insn *altivec_vspltsf_internal; adjust for -maltivec=be on + a little endian target. + + Backport from mainline r207326 + 2014-01-30 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_expand_vector_init): Remove + unused variable "field". + * config/rs6000/vsx.md (vsx_mergel_): Add missing DONE. + (vsx_mergeh_): Likewise. + * config/rs6000/altivec.md (altivec_vmrghb): Likewise. + (altivec_vmrghh): Likewise. + (altivec_vmrghw): Likewise. + (altivec_vmrglb): Likewise. + (altivec_vmrglh): Likewise. + (altivec_vmrglw): Likewise. + (altivec_vspltb): Add missing uses. + (altivec_vsplth): Likewise. + (altivec_vspltw): Likewise. + (altivec_vspltsf): Likewise. + + Backport from mainline r207414 + 2014-02-02 Bill Schmidt + + * config/rs6000/altivec.md (UNSPEC_VSUMSWS_DIRECT): New unspec. + (altivec_vsumsws): Add handling for -maltivec=be with a little + endian target. + (altivec_vsumsws_direct): New. + (reduc_splus_): Call gen_altivec_vsumsws_direct instead of + gen_altivec_vsumsws. + + Backport from mainline r207415 + 2014-02-02 Bill Schmidt + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_le): Generalize + for vector types other than V16QImode. + * config/rs6000/altivec.md (altivec_vperm_): Change to a + define_expand, and call altivec_expand_vec_perm_le when producing + code with little endian element order. + (*altivec_vperm__internal): New insn having previous + behavior of altivec_vperm_. + (altivec_vperm__uns): Change to a define_expand, and call + altivec_expand_vec_perm_le when producing code with little endian + element order. + (*altivec_vperm__uns_internal): New insn having previous + behavior of altivec_vperm__uns. + + Backport from mainline r207520 + 2014-02-05 Bill Schmidt + + * altivec.md (UNSPEC_VPACK_UNS_UNS_MOD_DIRECT): New unspec. + (UNSPEC_VUNPACK_HI_SIGN_DIRECT): Likewise. + (UNSPEC_VUNPACK_LO_SIGN_DIRECT): Likewise. + (mulv8hi3): Use gen_altivec_vpkuwum_direct instead of + gen_altivec_vpkuwum. + (altivec_vpkpx): Test for VECTOR_ELT_ORDER_BIG instead of for + BYTES_BIG_ENDIAN. + (altivec_vpksss): Likewise. + (altivec_vpksus): Likewise. + (altivec_vpkuus): Likewise. + (altivec_vpkuum): Likewise. + (altivec_vpkuum_direct): New (copy of + altivec_vpkuum that still relies on BYTES_BIG_ENDIAN, for + internal use). + (altivec_vupkhs): Emit vupkls* instead of vupkhs* when + target is little endian and -maltivec=be is not specified. + (*altivec_vupkhs_direct): New (copy of + altivec_vupkhs that always emits vupkhs*, for internal + use). + (altivec_vupkls): Emit vupkhs* instead of vupkls* when + target is little endian and -maltivec=be is not specified. + (*altivec_vupkls_direct): New (copy of + altivec_vupkls that always emits vupkls*, for internal + use). + (altivec_vupkhpx): Emit vupklpx instead of vupkhpx when target is + little endian and -maltivec=be is not specified. + (altivec_vupklpx): Emit vupkhpx instead of vupklpx when target is + little endian and -maltivec=be is not specified. + + Backport from mainline r207521 + 2014-02-05 Bill Schmidt + + * config/rs6000/altivec.md (altivec_vsum2sws): Adjust code + generation for -maltivec=be. + (altivec_vsumsws): Simplify redundant test. + + Backport from mainline r207525 + 2014-02-05 Bill Schmidt + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Change + CODE_FOR_altivec_vpku[hw]um to + CODE_FOR_altivec_vpku[hw]um_direct. + * config/rs6000/altivec.md (vec_unpacks_hi_): Change + UNSPEC_VUNPACK_HI_SIGN to UNSPEC_VUNPACK_HI_SIGN_DIRECT. + (vec_unpacks_lo_): Change UNSPEC_VUNPACK_LO_SIGN to + UNSPEC_VUNPACK_LO_SIGN_DIRECT. + + Backport from mainline r207814. + 2014-02-16 Bill Schmidt + + * config/rs6000/vsx.md (vsx_xxpermdi_): Handle little + endian targets. + + Backport from mainline r207815. + 2014-02-16 Bill Schmidt + + * config/rs6000/altivec.md (p8_vmrgew): Handle little endian + targets. + (p8_vmrgow): Likewise. + + Backport from mainline r207919. + 2014-02-19 Bill Schmidt + + * config/rs6000/rs6000.c (vspltis_constant): Fix most significant + bit of zero. + + Backport from mainline 208019 + 2014-02-21 Bill Schmidt + + * config/rs6000/altivec.md (altivec_lvxl): Rename as + *altivec_lvxl__internal and use VM2 iterator instead of + V4SI. + (altivec_lvxl_): New define_expand incorporating + -maltivec=be semantics where needed. + (altivec_lvx): Rename as *altivec_lvx__internal. + (altivec_lvx_): New define_expand incorporating -maltivec=be + semantics where needed. + (altivec_stvx): Rename as *altivec_stvx__internal. + (altivec_stvx_): New define_expand incorporating + -maltivec=be semantics where needed. + (altivec_stvxl): Rename as *altivec_stvxl__internal and use + VM2 iterator instead of V4SI. + (altivec_stvxl_): New define_expand incorporating + -maltivec=be semantics where needed. + * config/rs6000/rs6000-builtin.def: Add new built-in definitions + LVXL_V2DF, LVXL_V2DI, LVXL_V4SF, LVXL_V4SI, LVXL_V8HI, LVXL_V16QI, + LVX_V2DF, LVX_V2DI, LVX_V4SF, LVX_V4SI, LVX_V8HI, LVX_V16QI, + STVX_V2DF, STVX_V2DI, STVX_V4SF, STVX_V4SI, STVX_V8HI, STVX_V16QI, + STVXL_V2DF, STVXL_V2DI, STVXL_V4SF, STVXL_V4SI, STVXL_V8HI, + STVXL_V16QI. + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Replace + ALTIVEC_BUILTIN_LVX with ALTIVEC_BUILTIN_LVX_ throughout; + similarly for ALTIVEC_BUILTIN_LVXL, ALTIVEC_BUILTIN_STVX, and + ALTIVEC_BUILTIN_STVXL. + * config/rs6000/rs6000-protos.h (altivec_expand_lvx_be): New + prototype. + (altivec_expand_stvx_be): Likewise. + * config/rs6000/rs6000.c (swap_selector_for_mode): New function. + (altivec_expand_lvx_be): Likewise. + (altivec_expand_stvx_be): Likewise. + (altivec_expand_builtin): Add cases for + ALTIVEC_BUILTIN_STVX_, ALTIVEC_BUILTIN_STVXL_, + ALTIVEC_BUILTIN_LVXL_, and ALTIVEC_BUILTIN_LVX_. + (altivec_init_builtins): Add definitions for + __builtin_altivec_lvxl_, __builtin_altivec_lvx_, + __builtin_altivec_stvx_, and + __builtin_altivec_stvxl_. + + Backport from mainline 208021 + 2014-02-21 Bill Schmidt + + * config/rs6000/altivec.md (altivec_vsumsws): Replace second + vspltw with vsldoi. + (reduc_uplus_v16qi): Use gen_altivec_vsumsws_direct instead of + gen_altivec_vsumsws. + + Backport from mainline 208049 + 2014-02-23 Bill Schmidt + + * config/rs6000/altivec.md (altivec_lvex): Replace + define_insn with define_expand and new define_insn + *altivec_lvex_internal. + (altivec_stvex): Replace define_insn with define_expand + and new define_insn *altivec_stvex_internal. + * config/rs6000/rs6000-protos.h (altivec_expand_stvex_be): New + prototype. + * config/rs6000/rs6000.c (altivec_expand_lvx_be): Document use by + lve*x built-ins. + (altivec_expand_stvex_be): New function. + + Backport from mainline + 2014-02-23 Bill Schmidt + * config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Relax assert + to permit subregs. + + Backport from mainline + 2014-02-25 Bill Schmidt + * config/rs6000/vector.md (*vector_unordered): Change split + to use canonical form for nor3. + + 2014-04-04 Bill Schmidt + + Backport from mainline + 2014-02-04 Michael Meissner + + * config/rs6000/rs6000.opt (-mlra): Add switch to enable the LRA + register allocator. + + * config/rs6000/rs6000.c (TARGET_LRA_P): Add support for -mlra to + enable the LRA register allocator. Back port the changes from the + trunk to enable LRA. + (rs6000_legitimate_offset_address_p): Likewise. + (legitimate_lo_sum_address_p): Likewise. + (use_toc_relative_ref): Likewise. + (rs6000_legitimate_address_p): Likewise. + (rs6000_emit_move): Likewise. + (rs6000_secondary_memory_needed_mode): Likewise. + (rs6000_alloc_sdmode_stack_slot): Likewise. + (rs6000_lra_p): Likewise. + + * config/rs6000/sync.md (load_lockedti): Copy TI/PTI variables by + 64-bit parts to force the register allocator to allocate even/odd + register pairs for the quad word atomic instructions. + (store_conditionalti): Likewise. + + 2014-04-04 Bill Schmidt + + Back port from mainline + 2014-01-23 Michael Meissner + + PR target/59909 + * doc/invoke.texi (RS/6000 and PowerPC Options): Document + -mquad-memory-atomic. Update -mquad-memory documentation to say + it is only used for non-atomic loads/stores. + + * config/rs6000/predicates.md (quad_int_reg_operand): Allow either + -mquad-memory or -mquad-memory-atomic switches. + + * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add + -mquad-memory-atomic to ISA 2.07 support. + + * config/rs6000/rs6000.opt (-mquad-memory-atomic): Add new switch + to separate support of normal quad word memory operations (ldq, + stq) from the atomic quad word memory operations. + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Add + support to separate non-atomic quad word operations from atomic + quad word operations. Disable non-atomic quad word operations in + little endian mode so that we don't have to swap words after the + load and before the store. + (quad_load_store_p): Add comment about atomic quad word support. + (rs6000_opt_masks): Add -mquad-memory-atomic to the list of + options printed with -mdebug=reg. + + * config/rs6000/rs6000.h (TARGET_SYNC_TI): Use + -mquad-memory-atomic as the test for whether we have quad word + atomic instructions. + (TARGET_SYNC_HI_QI): If either -mquad-memory-atomic, + -mquad-memory, or -mp8-vector are used, allow byte/half-word + atomic operations. + + * config/rs6000/sync.md (load_lockedti): Insure that the address + is a proper indexed or indirect address for the lqarx instruction. + On little endian systems, swap the hi/lo registers after the lqarx + instruction. + (load_lockedpti): Use indexed_or_indirect_operand predicate to + insure the address is valid for the lqarx instruction. + (store_conditionalti): Insure that the address is a proper indexed + or indirect address for the stqcrx. instruction. On little endian + systems, swap the hi/lo registers before doing the stqcrx. + instruction. + (store_conditionalpti): Use indexed_or_indirect_operand predicate to + insure the address is valid for the stqcrx. instruction. + + * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros): + Define __QUAD_MEMORY__ and __QUAD_MEMORY_ATOMIC__ based on what + type of quad memory support is available. + + 2014-04-04 Bill Schmidt + + Apply mainline r202190, powerpc64le multilibs and multiarch dir + 2013-09-03 Alan Modra + + * config.gcc (powerpc*-*-linux*): Add support for little-endian + multilibs to big-endian target and vice versa. + * config/rs6000/t-linux64: Use := assignment on all vars. + (MULTILIB_EXTRA_OPTS): Remove fPIC. + (MULTILIB_OSDIRNAMES): Specify using mapping from multilib_options. + * config/rs6000/t-linux64le: New file. + * config/rs6000/t-linux64bele: New file. + * config/rs6000/t-linux64lebe: New file. + + 2014-04-04 Bill Schmidt + + Back port from mainline + 2014-01-16 Michael Meissner + + PR target/59844 + * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little + endian support, remove tests for WORDS_BIG_ENDIAN. + (p8_mfvsrd_3_): Likewise. + (reload_gpr_from_vsx): Likewise. + (reload_gpr_from_vsxsf): Likewise. + (p8_mfvsrd_4_disf): Likewise. + + 2014-04-04 Bill Schmidt + + Backport from mainline + 2013-04-05 Bill Schmidt + + PR target/56843 + * config/rs6000/rs6000.c (rs6000_emit_swdiv_high_precision): Remove. + (rs6000_emit_swdiv_low_precision): Remove. + (rs6000_emit_swdiv): Rewrite to handle between one and four + iterations of Newton-Raphson generally; modify required number of + iterations for some cases. + * config/rs6000/rs6000.h (RS6000_RECIP_HIGH_PRECISION_P): Remove. + + 2014-04-04 Bill Schmidt + + Backport from mainline + 2013-08-19 Peter Bergner + Jakub Jelinek + + * builtins.def (BUILT_IN_FABSD32): New DFP ABS builtin. + (BUILT_IN_FABSD64): Likewise. + (BUILT_IN_FABSD128): Likewise. + * builtins.c (expand_builtin): Add support for + new DFP ABS builtins. + (fold_builtin_1): Likewise. + * config/rs6000/dfp.md + (*abstd2_fpr): Handle non-overlapping destination + and source operands. + (*nabstd2_fpr): Likewise. + + 2014-04-04 Bill Schmidt + + Apply mainline r205060. + 2013-11-20 Alan Modra + * config/rs6000/sysv4.h (CC1_ENDIAN_LITTLE_SPEC): Define as empty. + * config/rs6000/rs6000.c (rs6000_option_override_internal): Default + to strict alignment on older processors when little-endian. + * config/rs6000/linux64.h (PROCESSOR_DEFAULT64): Default to power8 + for ELFv2. + + 2014-04-04 Bill Schmidt + + POWER ELFv2 ABI Support + Backport from mainline r204842: + + 2013-11-15 Ulrich Weigand + + * doc/invoke.texi (-mabi=elfv1, -mabi=elfv2): Document. + + Backport from mainline r204809: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/sysv4le.h (LINUX64_DEFAULT_ABI_ELFv2): Define. + + Backport from mainline r204808: + + 2013-11-14 Ulrich Weigand + Alan Modra + + * config/rs6000/rs6000.h (RS6000_SAVE_AREA): Handle ABI_ELFv2. + (RS6000_SAVE_TOC): Remove. + (RS6000_TOC_SAVE_SLOT): New macro. + * config/rs6000/rs6000.c (rs6000_parm_offset): New function. + (rs6000_parm_start): Use it. + (rs6000_function_arg_advance_1): Likewise. + (rs6000_emit_prologue): Use RS6000_TOC_SAVE_SLOT. + (rs6000_emit_epilogue): Likewise. + (rs6000_call_aix): Likewise. + (rs6000_output_function_prologue): Do not save/restore r11 + around calling _mcount for ABI_ELFv2. + + 2013-11-14 Ulrich Weigand + Alan Modra + + * config/rs6000/rs6000-protos.h (rs6000_reg_parm_stack_space): + Add prototype. + * config/rs6000/rs6000.h (RS6000_REG_SAVE): Remove. + (REG_PARM_STACK_SPACE): Call rs6000_reg_parm_stack_space. + * config/rs6000/rs6000.c (rs6000_parm_needs_stack): New function. + (rs6000_function_parms_need_stack): Likewise. + (rs6000_reg_parm_stack_space): Likewise. + (rs6000_function_arg): Do not replace BLKmode by Pmode when + returning a register argument. + + 2013-11-14 Ulrich Weigand + Michael Gschwind + + * config/rs6000/rs6000.h (FP_ARG_MAX_RETURN): New macro. + (ALTIVEC_ARG_MAX_RETURN): Likewise. + (FUNCTION_VALUE_REGNO_P): Use them. + * config/rs6000/rs6000.c (TARGET_RETURN_IN_MSB): Define. + (rs6000_return_in_msb): New function. + (rs6000_return_in_memory): Handle ELFv2 homogeneous aggregates. + Handle aggregates of up to 16 bytes for ELFv2. + (rs6000_function_value): Handle ELFv2 homogeneous aggregates. + + 2013-11-14 Ulrich Weigand + Michael Gschwind + + * config/rs6000/rs6000.h (AGGR_ARG_NUM_REG): Define. + * config/rs6000/rs6000.c (rs6000_aggregate_candidate): New function. + (rs6000_discover_homogeneous_aggregate): Likewise. + (rs6000_function_arg_boundary): Handle homogeneous aggregates. + (rs6000_function_arg_advance_1): Likewise. + (rs6000_function_arg): Likewise. + (rs6000_arg_partial_bytes): Likewise. + (rs6000_psave_function_arg): Handle BLKmode arguments. + + 2013-11-14 Ulrich Weigand + Michael Gschwind + + * config/rs6000/rs6000.h (AGGR_ARG_NUM_REG): Define. + * config/rs6000/rs6000.c (rs6000_aggregate_candidate): New function. + (rs6000_discover_homogeneous_aggregate): Likewise. + (rs6000_function_arg_boundary): Handle homogeneous aggregates. + (rs6000_function_arg_advance_1): Likewise. + (rs6000_function_arg): Likewise. + (rs6000_arg_partial_bytes): Likewise. + (rs6000_psave_function_arg): Handle BLKmode arguments. + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (machine_function): New member + r2_setup_needed. + (rs6000_emit_prologue): Set r2_setup_needed if necessary. + (rs6000_output_mi_thunk): Set r2_setup_needed. + (rs6000_output_function_prologue): Output global entry point + prologue and local entry point marker if needed for ABI_ELFv2. + Output -mprofile-kernel code here. + (output_function_profiler): Do not output -mprofile-kernel + code here; moved to rs6000_output_function_prologue. + (rs6000_file_start): Output ".abiversion 2" for ABI_ELFv2. + + (rs6000_emit_move): Do not handle dot symbols for ABI_ELFv2. + (rs6000_output_function_entry): Likewise. + (rs6000_assemble_integer): Likewise. + (rs6000_elf_encode_section_info): Likewise. + (rs6000_elf_declare_function_name): Do not create dot symbols + or .opd section for ABI_ELFv2. + + (rs6000_trampoline_size): Update for ABI_ELFv2 trampolines. + (rs6000_trampoline_init): Likewise. + (rs6000_elf_file_end): Call file_end_indicate_exec_stack + for ABI_ELFv2. + + (rs6000_call_aix): Handle ELFv2 indirect calls. Do not check + for function descriptors in ABI_ELFv2. + + * config/rs6000/rs6000.md ("*call_indirect_aix"): Support + on ABI_AIX only, not ABI_ELFv2. + ("*call_value_indirect_aix"): Likewise. + ("*call_indirect_elfv2"): New pattern. + ("*call_value_indirect_elfv2"): Likewise. + + * config/rs6000/predicates.md ("symbol_ref_operand"): Do not + check for function descriptors in ABI_ELFv2. + ("current_file_function_operand"): Likewise. + + * config/rs6000/ppc-asm.h [__powerpc64__ && _CALL_ELF == 2]: + (toc): Undefine. + (FUNC_NAME): Define ELFv2 variant. + (JUMP_TARGET): Likewise. + (FUNC_START): Likewise. + (HIDDEN_FUNC): Likewise. + (FUNC_END): Likeiwse. + + 2013-11-14 Ulrich Weigand + + * config.gcc [powerpc*-*-* | rs6000-*-*]: Support --with-abi=elfv1 + and --with-abi=elfv2. + * config/rs6000/option-defaults.h (OPTION_DEFAULT_SPECS): Add "abi". + * config/rs6000/rs6000.opt (mabi=elfv1): New option. + (mabi=elfv2): Likewise. + * config/rs6000/rs6000-opts.h (enum rs6000_abi): Add ABI_ELFv2. + * config/rs6000/linux64.h (DEFAULT_ABI): Do not hard-code to AIX_ABI + if !RS6000_BI_ARCH. + (ELFv2_ABI_CHECK): New macro. + (SUBSUBTARGET_OVERRIDE_OPTIONS): Use it to decide whether to set + rs6000_current_abi to ABI_AIX or ABI_ELFv2. + (GLIBC_DYNAMIC_LINKER64): Support ELFv2 ld.so version. + * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Predefine + _CALL_ELF and __STRUCT_PARM_ALIGN__ if appropriate. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Handle ABI_ELFv2. + (debug_stack_info): Likewise. + (rs6000_file_start): Treat ABI_ELFv2 the same as ABI_AIX. + (rs6000_legitimize_tls_address): Likewise. + (rs6000_conditional_register_usage): Likewise. + (rs6000_emit_move): Likewise. + (init_cumulative_args): Likewise. + (rs6000_function_arg_advance_1): Likewise. + (rs6000_function_arg): Likewise. + (rs6000_arg_partial_bytes): Likewise. + (rs6000_output_function_entry): Likewise. + (rs6000_assemble_integer): Likewise. + (rs6000_savres_strategy): Likewise. + (rs6000_stack_info): Likewise. + (rs6000_function_ok_for_sibcall): Likewise. + (rs6000_emit_load_toc_table): Likewise. + (rs6000_savres_routine_name): Likewise. + (ptr_regno_for_savres): Likewise. + (rs6000_emit_prologue): Likewise. + (rs6000_emit_epilogue): Likewise. + (rs6000_output_function_epilogue): Likewise. + (output_profile_hook): Likewise. + (output_function_profiler): Likewise. + (rs6000_trampoline_size): Likewise. + (rs6000_trampoline_init): Likewise. + (rs6000_elf_output_toc_section_asm_op): Likewise. + (rs6000_elf_encode_section_info): Likewise. + (rs6000_elf_reloc_rw_mask): Likewise. + (rs6000_elf_declare_function_name): Likewise. + (rs6000_function_arg_boundary): Treat ABI_ELFv2 the same as ABI_AIX, + except that rs6000_compat_align_parm is always assumed false. + (rs6000_gimplify_va_arg): Likewise. + (rs6000_call_aix): Update comment. + (rs6000_sibcall_aix): Likewise. + * config/rs6000/rs6000.md ("tls_gd_aix"): + Treat ABI_ELFv2 the same as ABI_AIX. + ("*tls_gd_call_aix"): Likewise. + ("tls_ld_aix"): Likewise. + ("*tls_ld_call_aix"): Likewise. + ("load_toc_aix_si"): Likewise. + ("load_toc_aix_di"): Likewise. + ("call"): Likewise. + ("call_value"): Likewise. + ("*call_local_aix"): Likewise. + ("*call_value_local_aix"): Likewise. + ("*call_nonlocal_aix"): Likewise. + ("*call_value_nonlocal_aix"): Likewise. + ("*call_indirect_aix"): Likewise. + ("*call_value_indirect_aix"): Likewise. + ("sibcall"): Likewise. + ("sibcall_value"): Likewise. + ("*sibcall_aix"): Likewise. + ("*sibcall_value_aix"): Likewise. + * config/rs6000/predicates.md ("symbol_ref_operand"): Likewise. + ("current_file_function_operand"): Likewise. + + Backport from mainline r204807: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_arg_partial_bytes): Simplify logic + by making use of the fact that for vector / floating point arguments + passed both in VRs/FPRs and in the fixed parameter area, the partial + bytes mechanism is in fact not used. + + Backport from mainline r204806: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_psave_function_arg): New function. + (rs6000_finish_function_arg): Likewise. + (rs6000_function_arg): Use rs6000_psave_function_arg and + rs6000_finish_function_arg to handle both vector and floating + point arguments that are also passed in GPRs / the stack. + + Backport from mainline r204805: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (USE_FP_FOR_ARG_P): Remove TYPE argument. + (USE_ALTIVEC_FOR_ARG_P): Likewise. + (rs6000_darwin64_record_arg_advance_recurse): Update uses. + (rs6000_function_arg_advance_1):Likewise. + (rs6000_darwin64_record_arg_recurse): Likewise. + (rs6000_function_arg): Likewise. + (rs6000_arg_partial_bytes): Likewise. + + Backport from mainline r204804: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Replace + "DEFAULT_ABI != ABI_AIX" test by testing for ABI_V4 or ABI_DARWIN. + (rs6000_savres_strategy): Likewise. + (rs6000_return_addr): Likewise. + (rs6000_emit_load_toc_table): Replace "DEFAULT_ABI != ABI_AIX" by + testing for ABI_V4 (since ABI_DARWIN is impossible here). + (rs6000_emit_prologue): Likewise. + (legitimate_lo_sum_address_p): Simplify DEFAULT_ABI test. + (rs6000_elf_declare_function_name): Remove duplicated test. + * config/rs6000/rs6000.md ("load_toc_v4_PIC_1"): Explicitly test + for ABI_V4 (instead of "DEFAULT_ABI != ABI_AIX" test). + ("load_toc_v4_PIC_1_normal"): Likewise. + ("load_toc_v4_PIC_1_476"): Likewise. + ("load_toc_v4_PIC_1b"): Likewise. + ("load_toc_v4_PIC_1b_normal"): Likewise. + ("load_toc_v4_PIC_1b_476"): Likewise. + ("load_toc_v4_PIC_2"): Likewise. + ("load_toc_v4_PIC_3b"): Likewise. + ("load_toc_v4_PIC_3c"): Likewise. + * config/rs6000/rs6000.h (RS6000_REG_SAVE): Simplify DEFAULT_ABI test. + (RS6000_SAVE_AREA): Likewise. + (FP_ARG_MAX_REG): Likewise. + (RETURN_ADDRESS_OFFSET): Likewise. + * config/rs6000/sysv.h (TARGET_TOC): Test for ABI_V4 instead + of ABI_AIX. + (SUBTARGET_OVERRIDE_OPTIONS): Likewise. + (MINIMAL_TOC_SECTION_ASM_OP): Likewise. + + Backport from mainline r204803: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_call_indirect_aix): Rename to ... + (rs6000_call_aix): ... this. Handle both direct and indirect calls. + Create call insn directly instead of via various gen_... routines. + Mention special registers used by the call in CALL_INSN_FUNCTION_USAGE. + (rs6000_sibcall_aix): New function. + * config/rs6000/rs6000.md (TOC_SAVE_OFFSET_32BIT): Remove. + (TOC_SAVE_OFFSET_64BIT): Likewise. + (AIX_FUNC_DESC_TOC_32BIT): Likewise. + (AIX_FUNC_DESC_TOC_64BIT): Likewise. + (AIX_FUNC_DESC_SC_32BIT): Likewise. + (AIX_FUNC_DESC_SC_64BIT): Likewise. + ("call" expander): Call rs6000_call_aix. + ("call_value" expander): Likewise. + ("call_indirect_aix"): Replace this pattern ... + ("call_indirect_aix_nor11"): ... and this pattern ... + ("*call_indirect_aix"): ... by this insn pattern. + ("call_value_indirect_aix"): Replace this pattern ... + ("call_value_indirect_aix_nor11"): ... and this pattern ... + ("*call_value_indirect_aix"): ... by this insn pattern. + ("*call_nonlocal_aix32", "*call_nonlocal_aix64"): Replace by ... + ("*call_nonlocal_aix"): ... this pattern. + ("*call_value_nonlocal_aix32", "*call_value_nonlocal_aix64"): Replace + ("*call_value_nonlocal_aix"): ... by this pattern. + ("*call_local_aix"): New insn pattern. + ("*call_value_local_aix"): Likewise. + ("sibcall" expander): Call rs6000_sibcall_aix. + ("sibcall_value" expander): Likewise. Move earlier in file. + ("*sibcall_nonlocal_aix"): Replace by ... + ("*sibcall_aix"): ... this pattern. + ("*sibcall_value_nonlocal_aix"): Replace by ... + ("*sibcall_value_aix"): ... this pattern. + * config/rs6000/rs6000-protos.h (rs6000_call_indirect_aix): Remove. + (rs6000_call_aix): Add prototype. + (rs6000_sibcall_aix): Likewise. + + Backport from mainline r204799: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_emit_prologue): Do not place a + RTX_FRAME_RELATED_P marker on the UNSPEC_MOVESI_FROM_CR insn. + Instead, add USEs of all modified call-saved CR fields to the + insn storing the result to the stack slot, and provide an + appropriate REG_FRAME_RELATED_EXPR for that insn. + * config/rs6000/rs6000.md ("*crsave"): New insn pattern. + * config/rs6000/predicates.md ("crsave_operation"): New predicate. + + 2014-04-04 Bill Schmidt + + ELFv2 ABI Call Support + Backport from mainline r204798: + + 2013-11-14 Ulrich Weigand + Alan Modra + + * function.c (assign_parms): Use all.reg_parm_stack_space instead + of re-evaluating REG_PARM_STACK_SPACE target macro. + (locate_and_pad_parm): New parameter REG_PARM_STACK_SPACE. Use it + instead of evaluating target macro REG_PARM_STACK_SPACE every time. + (assign_parm_find_entry_rtl): Update call. + * calls.c (initialize_argument_information): Update call. + (emit_library_call_value_1): Likewise. + * expr.h (locate_and_pad_parm): Update prototype. + + Backport from mainline r204797: + + 2013-11-14 Ulrich Weigand + + * calls.c (store_unaligned_arguments_into_pseudos): Skip PARALLEL + arguments. + + Backport from mainline r197003: + + 2013-03-23 Eric Botcazou + + * calls.c (expand_call): Add missing guard to code handling return + of non-BLKmode structures in MSB. + * function.c (expand_function_end): Likewise. + + 2014-04-04 Bill Schmidt + + Backport from mainline r201750. + Note: Default setting of -mcompat-align-parm inverted! + + 2013-08-14 Bill Schmidt + + PR target/57949 + * doc/invoke.texi: Add documentation of mcompat-align-parm + option. + * config/rs6000/rs6000.opt: Add mcompat-align-parm option. + * config/rs6000/rs6000.c (rs6000_function_arg_boundary): For AIX + and Linux, correct BLKmode alignment when 128-bit alignment is + required and compatibility flag is not set. + (rs6000_gimplify_va_arg): For AIX and Linux, honor specified + alignment for zero-size arguments when compatibility flag is not + set. + + 2014-04-04 Bill Schmidt + + Little Endian Vector Support + Backport from mainline r205333 + 2013-11-24 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_expand_vec_perm_const_1): Correct + for little endian. + + Backport from mainline r205241 + 2013-11-21 Bill Schmidt + + * config/rs6000/vector.md (vec_pack_trunc_v2df): Revert previous + little endian change. + (vec_pack_sfix_trunc_v2df): Likewise. + (vec_pack_ufix_trunc_v2df): Likewise. + * config/rs6000/rs6000.c (rs6000_expand_interleave): Correct + double checking of endianness. + + Backport from mainline r205146 + 2013-11-20 Bill Schmidt + + * config/rs6000/vsx.md (vsx_set_): Adjust for little endian. + (vsx_extract_): Likewise. + (*vsx_extract__one_le): New LE variant on + *vsx_extract__zero. + (vsx_extract_v4sf): Adjust for little endian. + + Backport from mainline r205080 + 2013-11-19 Bill Schmidt + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Adjust + V16QI vector splat case for little endian. + + Backport from mainline r205045: + + 2013-11-19 Ulrich Weigand + + * config/rs6000/vector.md ("mov"): Do not call + rs6000_emit_le_vsx_move to move into or out of GPRs. + * config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Assert + source and destination are not GPR hard regs. + + Backport from mainline r204920 + 2011-11-17 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_frame_related): Add split_reg + parameter and use it in REG_FRAME_RELATED_EXPR note. + (emit_frame_save): Call rs6000_frame_related with extra NULL_RTX + parameter. + (rs6000_emit_prologue): Likewise, but for little endian VSX + stores, pass the source register of the store instead. + + Backport from mainline r204862 + 2013-11-15 Bill Schmidt + + * config/rs6000/altivec.md (UNSPEC_VPERM_X, UNSPEC_VPERM_UNS_X): + Remove. + (altivec_vperm_): Revert earlier little endian change. + (*altivec_vperm__internal): Remove. + (altivec_vperm__uns): Revert earlier little endian change. + (*altivec_vperm__uns_internal): Remove. + * config/rs6000/vector.md (vec_realign_load_): Revise + commentary. + + Backport from mainline r204441 + 2013-11-05 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_option_override_internal): + Remove restriction against use of VSX instructions when generating + code for little endian mode. + + Backport from mainline r204440 + 2013-11-05 Bill Schmidt + + * config/rs6000/altivec.md (mulv4si3): Ensure we generate vmulouh + for both big and little endian. + (mulv8hi3): Swap input operands for merge high and merge low + instructions for little endian. + + Backport from mainline r204439 + 2013-11-05 Bill Schmidt + + * config/rs6000/altivec.md (vec_widen_umult_even_v16qi): Change + define_insn to define_expand that uses even patterns for big + endian and odd patterns for little endian. + (vec_widen_smult_even_v16qi): Likewise. + (vec_widen_umult_even_v8hi): Likewise. + (vec_widen_smult_even_v8hi): Likewise. + (vec_widen_umult_odd_v16qi): Likewise. + (vec_widen_smult_odd_v16qi): Likewise. + (vec_widen_umult_odd_v8hi): Likewise. + (vec_widen_smult_odd_v8hi): Likewise. + (altivec_vmuleub): New define_insn. + (altivec_vmuloub): Likewise. + (altivec_vmulesb): Likewise. + (altivec_vmulosb): Likewise. + (altivec_vmuleuh): Likewise. + (altivec_vmulouh): Likewise. + (altivec_vmulesh): Likewise. + (altivec_vmulosh): Likewise. + + Backport from mainline r204395 + 2013-11-05 Bill Schmidt + + * config/rs6000/vector.md (vec_pack_sfix_trunc_v2df): Adjust for + little endian. + (vec_pack_ufix_trunc_v2df): Likewise. + + Backport from mainline r204363 + 2013-11-04 Bill Schmidt + + * config/rs6000/altivec.md (vec_widen_umult_hi_v16qi): Swap + arguments to merge instruction for little endian. + (vec_widen_umult_lo_v16qi): Likewise. + (vec_widen_smult_hi_v16qi): Likewise. + (vec_widen_smult_lo_v16qi): Likewise. + (vec_widen_umult_hi_v8hi): Likewise. + (vec_widen_umult_lo_v8hi): Likewise. + (vec_widen_smult_hi_v8hi): Likewise. + (vec_widen_smult_lo_v8hi): Likewise. + + Backport from mainline r204350 + 2013-11-04 Bill Schmidt + + * config/rs6000/vsx.md (*vsx_le_perm_store_ for VSX_D): + Replace the define_insn_and_split with a define_insn and two + define_splits, with the split after reload re-permuting the source + register to its original value. + (*vsx_le_perm_store_ for VSX_W): Likewise. + (*vsx_le_perm_store_v8hi): Likewise. + (*vsx_le_perm_store_v16qi): Likewise. + + Backport from mainline r204321 + 2013-11-04 Bill Schmidt + + * config/rs6000/vector.md (vec_pack_trunc_v2df): Adjust for + little endian. + + Backport from mainline r204321 + 2013-11-02 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_expand_vector_set): Adjust for + little endian. + + Backport from mainline r203980 + 2013-10-23 Bill Schmidt + + * config/rs6000/altivec.md (mulv8hi3): Adjust for little endian. + + Backport from mainline r203930 + 2013-10-22 Bill Schmidt + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Reverse + meaning of merge-high and merge-low masks for little endian; avoid + use of vector-pack masks for little endian for mismatched modes. + + Backport from mainline r203877 + 2013-10-20 Bill Schmidt + + * config/rs6000/altivec.md (vec_unpacku_hi_v16qi): Adjust for + little endian. + (vec_unpacku_hi_v8hi): Likewise. + (vec_unpacku_lo_v16qi): Likewise. + (vec_unpacku_lo_v8hi): Likewise. + + Backport from mainline r203863 + 2013-10-19 Bill Schmidt + + * config/rs6000/rs6000.c (vspltis_constant): Make sure we check + all elements for both endian flavors. + + Backport from mainline r203714 + 2013-10-16 Bill Schmidt + + * gcc/config/rs6000/vector.md (vec_unpacks_hi_v4sf): Correct for + endianness. + (vec_unpacks_lo_v4sf): Likewise. + (vec_unpacks_float_hi_v4si): Likewise. + (vec_unpacks_float_lo_v4si): Likewise. + (vec_unpacku_float_hi_v4si): Likewise. + (vec_unpacku_float_lo_v4si): Likewise. + + Backport from mainline r203713 + 2013-10-16 Bill Schmidt + + * config/rs6000/vsx.md (vsx_concat_): Adjust output for LE. + (vsx_concat_v2sf): Likewise. + + Backport from mainline r203458 + 2013-10-11 Bill Schmidt + + * config/rs6000/vsx.md (*vsx_le_perm_load_v2di): Generalize to + handle vector float as well. + (*vsx_le_perm_load_v4si): Likewise. + (*vsx_le_perm_store_v2di): Likewise. + (*vsx_le_perm_store_v4si): Likewise. + + Backport from mainline r203457 + 2013-10-11 Bill Schmidt + + * config/rs6000/vector.md (vec_realign_load): Generate vperm + directly to circumvent subtract from splat{31} workaround. + * config/rs6000/rs6000-protos.h (altivec_expand_vec_perm_le): New + prototype. + * config/rs6000/rs6000.c (altivec_expand_vec_perm_le): New. + * config/rs6000/altivec.md (define_c_enum "unspec"): Add + UNSPEC_VPERM_X and UNSPEC_VPERM_UNS_X. + (altivec_vperm_): Convert to define_insn_and_split to + separate big and little endian logic. + (*altivec_vperm__internal): New define_insn. + (altivec_vperm__uns): Convert to define_insn_and_split to + separate big and little endian logic. + (*altivec_vperm__uns_internal): New define_insn. + (vec_permv16qi): Add little endian logic. + + Backport from mainline r203247 + 2013-10-07 Bill Schmidt + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const_le): New. + (altivec_expand_vec_perm_const): Call it. + + Backport from mainline r203246 + 2013-10-07 Bill Schmidt + + * config/rs6000/vector.md (mov): Emit permuted move + sequences for LE VSX loads and stores at expand time. + * config/rs6000/rs6000-protos.h (rs6000_emit_le_vsx_move): New + prototype. + * config/rs6000/rs6000.c (rs6000_const_vec): New. + (rs6000_gen_le_vsx_permute): New. + (rs6000_gen_le_vsx_load): New. + (rs6000_gen_le_vsx_store): New. + (rs6000_gen_le_vsx_move): New. + * config/rs6000/vsx.md (*vsx_le_perm_load_v2di): New. + (*vsx_le_perm_load_v4si): New. + (*vsx_le_perm_load_v8hi): New. + (*vsx_le_perm_load_v16qi): New. + (*vsx_le_perm_store_v2di): New. + (*vsx_le_perm_store_v4si): New. + (*vsx_le_perm_store_v8hi): New. + (*vsx_le_perm_store_v16qi): New. + (*vsx_xxpermdi2_le_): New. + (*vsx_xxpermdi4_le_): New. + (*vsx_xxpermdi8_le_V8HI): New. + (*vsx_xxpermdi16_le_V16QI): New. + (*vsx_lxvd2x2_le_): New. + (*vsx_lxvd2x4_le_): New. + (*vsx_lxvd2x8_le_V8HI): New. + (*vsx_lxvd2x16_le_V16QI): New. + (*vsx_stxvd2x2_le_): New. + (*vsx_stxvd2x4_le_): New. + (*vsx_stxvd2x8_le_V8HI): New. + (*vsx_stxvd2x16_le_V16QI): New. + + Backport from mainline r201235 + 2013-07-24 Bill Schmidt + Anton Blanchard + + * config/rs6000/altivec.md (altivec_vpkpx): Handle little endian. + (altivec_vpksss): Likewise. + (altivec_vpksus): Likewise. + (altivec_vpkuus): Likewise. + (altivec_vpkuum): Likewise. + + Backport from mainline r201208 + 2013-07-24 Bill Schmidt + Anton Blanchard + + * config/rs6000/vector.md (vec_realign_load_): Reorder input + operands to vperm for little endian. + * config/rs6000/rs6000.c (rs6000_expand_builtin): Use lvsr instead + of lvsl to create the control mask for a vperm for little endian. + + Backport from mainline r201195 + 2013-07-23 Bill Schmidt + Anton Blanchard + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Reverse + two operands for little-endian. + + Backport from mainline r201193 + 2013-07-23 Bill Schmidt + Anton Blanchard + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Correct + selection of field for vector splat in little endian mode. + + Backport from mainline r201149 + 2013-07-22 Bill Schmidt + Anton Blanchard + + * config/rs6000/rs6000.c (rs6000_expand_vector_init): Fix + endianness when selecting field to splat. + + 2014-04-04 Bill Schmidt + + Backport from mainline r205123: + + 2013-11-20 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_cannot_change_mode_class): Do not + allow subregs of TDmode in FPRs of smaller size in little-endian. + (rs6000_split_multireg_move): When splitting an access to TDmode + in FPRs, do not use simplify_gen_subreg. + + Backport from mainline r204927: + + 2013-11-17 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_emit_move): Use low word of + sdmode_stack_slot also in little-endian mode. + + 2014-04-04 Bill Schmidt + + Power8 HTM Support + Backport from mainline + 2013-12-03 Peter Bergner + + * config/rs6000/htmintrin.h (_TEXASR_INSTRUCTION_FETCH_CONFLICT): Fix + typo in macro name. + (_TEXASRU_INSTRUCTION_FETCH_CONFLICT): Likewise. + + Backport from mainline r205233. + 2013-11-21 Peter Bergner + + * doc/extend.texi: Document htm builtins. + + Backport from mainline + 2013-07-17 Iain Sandoe + + * config/rs6000/darwin.h (REGISTER_NAMES): Add HTM registers. + + Backport from mainline + 2013-07-16 Peter Bergner + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Do not + enable extra ISA flags with TARGET_HTM. + + 2013-07-16 Jakub Jelinek + Peter Bergner + + * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTERS): Mention HTM + registers in the comment. + (DWARF_FRAME_REGISTERS): Subtract also the 3 HTM registers. + (DWARF_REG_TO_UNWIND_COLUMN): Use DWARF_FRAME_REGISTERS + rather than FIRST_PSEUDO_REGISTERS. + + * config.gcc (powerpc*-*-*): Install htmintrin.h and htmxlintrin.h. + * config/rs6000/t-rs6000 (MD_INCLUDES): Add htm.md. + * config/rs6000/rs6000.opt: Add -mhtm option. + * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_HTM. + (ISA_2_7_MASKS_SERVER): Add OPTION_MASK_HTM. + * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define + __HTM__ if the HTM instructions are available. + * config/rs6000/predicates.md (u3bit_cint_operand, u10bit_cint_operand) + (htm_spr_reg_operand): New define_predicates. + * config/rs6000/rs6000.md (define_attr "type"): Add htm. + (TFHAR_REGNO, TFIAR_REGNO, TEXASR_REGNO): New define_constants. + Include htm.md. + * config/rs6000/rs6000-builtin.def (BU_HTM_0, BU_HTM_1, BU_HTM_2) + (BU_HTM_3, BU_HTM_SPR0, BU_HTM_SPR1): Add support macros for defining + HTM builtin functions. + * config/rs6000/rs6000.c (RS6000_BUILTIN_H): New macro. + (rs6000_reg_names, alt_reg_names): Add HTM SPR register names. + (rs6000_init_hard_regno_mode_ok): Add support for HTM instructions. + (rs6000_builtin_mask_calculate): Likewise. + (rs6000_option_override_internal): Likewise. + (bdesc_htm): Add new HTM builtin support. + (htm_spr_num): New function. + (htm_spr_regno): Likewise. + (rs6000_htm_spr_icode): Likewise. + (htm_expand_builtin): Likewise. + (htm_init_builtins): Likewise. + (rs6000_expand_builtin): Add support for HTM builtin functions. + (rs6000_init_builtins): Likewise. + (rs6000_invalid_builtin, rs6000_opt_mask): Add support for -mhtm option. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add support for -mhtm. + (TARGET_HTM, MASK_HTM): Define macros. + (FIRST_PSEUDO_REGISTER): Adjust for new HTM SPR registers. + (FIXED_REGISTERS): Likewise. + (CALL_USED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (enum reg_class): Likewise. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + (REGISTER_NAMES): Likewise. + (ADDITIONAL_REGISTER_NAMES): Likewise. + (RS6000_BTC_SPR, RS6000_BTC_VOID, RS6000_BTC_32BIT, RS6000_BTC_64BIT) + (RS6000_BTC_MISC_MASK, RS6000_BTM_HTM): New macros. + (RS6000_BTM_COMMON): Add RS6000_BTM_HTM. + * config/rs6000/htm.md: New file. + * config/rs6000/htmintrin.h: New file. + * config/rs6000/htmxlintrin.h: New file. + + 2014-04-04 Bill Schmidt + + Power8 Base Support + Apply mainline + 2013-11-23 Alan Modra + * config/rs6000/vsx.md (fusion peepholes): Disable when !TARGET_VSX. + + Backport from mainline + 2013-11-12 Michael Meissner + + PR target/59054 + * config/rs6000/rs6000.md (movdi_internal32): Eliminate + constraints that would allow DImode into the traditional Altivec + registers, but cause undesirable code generation when loading 0 as + a constant. + (movdi_internal64): Likewise. + (cmp_fpr): Do not use %x for CR register output. + (extendsfdf2_fpr): Fix constraints when -mallow-upper-df and + -mallow-upper-sf debug switches are used. + + Backport from mainline + 2013-10-17 Michael Meissner + + * config/rs6000/rs6000.c (enum rs6000_reload_reg_type): Add new + fields to the reg_addr array that describes the valid addressing + mode for any register, general purpose registers, floating point + registers, and Altivec registers. + (FIRST_RELOAD_REG_CLASS): Likewise. + (LAST_RELOAD_REG_CLASS): Likewise. + (struct reload_reg_map_type): Likewise. + (reload_reg_map_type): Likewise. + (RELOAD_REG_VALID): Likewise. + (RELOAD_REG_MULTIPLE): Likewise. + (RELOAD_REG_INDEXED): Likewise. + (RELOAD_REG_OFFSET): Likewise. + (RELOAD_REG_PRE_INCDEC): Likewise. + (RELOAD_REG_PRE_MODIFY): Likewise. + (reg_addr): Likewise. + (mode_supports_pre_incdec_p): New helper functions to say whether + a given mode supports PRE_INC, PRE_DEC, and PRE_MODIFY. + (mode_supports_pre_modify_p): Likewise. + (rs6000_debug_vector_unit): Rearrange the -mdebug=reg output to + print the valid address mode bits for each mode. + (rs6000_debug_print_mode): Likewise. + (rs6000_debug_reg_global): Likewise. + (rs6000_setup_reg_addr_masks): New function to set up the address + mask bits for each type. + (rs6000_init_hard_regno_mode_ok): Use memset to clear arrays. + Call rs6000_setup_reg_addr_masks to set up the address mask bits. + (rs6000_legitimate_address_p): Use mode_supports_pre_incdec_p and + mode_supports_pre_modify_p to determine if PRE_INC, PRE_DEC, and + PRE_MODIFY are supported. + (rs6000_output_move_128bit): Change to use {src,dest}_vmx_p for altivec + registers, instead of {src,dest}_av_p. + (rs6000_print_options_internal): Tweak the debug output slightly. + + Backport from mainline + 2013-10-03 Michael Meissner + + * config/rs6000/rs6000-builtin.def (XSRDPIM): Use floatdf2, + ceildf2, btruncdf2, instead of vsx_* name. + + * config/rs6000/vsx.md (vsx_add3): Change arithmetic + iterators to only do V2DF and V4SF here. Move the DF code to + rs6000.md where it is combined with SF mode. Replace with + just 'v' since only vector operations are handled with these insns + after moving the DF support to rs6000.md. + (vsx_sub3): Likewise. + (vsx_mul3): Likewise. + (vsx_div3): Likewise. + (vsx_fre2): Likewise. + (vsx_neg2): Likewise. + (vsx_abs2): Likewise. + (vsx_nabs2): Likewise. + (vsx_smax3): Likewise. + (vsx_smin3): Likewise. + (vsx_sqrt2): Likewise. + (vsx_rsqrte2): Likewise. + (vsx_fms4): Likewise. + (vsx_nfma4): Likewise. + (vsx_copysign3): Likewise. + (vsx_btrunc2): Likewise. + (vsx_floor2): Likewise. + (vsx_ceil2): Likewise. + (vsx_smaxsf3): Delete scalar ops that were moved to rs6000.md. + (vsx_sminsf3): Likewise. + (vsx_fmadf4): Likewise. + (vsx_fmsdf4): Likewise. + (vsx_nfmadf4): Likewise. + (vsx_nfmsdf4): Likewise. + (vsx_cmpdf_internal1): Likewise. + + * config/rs6000/rs6000.h (TARGET_SF_SPE): Define macros to make it + simpler to select whether a target has SPE or traditional floating + point support in iterators. + (TARGET_DF_SPE): Likewise. + (TARGET_SF_FPR): Likewise. + (TARGET_DF_FPR): Likewise. + (TARGET_SF_INSN): Macros to say whether floating point support + exists for a given operation for expanders. + (TARGET_DF_INSN): Likewise. + + * config/rs6000/rs6000.c (Ftrad): New mode attributes to allow + combining of SF/DF mode operations, using both traditional and VSX + registers. + (Fvsx): Likewise. + (Ff): Likewise. + (Fv): Likewise. + (Fs): Likewise. + (Ffre): Likewise. + (FFRE): Likewise. + (abs2): Combine SF/DF modes using traditional floating point + instructions. Add support for using the upper DF registers with + VSX support, and SF registers with power8-vector support. Update + expanders for operations supported by both the SPE and traditional + floating point units. + (abs2_fpr): Likewise. + (nabs2): Likewise. + (nabs2_fpr): Likewise. + (neg2): Likewise. + (neg2_fpr): Likewise. + (add3): Likewise. + (add3_fpr): Likewise. + (sub3): Likewise. + (sub3_fpr): Likewise. + (mul3): Likewise. + (mul3_fpr): Likewise. + (div3): Likewise. + (div3_fpr): Likewise. + (sqrt3): Likewise. + (sqrt3_fpr): Likewise. + (fre): Likewise. + (rsqrt2): Likewise. + (cmp_fpr): Likewise. + (smax3): Likewise. + (smin3): Likewise. + (smax3_vsx): Likewise. + (smin3_vsx): Likewise. + (negsf2): Delete SF operations that are merged with DF. + (abssf2): Likewise. + (addsf3): Likewise. + (subsf3): Likewise. + (mulsf3): Likewise. + (divsf3): Likewise. + (fres): Likewise. + (fmasf4_fpr): Likewise. + (fmssf4_fpr): Likewise. + (nfmasf4_fpr): Likewise. + (nfmssf4_fpr): Likewise. + (sqrtsf2): Likewise. + (rsqrtsf_internal1): Likewise. + (smaxsf3): Likewise. + (sminsf3): Likewise. + (cmpsf_internal1): Likewise. + (copysign3_fcpsgn): Add VSX/power8-vector support. + (negdf2): Delete DF operations that are merged with SF. + (absdf2): Likewise. + (nabsdf2): Likewise. + (adddf3): Likewise. + (subdf3): Likewise. + (muldf3): Likewise. + (divdf3): Likewise. + (fred): Likewise. + (rsqrtdf_internal1): Likewise. + (fmadf4_fpr): Likewise. + (fmsdf4_fpr): Likewise. + (nfmadf4_fpr): Likewise. + (nfmsdf4_fpr): Likewise. + (sqrtdf2): Likewise. + (smaxdf3): Likewise. + (smindf3): Likewise. + (cmpdf_internal1): Likewise. + (lrintdi2): Use TARGET__FPR macro. + (btrunc2): Delete separate expander, and combine with the + insn and add VSX instruction support. Use TARGET__FPR. + (btrunc2_fpr): Likewise. + (ceil2): Likewise. + (ceil2_fpr): Likewise. + (floor2): Likewise. + (floor2_fpr): Likewise. + (fma4_fpr): Combine SF and DF fused multiply/add support. + Add support for using the upper registers with VSX and + power8-vector. Move insns to be closer to the define_expands. On + VSX systems, prefer the traditional form of FMA over the VSX + version, since the traditional form allows the target not to + overlap with the inputs. + (fms4_fpr): Likewise. + (nfma4_fpr): Likewise. + (nfms4_fpr): Likewise. + + Backport from mainline + 2013-09-27 Michael Meissner + + * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow + DFmode, DImode, and SFmode in the upper VSX registers based on the + -mupper-regs-{df,sf} flags. Fix wu constraint to be ALTIVEC_REGS + if -mpower8-vector. Combine -mvsx-timode handling with the rest + of the VSX register handling. + + * config/rs6000/rs6000.md (f32_lv): Use %x0 for VSX regsters. + (f32_sv): Likewise. + (zero_extendsidi2_lfiwzx): Add support for loading into the + Altivec registers with -mpower8-vector. Use wu/wv constraints to + only do VSX memory options on Altivec registers. + (extendsidi2_lfiwax): Likewise. + (extendsfdf2_fpr): Likewise. + (mov_hardfloat, SF/SD modes): Likewise. + (mov_hardfloat32, DF/DD modes): Likewise. + (mov_hardfloat64, DF/DD modes): Likewise. + (movdi_internal64): Likewise. + + Backport from mainline + 2013-09-23 Michael Meissner + + * config/rs6000/rs6000.c (rs6000_vector_reload): Delete, combine + reload helper function arrays into a single array reg_addr. + (reload_fpr_gpr): Likewise. + (reload_gpr_vsx): Likewise. + (reload_vsx_gpr): Likewise. + (struct rs6000_reg_addr): Likewise. + (reg_addr): Likewise. + (rs6000_debug_reg_global): Change rs6000_vector_reload, + reload_fpr_gpr, reload_gpr_vsx, reload_vsx_gpr uses to reg_addr. + (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_secondary_reload_direct_move): Likewise. + (rs6000_secondary_reload): Likewise. + + * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add new + constraints: wu, ww, and wy. Repurpose wv constraint added during + power8 changes. Put wg constraint in alphabetical order. + + * config/rs6000/rs6000.opt (-mvsx-scalar-float): New debug switch + for future work to add ISA 2.07 VSX single precision support. + (-mvsx-scalar-double): Change default from -1 to 1, update + documentation comment. + (-mvsx-scalar-memory): Rename debug switch to -mupper-regs-df. + (-mupper-regs-df): New debug switch to control whether DF values + can go in the traditional Altivec registers. + (-mupper-regs-sf): New debug switch to control whether SF values + can go in the traditional Altivec registers. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print wu, ww, + and wy constraints. + (rs6000_init_hard_regno_mode_ok): Use ssize_t instead of int for + loop variables. Rename -mvsx-scalar-memory to -mupper-regs-df. + Add new constraints, wu/ww/wy. Repurpose wv constraint. + (rs6000_debug_legitimate_address_p): Print if we are running + before, during, or after reload. + (rs6000_secondary_reload): Add a comment. + (rs6000_opt_masks): Add -mupper-regs-df, -mupper-regs-sf. + + * config/rs6000/constraints.md (wa constraint): Sort w + constraints. Update documentation string. + (wd constraint): Likewise. + (wf constraint): Likewise. + (wg constraint): Likewise. + (wn constraint): Likewise. + (ws constraint): Likewise. + (wt constraint): Likewise. + (wx constraint): Likewise. + (wz constraint): Likewise. + (wu constraint): New constraint for ISA 2.07 SFmode scalar + instructions. + (ww constraint): Likewise. + (wy constraint): Likewise. + (wv constraint): Repurpose ISA 2.07 constraint that did not use in + the previous submissions. + * doc/md.texi (PowerPC and IBM RS6000): Likewise. + + Backport from mainline + 2013-10-17 Michael Meissner + + PR target/58673 + * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Only + restrict TImode addresses to single indirect registers if both + -mquad-memory and -mvsx-timode are used. + (rs6000_output_move_128bit): Use quad_load_store_p to determine if + we should emit load/store quad. Remove using %y for quad memory + addresses. + + * config/rs6000/rs6000.md (mov_ppc64, TI/PTImode): Add + constraints to allow load/store quad on machines where TImode is + not allowed in VSX registers. Use 'n' instead of 'F' constraint + for TImode to load integer constants. + + Backport from mainline + 2013-10-02 Michael Meissner + + PR target/58587 + * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Turn off + setting -mvsx-timode by default until the underlying problem is + fixed. + (RS6000_CPU, power7 defaults): Likewise. + + Backport from trunk + 2013-08-16 Michael Meissner + + PR target/58160 + * config/rs6000/predicates.md (fusion_gpr_mem_load): Allow the + memory rtx to contain ZERO_EXTEND and SIGN_EXTEND. + + * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): Pass operands + array instead of each individual operand as a separate argument. + (emit_fusion_gpr_load): Likewise. + (expand_fusion_gpr_load): Add new function declaration. + + * config/rs6000/rs6000.c (fusion_gpr_load_p): Change the calling + signature to have the operands passed as an array, instead of as + separate arguments. Allow ZERO_EXTEND to be in the memory + address, and also SIGN_EXTEND if -mpower8-fusion-sign. Do not + depend on the register live/dead flags when peepholes are run. + (expand_fusion_gpr_load): New function to be called from the + peephole2 pass, to change the register that addis sets to be the + target register. + (emit_fusion_gpr_load): Change the calling signature to have the + operands passed as an array, instead of as separate arguments. + Allow ZERO_EXTEND to be in the memory address, and also + SIGN_EXTEND if -mpower8-fusion-sign. + + * config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): Delete unused + unspec enumeration. + (power8 fusion peephole/peephole2): Rework the fusion peepholes to + adjust the register addis loads up in the peephole2 pass. Do not + depend on the register live/dead state when the peephole pass is + done. + + Backport from trunk + 2013-07-23 Michael Meissner + + * config/rs6000/vector.md (xor3): Move 128-bit boolean + expanders to rs6000.md. + (ior3): Likewise. + (and3): Likewise. + (one_cmpl2): Likewise. + (nor3): Likewise. + (andc3): Likewise. + (eqv3): Likewise. + (nand3): Likewise. + (orc3): Likewise. + + * config/rs6000/rs6000-protos.h (rs6000_split_logical): New + declaration. + + * config/rs6000/rs6000.c (rs6000_split_logical_inner): Add support + to split multi-word logical operations. + (rs6000_split_logical_di): Likewise. + (rs6000_split_logical): Likewise. + + * config/rs6000/vsx.md (VSX_L2): Delete, no longer used. + (vsx_and3_32bit): Move 128-bit logical insns to rs6000.md, + and allow TImode operations in 32-bit. + (vsx_and3_64bit): Likewise. + (vsx_ior3_32bit): Likewise. + (vsx_ior3_64bit): Likewise. + (vsx_xor3_32bit): Likewise. + (vsx_xor3_64bit): Likewise. + (vsx_one_cmpl2_32bit): Likewise. + (vsx_one_cmpl2_64bit): Likewise. + (vsx_nor3_32bit): Likewise. + (vsx_nor3_64bit): Likewise. + (vsx_andc3_32bit): Likewise. + (vsx_andc3_64bit): Likewise. + (vsx_eqv3_32bit): Likewise. + (vsx_eqv3_64bit): Likewise. + (vsx_nand3_32bit): Likewise. + (vsx_nand3_64bit): Likewise. + (vsx_orc3_32bit): Likewise. + (vsx_orc3_64bit): Likewise. + + * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Always allow vector + logical types in GPRs. + + * config/rs6000/altivec.md (altivec_and3): Move 128-bit + logical insns to rs6000.md, and allow TImode operations in + 32-bit. + (altivec_ior3): Likewise. + (altivec_xor3): Likewise. + (altivec_one_cmpl2): Likewise. + (altivec_nor3): Likewise. + (altivec_andc3): Likewise. + + * config/rs6000/rs6000.md (BOOL_128): New mode iterators and mode + attributes for moving the 128-bit logical operations into + rs6000.md. + (BOOL_REGS_OUTPUT): Likewise. + (BOOL_REGS_OP1): Likewise. + (BOOL_REGS_OP2): Likewise. + (BOOL_REGS_UNARY): Likewise. + (BOOL_REGS_AND_CR0): Likewise. + (one_cmpl2): Add support for DI logical operations on + 32-bit, splitting the operations to 32-bit. + (anddi3): Likewise. + (iordi3): Likewise. + (xordi3): Likewise. + (and3, 128-bit types): Rewrite 2013-06-06 logical operator + changes to combine the 32/64-bit code, allow logical operations on + TI mode in 32-bit, and to use similar match_operator patterns like + scalar mode uses. Combine the Altivec and VSX code for logical + operations, and move it here. + (ior3, 128-bit types): Likewise. + (xor3, 128-bit types): Likewise. + (one_cmpl3, 128-bit types): Likewise. + (nor3, 128-bit types): Likewise. + (andc3, 128-bit types): Likewise. + (eqv3, 128-bit types): Likewise. + (nand3, 128-bit types): Likewise. + (orc3, 128-bit types): Likewise. + (and3_internal): Likewise. + (bool3_internal): Likewise. + (boolc3_internal1): Likewise. + (boolc3_internal2): Likewise. + (boolcc3_internal1): Likewise. + (boolcc3_internal2): Likewise. + (eqv3_internal1): Likewise. + (eqv3_internal2): Likewise. + (one_cmpl13_internal): Likewise. + + Back port from mainline: + 2013-06-06 Michael Meissner + Pat Haugen + Peter Bergner + + * lib/target-supports.exp (check_p8vector_hw_available) Add power8 + support. + (check_effective_target_powerpc_p8vector_ok): Likewise. + (is-effective-target): Likewise. + (check_vect_support_and_set_flags): Likewise. + + Backport from mainline + 2013-07-31 Michael Meissner + + * config/rs6000/predicates.md (fusion_gpr_addis): New predicates + to support power8 load fusion. + (fusion_gpr_mem_load): Likewise. + + * config/rs6000/rs6000-modes.def (PTImode): Update a comment. + + * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): New + declarations for power8 load fusion. + (emit_fusion_gpr_load): Likewise. + + * config/rs6000/rs6000.c (rs6000_option_override_internal): If + tuning for power8, turn on fusion mode by default. Turn on sign + extending fusion mode if normal fusion mode is on, and we are at + -O2 or -O3. + (fusion_gpr_load_p): New function, return true if we can fuse an + addis instruction with a dependent load to a GPR. + (emit_fusion_gpr_load): Emit the instructions for power8 load + fusion to GPRs. + + * config/rs6000/vsx.md (VSX_M2): New iterator for fusion + peepholes. + (VSX load fusion peepholes): New peepholes to fuse together an + addi instruction with a VSX load instruction. + + * config/rs6000/rs6000.md (GPR load fusion peepholes): New + peepholes to fuse an addis instruction with a load to a GPR base + register. If we are supporting sign extending fusions, convert + sign extending loads to zero extending loads and add an explicit + sign extension. + + Backport from mainline + 2013-07-18 Pat Haugen + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Adjust flag + interaction for new Power8 flags and VSX. + + Back port from the trunk + 2013-06-28 Michael Meissner + + PR target/57744 + * config/rs6000/rs6000.h (MODES_TIEABLE_P): Do not allow PTImode + to tie with any other modes. Eliminate Altivec vector mode tests, + since these are a subset of ALTIVEC or VSX vector modes. Simplify + code, to return 0 if testing MODE2 for a condition, if we've + already tested MODE1 for the same condition. + + Backport from mainline + 2013-06-28 Pat Haugen + + * config/rs6000/rs6000.md (define_insn ""): Fix insn type. + + Back port from the trunk + 2013-06-26 Michael Meissner + Pat Haugen + Peter Bergner + + * config/rs6000/power8.md: New. + * config/rs6000/rs6000-cpus.def (RS6000_CPU table): Adjust processor + setting for power8 entry. + * config/rs6000/t-rs6000 (MD_INCLUDES): Add power8.md. + * config/rs6000/rs6000.c (is_microcoded_insn, is_cracked_insn): Adjust + test for Power4/Power5 only. + (insn_must_be_first_in_group, insn_must_be_last_in_group): Add Power8 + support. + (force_new_group): Adjust comment. + * config/rs6000/rs6000.md: Include power8.md. + + Back port from the trunk + 2013-06-14 Michael Meissner + + PR target/57615 + * config/rs6000/rs6000.md (mov_ppc64): Call + rs6000_output_move_128bit to handle emitting quad memory + operations. Set attribute length to 8 bytes. + + Back port from the trunk + 2013-06-13 Michael Meissner + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Move + test for clearing quad memory on 32-bit later. + + Back port from the trunk + + 2013-06-12 Michael Meissner + Pat Haugen + Peter Bergner + + * config/rs6000/rs6000.c (emit_load_locked): Add support for + power8 byte, half-word, and quad-word atomic instructions. + (emit_store_conditional): Likewise. + (rs6000_expand_atomic_compare_and_swap): Likewise. + (rs6000_expand_atomic_op): Likewise. + + * config/rs6000/sync.md (larx): Add new modes for power8. + (stcx): Likewise. + (AINT): New mode iterator to include TImode as well as normal + integer modes on power8. + (fetchop_pred): Use int_reg_operand instead of gpc_reg_operand so + that VSX registers are not considered. Use AINT mode iterator + instead of INT1 to allow inclusion of quad word atomic operations + on power8. + (load_locked): Likewise. + (store_conditional): Likewise. + (atomic_compare_and_swap): Likewise. + (atomic_exchange): Likewise. + (atomic_nand): Likewise. + (atomic_fetch_): Likewise. + (atomic_nand_fetch): Likewise. + (mem_thread_fence): Use gen_loadsync_ instead of enumerating + each type. + (ATOMIC): On power8, add QImode, HImode modes. + (load_locked_si): Varients of load_locked for QI/HI + modes that promote to SImode. + (load_lockedti): Convert TImode arguments to PTImode, so that we + get a guaranteed even/odd register pair. + (load_lockedpti): Likewise. + (store_conditionalti): Likewise. + (store_conditionalpti): Likewise. + + * config/rs6000/rs6000.md (QHI): New mode iterator for power8 + atomic load/store instructions. + (HSI): Likewise. + + Back port from the trunk + + 2013-06-10 Michael Meissner + Pat Haugen + Peter Bergner + + * config/rs6000/vector.md (GPR move splitter): Do not split moves + of vectors in GPRS if they are direct moves or quad word load or + store moves. + + * config/rs6000/rs6000-protos.h (rs6000_output_move_128bit): Add + declaration. + (direct_move_p): Likewise. + (quad_load_store_p): Likewise. + + * config/rs6000/rs6000.c (enum rs6000_reg_type): Simplify register + classes into bins based on the physical register type. + (reg_class_to_reg_type): Likewise. + (IS_STD_REG_TYPE): Likewise. + (IS_FP_VECT_REG_TYPE): Likewise. + (reload_fpr_gpr): Arrays to determine what insn to use if we can + use direct move instructions. + (reload_gpr_vsx): Likewise. + (reload_vsx_gpr): Likewise. + (rs6000_init_hard_regno_mode_ok): Precalculate the register type + information that is a simplification of register classes. Also + precalculate direct move reload helpers. + (direct_move_p): New function to return true if the operation can + be done as a direct move instruciton. + (quad_load_store_p): New function to return true if the operation + is a quad memory operation. + (rs6000_legitimize_address): If quad memory, only allow register + indirect for TImode addresses. + (rs6000_legitimate_address_p): Likewise. + (enum reload_reg_type): Delete, replace with rs6000_reg_type. + (rs6000_reload_register_type): Likewise. + (register_to_reg_type): Return register type. + (rs6000_secondary_reload_simple_move): New helper function for + secondary reload and secondary memory needed to identify anything + that is a simple move, and does not need reloading. + (rs6000_secondary_reload_direct_move): New helper function for + secondary reload to identify cases that can be done with several + instructions via the direct move instructions. + (rs6000_secondary_reload_move): New helper function for secondary + reload to identify moves between register types that can be done. + (rs6000_secondary_reload): Add support for quad memory operations + and for direct move. + (rs6000_secondary_memory_needed): Likewise. + (rs6000_debug_secondary_memory_needed): Change argument names. + (rs6000_output_move_128bit): New function to return the move to + use for 128-bit moves, including knowing about the various + limitations of quad memory operations. + + * config/rs6000/vsx.md (vsx_mov): Add support for quad + memory operations. call rs6000_output_move_128bit for the actual + instruciton(s) to generate. + (vsx_movti_64bit): Likewise. + + * config/rs6000/rs6000.md (UNSPEC_P8V_FMRGOW): New unspec values. + (UNSPEC_P8V_MTVSRWZ): Likewise. + (UNSPEC_P8V_RELOAD_FROM_GPR): Likewise. + (UNSPEC_P8V_MTVSRD): Likewise. + (UNSPEC_P8V_XXPERMDI): Likewise. + (UNSPEC_P8V_RELOAD_FROM_VSX): Likewise. + (UNSPEC_FUSION_GPR): Likewise. + (FMOVE128_GPR): New iterator for direct move. + (f32_lv): New mode attribute for load/store of SFmode/SDmode + values. + (f32_sv): Likewise. + (f32_dm): Likewise. + (zero_extenddi2_internal1): Add support for power8 32-bit + loads and direct move instructions. + (zero_extendsidi2_lfiwzx): Likewise. + (extendsidi2_lfiwax): Likewise. + (extendsidi2_nocell): Likewise. + (floatsi2_lfiwax): Likewise. + (lfiwax): Likewise. + (floatunssi2_lfiwzx): Likewise. + (lfiwzx): Likewise. + (fix_trunc_stfiwx): Likewise. + (fixuns_trunc_stfiwx): Likewise. + (mov_hardfloat, 32-bit floating point): Likewise. + (mov_hardfloat64, 64-bit floating point): Likewise. + (parity2_cmpb): Set length/type attr. + (unnamed shift right patterns, mov_internal2): Change type attr + for 'mr.' to fast_compare. + (bpermd_): Change type attr to popcnt. + (p8_fmrgow_): New insns for power8 direct move support. + (p8_mtvsrwz_1): Likewise. + (p8_mtvsrwz_2): Likewise. + (reload_fpr_from_gpr): Likewise. + (p8_mtvsrd_1): Likewise. + (p8_mtvsrd_2): Likewise. + (p8_xxpermdi_): Likewise. + (reload_vsx_from_gpr): Likewise. + (reload_vsx_from_gprsf): Likewise. + (p8_mfvsrd_3_): LIkewise. + (reload_gpr_from_vsx): Likewise. + (reload_gpr_from_vsxsf): Likewise. + (p8_mfvsrd_4_disf): Likewise. + (multi-word GPR splits): Do not split direct moves or quad memory + operations. + + Backport from the trunk + + 2013-06-06 Michael Meissner + Pat Haugen + Peter Bergner + + * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): + Document new power8 builtins. + + * config/rs6000/vector.md (and3): Add a clobber/scratch of a + condition code register, to allow 128-bit logical operations to be + done in the VSX or GPR registers. + (nor3): Use the canonical form for nor. + (eqv3): Add expanders for power8 xxleqv, xxlnand, xxlorc, + vclz*, and vpopcnt* vector instructions. + (nand3): Likewise. + (orc3): Likewise. + (clz2): LIkewise. + (popcount2): Likewise. + + * config/rs6000/predicates.md (int_reg_operand): Rework tests so + that only the GPRs are recognized. + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + support for new power8 builtins. + + * config/rs6000/rs6000-builtin.def (xscvspdpn): Add new power8 + builtin functions. + (xscvdpspn): Likewise. + (vclz): Likewise. + (vclzb): Likewise. + (vclzh): Likewise. + (vclzw): Likewise. + (vclzd): Likewise. + (vpopcnt): Likewise. + (vpopcntb): Likewise. + (vpopcnth): Likewise. + (vpopcntw): Likewise. + (vpopcntd): Likewise. + (vgbbd): Likewise. + (vmrgew): Likewise. + (vmrgow): Likewise. + (eqv): Likewise. + (eqv_v16qi3): Likewise. + (eqv_v8hi3): Likewise. + (eqv_v4si3): Likewise. + (eqv_v2di3): Likewise. + (eqv_v4sf3): Likewise. + (eqv_v2df3): Likewise. + (nand): Likewise. + (nand_v16qi3): Likewise. + (nand_v8hi3): Likewise. + (nand_v4si3): Likewise. + (nand_v2di3): Likewise. + (nand_v4sf3): Likewise. + (nand_v2df3): Likewise. + (orc): Likewise. + (orc_v16qi3): Likewise. + (orc_v8hi3): Likewise. + (orc_v4si3): Likewise. + (orc_v2di3): Likewise. + (orc_v4sf3): Likewise. + (orc_v2df3): Likewise. + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Only + allow power8 quad mode in 64-bit. + (rs6000_builtin_vectorized_function): Add support to vectorize + ISA 2.07 count leading zeros, population count builtins. + (rs6000_expand_vector_init): On ISA 2.07 use xscvdpspn to form + V4SF vectors instead of xscvdpsp to avoid IEEE related traps. + (builtin_function_type): Add vgbbd builtin function which takes an + unsigned argument. + (altivec_expand_vec_perm_const): Add support for new power8 merge + instructions. + + * config/rs6000/vsx.md (VSX_L2): New iterator for 128-bit types, + that does not include TImdoe for use with 32-bit. + (UNSPEC_VSX_CVSPDPN): Support for power8 xscvdpspn and xscvspdpn + instructions. + (UNSPEC_VSX_CVDPSPN): Likewise. + (vsx_xscvdpspn): Likewise. + (vsx_xscvspdpn): Likewise. + (vsx_xscvdpspn_scalar): Likewise. + (vsx_xscvspdpn_directmove): Likewise. + (vsx_and3): Split logical operations into 32-bit and + 64-bit. Add support to do logical operations on TImode as well as + VSX vector types. Allow logical operations to be done in either + VSX registers or in general purpose registers in 64-bit mode. Add + splitters if GPRs were used. For AND, add clobber of CCmode to + allow use of ANDI on GPRs. Rewrite nor to use the canonical RTL + encoding. + (vsx_and3_32bit): Likewise. + (vsx_and3_64bit): Likewise. + (vsx_ior3): Likewise. + (vsx_ior3_32bit): Likewise. + (vsx_ior3_64bit): Likewise. + (vsx_xor3): Likewise. + (vsx_xor3_32bit): Likewise. + (vsx_xor3_64bit): Likewise. + (vsx_one_cmpl2): Likewise. + (vsx_one_cmpl2_32bit): Likewise. + (vsx_one_cmpl2_64bit): Likewise. + (vsx_nor3): Likewise. + (vsx_nor3_32bit): Likewise. + (vsx_nor3_64bit): Likewise. + (vsx_andc3): Likewise. + (vsx_andc3_32bit): Likewise. + (vsx_andc3_64bit): Likewise. + (vsx_eqv3_32bit): Add support for power8 xxleqv, xxlnand, + and xxlorc instructions. + (vsx_eqv3_64bit): Likewise. + (vsx_nand3_32bit): Likewise. + (vsx_nand3_64bit): Likewise. + (vsx_orc3_32bit): Likewise. + (vsx_orc3_64bit): Likewise. + + * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Update comment. + + * config/rs6000/altivec.md (UNSPEC_VGBBD): Add power8 vgbbd + instruction. + (p8_vmrgew): Add power8 vmrgew and vmrgow instructions. + (p8_vmrgow): Likewise. + (altivec_and3): Add clobber of CCmode to allow AND using + GPRs to be split under VSX. + (p8v_clz2): Add power8 count leading zero support. + (p8v_popcount2): Add power8 population count support. + (p8v_vgbbd): Add power8 gather bits by bytes by doubleword + support. + + * config/rs6000/rs6000.md (eqv3): Add support for powerp eqv + instruction. + + * config/rs6000/altivec.h (vec_eqv): Add defines to export power8 + builtin functions. + (vec_nand): Likewise. + (vec_vclz): Likewise. + (vec_vclzb): Likewise. + (vec_vclzd): Likewise. + (vec_vclzh): Likewise. + (vec_vclzw): Likewise. + (vec_vgbbd): Likewise. + (vec_vmrgew): Likewise. + (vec_vmrgow): Likewise. + (vec_vpopcnt): Likewise. + (vec_vpopcntb): Likewise. + (vec_vpopcntd): Likewise. + (vec_vpopcnth): Likewise. + (vec_vpopcntw): Likewise. + + Backport from trunk + + 2013-05-29 Michael Meissner + Pat Haugen + Peter Bergner + + * config/rs6000/vector.md (VEC_I): Add support for new power8 V2DI + instructions. + (VEC_A): Likewise. + (VEC_C): Likewise. + (vrotl3): Likewise. + (vashl3): Likewise. + (vlshr3): Likewise. + (vashr3): Likewise. + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + support for power8 V2DI builtins. + + * config/rs6000/rs6000-builtin.def (abs_v2di): Add support for + power8 V2DI builtins. + (vupkhsw): Likewise. + (vupklsw): Likewise. + (vaddudm): Likewise. + (vminsd): Likewise. + (vmaxsd): Likewise. + (vminud): Likewise. + (vmaxud): Likewise. + (vpkudum): Likewise. + (vpksdss): Likewise. + (vpkudus): Likewise. + (vpksdus): Likewise. + (vrld): Likewise. + (vsld): Likewise. + (vsrd): Likewise. + (vsrad): Likewise. + (vsubudm): Likewise. + (vcmpequd): Likewise. + (vcmpgtsd): Likewise. + (vcmpgtud): Likewise. + (vcmpequd_p): Likewise. + (vcmpgtsd_p): Likewise. + (vcmpgtud_p): Likewise. + (vupkhsw): Likewise. + (vupklsw): Likewise. + (vaddudm): Likewise. + (vmaxsd): Likewise. + (vmaxud): Likewise. + (vminsd): Likewise. + (vminud): Likewise. + (vpksdss): Likewise. + (vpksdus): Likewise. + (vpkudum): Likewise. + (vpkudus): Likewise. + (vrld): Likewise. + (vsld): Likewise. + (vsrad): Likewise. + (vsrd): Likewise. + (vsubudm): Likewise. + + * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add + support for power8 V2DI instructions. + + * config/rs6000/altivec.md (UNSPEC_VPKUHUM): Add support for + power8 V2DI instructions. Combine pack and unpack insns to use an + iterator for each mode. Check whether a particular mode supports + Altivec instructions instead of just checking TARGET_ALTIVEC. + (UNSPEC_VPKUWUM): Likewise. + (UNSPEC_VPKSHSS): Likewise. + (UNSPEC_VPKSWSS): Likewise. + (UNSPEC_VPKUHUS): Likewise. + (UNSPEC_VPKSHUS): Likewise. + (UNSPEC_VPKUWUS): Likewise. + (UNSPEC_VPKSWUS): Likewise. + (UNSPEC_VPACK_SIGN_SIGN_SAT): Likewise. + (UNSPEC_VPACK_SIGN_UNS_SAT): Likewise. + (UNSPEC_VPACK_UNS_UNS_SAT): Likewise. + (UNSPEC_VPACK_UNS_UNS_MOD): Likewise. + (UNSPEC_VUPKHSB): Likewise. + (UNSPEC_VUNPACK_HI_SIGN): Likewise. + (UNSPEC_VUNPACK_LO_SIGN): Likewise. + (UNSPEC_VUPKHSH): Likewise. + (UNSPEC_VUPKLSB): Likewise. + (UNSPEC_VUPKLSH): Likewise. + (VI2): Likewise. + (VI_char): Likewise. + (VI_scalar): Likewise. + (VI_unit): Likewise. + (VP): Likewise. + (VP_small): Likewise. + (VP_small_lc): Likewise. + (VU_char): Likewise. + (add3): Likewise. + (altivec_vaddcuw): Likewise. + (altivec_vaddus): Likewise. + (altivec_vaddss): Likewise. + (sub3): Likewise. + (altivec_vsubcuw): Likewise. + (altivec_vsubus): Likewise. + (altivec_vsubss): Likewise. + (altivec_vavgs): Likewise. + (altivec_vcmpbfp): Likewise. + (altivec_eq): Likewise. + (altivec_gt): Likewise. + (altivec_gtu): Likewise. + (umax3): Likewise. + (smax3): Likewise. + (umin3): Likewise. + (smin3): Likewise. + (altivec_vpkuhum): Likewise. + (altivec_vpkuwum): Likewise. + (altivec_vpkshss): Likewise. + (altivec_vpkswss): Likewise. + (altivec_vpkuhus): Likewise. + (altivec_vpkshus): Likewise. + (altivec_vpkuwus): Likewise. + (altivec_vpkswus): Likewise. + (altivec_vpksss): Likewise. + (altivec_vpksus): Likewise. + (altivec_vpkuus): Likewise. + (altivec_vpkuum): Likewise. + (altivec_vrl): Likewise. + (altivec_vsl): Likewise. + (altivec_vsr): Likewise. + (altivec_vsra): Likewise. + (altivec_vsldoi_): Likewise. + (altivec_vupkhsb): Likewise. + (altivec_vupkhs): Likewise. + (altivec_vupkls): Likewise. + (altivec_vupkhsh): Likewise. + (altivec_vupklsb): Likewise. + (altivec_vupklsh): Likewise. + (altivec_vcmpequ_p): Likewise. + (altivec_vcmpgts_p): Likewise. + (altivec_vcmpgtu_p): Likewise. + (abs2): Likewise. + (vec_unpacks_hi_v16qi): Likewise. + (vec_unpacks_hi_v8hi): Likewise. + (vec_unpacks_lo_v16qi): Likewise. + (vec_unpacks_hi_): Likewise. + (vec_unpacks_lo_v8hi): Likewise. + (vec_unpacks_lo_): Likewise. + (vec_pack_trunc_v8h): Likewise. + (vec_pack_trunc_v4si): Likewise. + (vec_pack_trunc_): Likewise. + + * config/rs6000/altivec.h (vec_vaddudm): Add defines for power8 + V2DI builtins. + (vec_vmaxsd): Likewise. + (vec_vmaxud): Likewise. + (vec_vminsd): Likewise. + (vec_vminud): Likewise. + (vec_vpksdss): Likewise. + (vec_vpksdus): Likewise. + (vec_vpkudum): Likewise. + (vec_vpkudus): Likewise. + (vec_vrld): Likewise. + (vec_vsld): Likewise. + (vec_vsrad): Likewise. + (vec_vsrd): Likewise. + (vec_vsubudm): Likewise. + (vec_vupkhsw): Likewise. + (vec_vupklsw): Likewise. + + 2013-05-22 Michael Meissner + Pat Haugen + Peter Bergner + + * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add + documentation for the power8 crypto builtins. + + * config/rs6000/t-rs6000 (MD_INCLUDES): Add crypto.md. + + * config/rs6000/rs6000-builtin.def (BU_P8V_AV_1): Add support + macros for defining power8 builtin functions. + (BU_P8V_AV_2): Likewise. + (BU_P8V_AV_P): Likewise. + (BU_P8V_VSX_1): Likewise. + (BU_P8V_OVERLOAD_1): Likewise. + (BU_P8V_OVERLOAD_2): Likewise. + (BU_CRYPTO_1): Likewise. + (BU_CRYPTO_2): Likewise. + (BU_CRYPTO_3): Likewise. + (BU_CRYPTO_OVERLOAD_1): Likewise. + (BU_CRYPTO_OVERLOAD_2): Likewise. + (XSCVSPDP): Fix typo, point to the correct instruction. + (VCIPHER): Add power8 crypto builtins. + (VCIPHERLAST): Likewise. + (VNCIPHER): Likewise. + (VNCIPHERLAST): Likewise. + (VPMSUMB): Likewise. + (VPMSUMH): Likewise. + (VPMSUMW): Likewise. + (VPERMXOR_V2DI): Likewise. + (VPERMXOR_V4SI: Likewise. + (VPERMXOR_V8HI: Likewise. + (VPERMXOR_V16QI: Likewise. + (VSHASIGMAW): Likewise. + (VSHASIGMAD): Likewise. + (VPMSUM): Likewise. + (VPERMXOR): Likewise. + (VSHASIGMA): Likewise. + + * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define + __CRYPTO__ if the crypto instructions are available. + (altivec_overloaded_builtins): Add support for overloaded power8 + builtins. + + * config/rs6000/rs6000.c (rs6000_expand_ternop_builtin): Add + support for power8 crypto builtins. + (builtin_function_type): Likewise. + (altivec_init_builtins): Add support for builtins that take vector + long long (V2DI) arguments. + + * config/rs6000/crypto.md: New file, define power8 crypto + instructions. + + 2013-05-22 Michael Meissner + Pat Haugen + Peter Bergner + + * doc/invoke.texi (Option Summary): Add power8 options. + (RS/6000 and PowerPC Options): Likewise. + + * doc/md.texi (PowerPC and IBM RS6000 constraints): Update to use + constraints.md instead of rs6000.h. Reorder w* constraints. Add + wm, wn, wr documentation. + + * gcc/config/rs6000/constraints.md (wm): New constraint for VSX + registers if direct move instructions are enabled. + (wn): New constraint for no registers. + (wq): New constraint for quad word even GPR registers. + (wr): New constraint if 64-bit instructions are enabled. + (wv): New constraint if power8 vector instructions are enabled. + (wQ): New constraint for quad word memory locations. + + * gcc/config/rs6000/predicates.md (const_0_to_15_operand): New + constraint for 0..15 for crypto instructions. + (gpc_reg_operand): If VSX allow registers in VSX registers as well + as GPR and floating point registers. + (int_reg_operand): New predicate to match only GPR registers. + (base_reg_operand): New predicate to match base registers. + (quad_int_reg_operand): New predicate to match even GPR registers + for quad memory operations. + (vsx_reg_or_cint_operand): New predicate to allow vector logical + operations in both GPR and VSX registers. + (quad_memory_operand): New predicate for quad memory operations. + (reg_or_indexed_operand): New predicate for direct move support. + + * gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): + Inherit from ISA_2_4_MASKS, not ISA_2_2_MASKS. + (ISA_2_7_MASKS_SERVER): New mask for ISA 2.07 (i.e. power8). + (POWERPC_MASKS): Add power8 options. + (power8 cpu): Use ISA_2_7_MASKS_SERVER instead of specifying the + various options. + + * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros): + Define _ARCH_PWR8 and __POWER8_VECTOR__ for power8. + + * gcc/config/rs6000/rs6000.opt (-mvsx-timode): Add documentation. + (-mpower8-fusion): New power8 options. + (-mpower8-fusion-sign): Likewise. + (-mpower8-vector): Likewise. + (-mcrypto): Likewise. + (-mdirect-move): Likewise. + (-mquad-memory): Likewise. + + * gcc/config/rs6000/rs6000.c (power8_cost): Initial definition for + power8. + (rs6000_hard_regno_mode_ok): Make PTImode only match even GPR + registers. + (rs6000_debug_reg_print): Print the base register class if + -mdebug=reg. + (rs6000_debug_vector_unit): Add p8_vector. + (rs6000_debug_reg_global): If -mdebug=reg, print power8 constraint + definitions. Also print fusion state. + (rs6000_init_hard_regno_mode_ok): Set up power8 constraints. + (rs6000_builtin_mask_calculate): Add power8 builtin support. + (rs6000_option_override_internal): Add support for power8. + (rs6000_common_init_builtins): Add debugging for skipped builtins + if -mdebug=builtin. + (rs6000_adjust_cost): Add power8 support. + (rs6000_issue_rate): Likewise. + (insn_must_be_first_in_group): Likewise. + (insn_must_be_last_in_group): Likewise. + (force_new_group): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + + * config/rs6000/rs6000.h (ASM_CPU_POWER8_SPEC): If we don't have a + power8 capable assembler, default to power7 options. + (TARGET_DIRECT_MOVE): Likewise. + (TARGET_CRYPTO): Likewise. + (TARGET_P8_VECTOR): Likewise. + (VECTOR_UNIT_P8_VECTOR_P): Define power8 vector support. + (VECTOR_UNIT_VSX_OR_P8_VECTOR_P): Likewise. + (VECTOR_MEM_P8_VECTOR_P): Likewise. + (VECTOR_MEM_VSX_OR_P8_VECTOR_P): Likewise. + (VECTOR_MEM_ALTIVEC_OR_VSX_P): Likewise. + (TARGET_XSCVDPSPN): Likewise. + (TARGET_XSCVSPDPN): Likewsie. + (TARGET_SYNC_HI_QI): Likewise. + (TARGET_SYNC_TI): Likewise. + (MASK_CRYPTO): Likewise. + (MASK_DIRECT_MOVE): Likewise. + (MASK_P8_FUSION): Likewise. + (MASK_P8_VECTOR): Likewise. + (REG_ALLOC_ORDER): Move fr13 to be lower in priority so that the + TFmode temporary used by some of the direct move instructions to + get two FP temporary registers does not force creation of a stack + frame. + (VLOGICAL_REGNO_P): Allow vector logical operations in GPRs. + (MODES_TIEABLE_P): Move the VSX tests above the Altivec tests so + that any VSX registers are tieable, even if they are also an + Altivec vector mode. + (r6000_reg_class_enum): Add wm, wr, wv constraints. + (RS6000_BTM_P8_VECTOR): Power8 builtin support. + (RS6000_BTM_CRYPTO): Likewise. + (RS6000_BTM_COMMON): Likewise. + + * config/rs6000/rs6000.md (cpu attribute): Add power8. + * config/rs6000/rs6000-opts.h (PROCESSOR_POWER8): Likewise. + (enum rs6000_vector): Add power8 vector support. + + + Backport from mainline + 2013-03-20 Pat Haugen + + * config/rs6000/predicates.md (indexed_address, update_address_mem + update_indexed_address_mem): New predicates. + * config/rs6000/vsx.md (vsx_extract__zero): Set correct "type" + attribute for load/store instructions. + * config/rs6000/dfp.md (movsd_store): Likewise. + (movsd_load): Likewise. + * config/rs6000/rs6000.md (zero_extenddi2_internal1): Likewise. + (unnamed HI->DI extend define_insn): Likewise. + (unnamed SI->DI extend define_insn): Likewise. + (unnamed QI->SI extend define_insn): Likewise. + (unnamed QI->HI extend define_insn): Likewise. + (unnamed HI->SI extend define_insn): Likewise. + (unnamed HI->SI extend define_insn): Likewise. + (extendsfdf2_fpr): Likewise. + (movsi_internal1): Likewise. + (movsi_internal1_single): Likewise. + (movhi_internal): Likewise. + (movqi_internal): Likewise. + (movcc_internal1): Correct mnemonic for stw insn. Set correct "type" + attribute for load/store instructions. + (mov_hardfloat): Set correct "type" attribute for load/store + instructions. + (mov_softfloat): Likewise. + (mov_hardfloat32): Likewise. + (mov_hardfloat64): Likewise. + (mov_softfloat64): Likewise. + (movdi_internal32): Likewise. + (movdi_internal64): Likewise. + (probe_stack_): Likewise. + + Backport from mainline + 2013-03-20 Michael Meissner + + * config/rs6000/vector.md (VEC_R): Add 32-bit integer, binary + floating point, and decimal floating point to reload iterator. + + * config/rs6000/constraints.md (wl constraint): New constraints to + return FLOAT_REGS if certain options are used to reduce the number + of separate patterns that exist in the file. + (wx constraint): Likewise. + (wz constraint): Likewise. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): If + -mdebug=reg, print wg, wl, wx, and wz constraints. + (rs6000_init_hard_regno_mode_ok): Initialize new constraints. + Initialize the reload functions for 64-bit binary/decimal floating + point types. + (reg_offset_addressing_ok_p): If we are on a power7 or later, use + LFIWZX and STFIWX to load/store 32-bit decimal types, and don't + create the buffer on the stack to overcome not having a 32-bit + load and store. + (rs6000_emit_move): Likewise. + (rs6000_secondary_memory_needed_rtx): Likewise. + (rs6000_alloc_sdmode_stack_slot): Likewise. + (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f + via xxlxor, just like DFmode 0.0. + + * config/rs6000/rs6000.h (TARGET_NO_SDMODE_STACK): New macro) + (define as 1 if we are running on a power7 or newer. + (enum r6000_reg_class_enum): Add new constraints. + + * config/rs6000/dfp.md (movsd): Delete, combine with binary + floating point moves in rs6000.md. Combine power6x (mfpgpr) moves + with other moves by using conditional constraits (wg). Use LFIWZX + and STFIWX for loading SDmode on power7. Use xxlxor to create + 0.0f. + (movsd splitter): Likewise. + (movsd_hardfloat): Likewise. + (movsd_softfloat): Likewise. + + * config/rs6000/rs6000.md (FMOVE32): New iterators to combine + binary and decimal floating point moves. + (fmove_ok): New attributes to combine binary and decimal floating + point moves, and to combine power6x (mfpgpr) moves along normal + floating moves. + (real_value_to_target): Likewise. + (f32_lr): Likewise. + (f32_lm): Likewise. + (f32_li): Likewise. + (f32_sr): Likewise. + (f32_sm): Likewise. + (f32_si): Likewise. + (movsf): Combine binary and decimal floating point moves. Combine + power6x (mfpgpr) moves with other moves by using conditional + constraits (wg). Use LFIWZX and STFIWX for loading SDmode on + power7. + (mov for SFmode/SDmode); Likewise. + (SFmode/SDmode splitters): Likewise. + (movsf_hardfloat): Likewise. + (mov_hardfloat for SFmode/SDmode): Likewise. + (movsf_softfloat): Likewise. + (mov_softfloat for SFmode/SDmode): Likewise. + + * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wl) + (wx and wz constraints. + + * config/rs6000/constraints.md (wg constraint): New constraint to + return FLOAT_REGS if -mmfpgpr (power6x) was used. + + * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg + constraint. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): If + -mdebug=reg, print wg, wl, wx, and wz constraints. + (rs6000_init_hard_regno_mode_ok): Initialize new constraints. + Initialize the reload functions for 64-bit binary/decimal floating + point types. + (reg_offset_addressing_ok_p): If we are on a power7 or later, use + LFIWZX and STFIWX to load/store 32-bit decimal types, and don't + create the buffer on the stack to overcome not having a 32-bit + load and store. + (rs6000_emit_move): Likewise. + (rs6000_secondary_memory_needed_rtx): Likewise. + (rs6000_alloc_sdmode_stack_slot): Likewise. + (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f + via xxlxor, just like DFmode 0.0. + + + * config/rs6000/dfp.md (movdd): Delete, combine with binary + floating point moves in rs6000.md. Combine power6x (mfpgpr) moves + with other moves by using conditional constraits (wg). Use LFIWZX + and STFIWX for loading SDmode on power7. + (movdd splitters): Likewise. + (movdd_hardfloat32): Likewise. + (movdd_softfloat32): Likewise. + (movdd_hardfloat64_mfpgpr): Likewise. + (movdd_hardfloat64): Likewise. + (movdd_softfloat64): Likewise. + + * config/rs6000/rs6000.md (FMOVE64): New iterators to combine + 64-bit binary and decimal floating point moves. + (FMOVE64X): Likewise. + (movdf): Combine 64-bit binary and decimal floating point moves. + Combine power6x (mfpgpr) moves with other moves by using + conditional constraits (wg). + (mov for DFmode/DDmode): Likewise. + (DFmode/DDmode splitters): Likewise. + (movdf_hardfloat32): Likewise. + (mov_hardfloat32 for DFmode/DDmode): Likewise. + (movdf_softfloat32): Likewise. + (movdf_hardfloat64_mfpgpr): Likewise. + (movdf_hardfloat64): Likewise. + (mov_hardfloat64 for DFmode/DDmode): Likewise. + (movdf_softfloat64): Likewise. + (mov_softfloat64 for DFmode/DDmode): Likewise. + (reload__load): Move to later in the file so they aren't in + the middle of the floating point move insns. + (reload__store): Likewise. + + * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg + constraint. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print out wg + constraint if -mdebug=reg. + (rs6000_initi_hard_regno_mode_ok): Enable wg constraint if + -mfpgpr. Enable using dd reload support if needed. + + * config/rs6000/dfp.md (movtd): Delete, combine with 128-bit + binary and decimal floating point moves in rs6000.md. + (movtd_internal): Likewise. + + * config/rs6000/rs6000.md (FMOVE128): Combine 128-bit binary and + decimal floating point moves. + (movtf): Likewise. + (movtf_internal): Likewise. + (mov_internal, TDmode/TFmode): Likewise. + (movtf_softfloat): Likewise. + (mov_softfloat, TDmode/TFmode): Likewise. + + * config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with + movdi_internal64, using wg constraint for move direct operations. + (movdi_internal64): Likewise. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print + MODES_TIEABLE_P for selected modes. Print the numerical value of + the various virtual registers. Use GPR/FPR first/last values) + (instead of hard coding the register numbers. Print which modes + have reload functions registered. + (rs6000_option_override_internal): If -mdebug=reg, trace the + options settings before/after setting cpu, target and subtarget + settings. + (rs6000_secondary_reload_trace): Improve the RTL dump for + -mdebug=addr and for secondary reload failures in + rs6000_secondary_reload_inner. + (rs6000_secondary_reload_fail): Likewise. + (rs6000_secondary_reload_inner): Likewise. + + * config/rs6000/rs6000.md (FIRST_GPR_REGNO): Add convenience + macros for first/last GPR and FPR registers. + (LAST_GPR_REGNO): Likewise. + (FIRST_FPR_REGNO): Likewise. + (LAST_FPR_REGNO): Likewise. + + * config/rs6000/vector.md (mul3): Use the combined macro + VECTOR_UNIT_ALTIVEC_OR_VSX_P instead of separate calls to + VECTOR_UNIT_ALTIVEC_P and VECTOR_UNIT_VSX_P. + (vcond): Likewise. + (vcondu): Likewise. + (vector_gtu): Likewise. + (vector_gte): Likewise. + (xor3): Don't allow logical operations on TImode in 32-bit + to prevent the compiler from converting DImode operations to + TImode. + (ior3): Likewise. + (and3): Likewise. + (one_cmpl2): Likewise. + (nor3): Likewise. + (andc3): Likewise. + + * config/rs6000/constraints.md (wt constraint): New constraint + that returns VSX_REGS if TImode is allowed in VSX registers. + + * config/rs6000/predicates.md (easy_fp_constant): 0.0f is an easy + constant under VSX. + + * config/rs6000/rs6000-modes.def (PTImode): Define, PTImode is + similar to TImode, but it is restricted to being in the GPRs. + + * config/rs6000/rs6000.opt (-mvsx-timode): New switch to allow + TImode to occupy a single VSX register. + + * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Default to + -mvsx-timode for power7/power8. + (power7 cpu): Likewise. + (power8 cpu): Likewise. + + * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Make + sure that TFmode/TDmode take up two registers if they are ever + allowed in the upper VSX registers. + (rs6000_hard_regno_mode_ok): If -mvsx-timode, allow TImode in VSX + registers. + (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_debug_reg_global): Add debugging for PTImode and wt + constraint. Print if LRA is turned on. + (rs6000_option_override_internal): Give an error if -mvsx-timode + and VSX is not enabled. + (invalid_e500_subreg): Handle PTImode, restricting it to GPRs. If + -mvsx-timode, restrict TImode to reg+reg addressing, and PTImode + to reg+offset addressing. Use PTImode when checking offset + addresses for validity. + (reg_offset_addressing_ok_p): Likewise. + (rs6000_legitimate_offset_address_p): Likewise. + (rs6000_legitimize_address): Likewise. + (rs6000_legitimize_reload_address): Likewise. + (rs6000_legitimate_address_p): Likewise. + (rs6000_eliminate_indexed_memrefs): Likewise. + (rs6000_emit_move): Likewise. + (rs6000_secondary_reload): Likewise. + (rs6000_secondary_reload_inner): Handle PTImode. Allow 64-bit + reloads to fpr registers to continue to use reg+offset addressing) + (but 64-bit reloads to altivec registers need reg+reg addressing. + Drop test for PRE_MODIFY, since VSX loads/stores no longer support + it. Treat LO_SUM like a PLUS operation. + (rs6000_secondary_reload_class): If type is 64-bit, prefer to use + FLOAT_REGS instead of VSX_RGS to allow use of reg+offset + addressing. + (rs6000_cannot_change_mode_class): Do not allow TImode in VSX + registers to share a register with a smaller sized type, since VSX + puts scalars in the upper 64-bits. + (print_operand): Add support for PTImode. + (rs6000_register_move_cost): Use VECTOR_MEM_VSX_P instead of + VECTOR_UNIT_VSX_P to catch types that can be loaded in VSX + registers, but don't have arithmetic support. + (rs6000_memory_move_cost): Add test for VSX. + (rs6000_opt_masks): Add -mvsx-timode. + + * config/rs6000/vsx.md (VSm): Change to use 64-bit aligned moves + for TImode. + (VSs): Likewise. + (VSr): Use wt constraint for TImode. + (VSv): Drop TImode support. + (vsx_movti): Delete, replace with versions for 32-bit and 64-bit. + (vsx_movti_64bit): Likewise. + (vsx_movti_32bit): Likewise. + (vec_store_): Use VSX iterator instead of vector iterator. + (vsx_and3): Delete use of '?' constraint on inputs, just put + one '?' on the appropriate output constraint. Do not allow TImode + logical operations on 32-bit systems. + (vsx_ior3): Likewise. + (vsx_xor3): Likewise. + (vsx_one_cmpl2): Likewise. + (vsx_nor3): Likewise. + (vsx_andc3): Likewise. + (vsx_concat_): Likewise. + (vsx_xxpermdi_): Fix thinko for non V2DF/V2DI modes. + + * config/rs6000/rs6000.h (MASK_VSX_TIMODE): Map from + OPTION_MASK_VSX_TIMODE. + (enum rs6000_reg_class_enum): Add RS6000_CONSTRAINT_wt. + (STACK_SAVEAREA_MODE): Use PTImode instead of TImode. + + * config/rs6000/rs6000.md (INT mode attribute): Add PTImode. + (TI2 iterator): New iterator for TImode, PTImode. + (wd mode attribute): Add values for vector types. + (movti_string): Replace TI move operations with operations for + TImode and PTImode. Add support for TImode being allowed in VSX + registers. + (mov_string, TImode/PTImode): Likewise. + (movti_ppc64): Likewise. + (mov_ppc64, TImode/PTImode): Likewise. + (TI mode splitters): Likewise. + + * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wt + constraint. + + 2014-04-04 Richard Biener + + * tree-ssanames.c (make_ssa_name_fn): Fix assert. + + 2014-04-02 Andreas Krebbel + + * config/s390/s390.c (s390_expand_insv): Use GET_MODE_BITSIZE. + + 2014-04-01 Richard Biener + + * gimple.h (struct gimple_statement_base): Align subcode to + 16 bits. + + 2014-04-01 Sebastian Huber + + * doc/invoke.texi (mapp-regs): Clarify. + + 2014-03-31 H.J. Lu + + PR rtl-optimization/60700 + Backport from mainline + 2013-07-30 Zhenqiang Chen + + PR rtl-optimization/57637 + * function.c (move_insn_for_shrink_wrap): Also check the + GEN set of the LIVE problem for the liveness analysis + if it exists, otherwise give up. + + 2014-03-30 Kaz Kojima + + Backport from mainline + 2014-03-19 Kaz Kojima + + PR target/60039 + * config/sh/sh.md (udivsi3_i1): Clobber R1 register. + + 2014-03-26 Martin Jambor + + PR ipa/60419 + * ipa.c (symtab_remove_unreachable_nodes): Clear thunk and + alias flags of nodes in the border. + + 2014-03-26 Eric Botcazou + + PR rtl-optimization/60452 + * rtlanal.c (rtx_addr_can_trap_p_1): Fix head comment. + : Return 1 for invalid offsets from the frame pointer. + + 2014-03-24 Richard Biener + + PR tree-optimization/60429 + * tree-ssa-structalias.c (get_constraint_for_ptr_offset): Remove + duplicated line. + + 2014-03-23 Eric Botcazou + + PR rtl-optimization/60601 + * bb-reorder.c (fix_up_fall_thru_edges): Test EDGE_FALLTHRU everywhere. + + * gcc.c (eval_spec_function): Initialize save_growing_value. + + 2014-03-20 Jakub Jelinek + + PR target/60568 + * config/i386/i386.c (x86_output_mi_thunk): Surround UNSPEC_GOT + into CONST, put pic register as first operand of PLUS. Use + gen_const_mem for both 32-bit and 64-bit PIC got loads. + + 2014-03-20 Eric Botcazou + + * config/sparc/sparc.c (sparc_do_work_around_errata): Implement work + around for store forwarding issue in the FPU on the UT699. + * config/sparc/sparc.md (in_branch_delay): Return false for single FP + loads and operations if -mfix-ut699 is specified. + (divtf3_hq): Tweak attribute. + (sqrttf2_hq): Likewise. + + 2014-03-18 Kai Tietz + + PR rtl-optimization/56356 + * sdbout.c (sdbout_parms): Verify that parms' + incoming argument is valid. + (sdbout_reg_parms): Likewise. + + 2014-03-18 Eric Botcazou + + * config/sparc/sparc.c (sparc_do_work_around_errata): Speed up and use + proper constant for the store mode. + + 2014-03-17 Mikael Pettersson + Committed by Bill Schmidt + + Backport from mainline: + + 2013-06-20 Joern Rennecke + + PR rtl-optimization/57425 + PR rtl-optimization/57569 + * alias.c (write_dependence_p): Remove parameters mem_mode and + canon_mem_addr. Add parameters x_mode, x_addr and x_canonicalized. + Changed all callers. + (canon_anti_dependence): Get comments and semantics in sync. + Add parameter mem_canonicalized. Changed all callers. + * rtl.h (canon_anti_dependence): Update prototype. + + 2013-06-16 Joern Rennecke + + PR rtl-optimization/57425 + PR rtl-optimization/57569 + * alias.c (write_dependence_p): Add new parameters mem_mode, + canon_mem_addr and mem_canonicalized. Change type of writep to bool. + Changed all callers. + (canon_anti_dependence): New function. + * cse.c (check_dependence): Use canon_anti_dependence. + * cselib.c (cselib_invalidate_mem): Likewise. + * rtl.h (canon_anti_dependence): Declare. + + 2014-03-17 Richard Biener + + Backport from mainline + 2014-03-11 Richard Biener + + PR tree-optimization/60429 + PR tree-optimization/60485 + * tree-ssa-structalias.c (set_union_with_increment): Properly + take into account all fields that overlap the shifted vars. + (do_sd_constraint): Likewise. + (do_ds_constraint): Likewise. + (get_constraint_for_ptr_offset): Likewise. + + 2014-03-15 Eric Botcazou + + * config/sparc/sparc-protos.h (tls_call_delay): Delete. + (eligible_for_call_delay): New prototype. + * config/sparc/sparc.c (tls_call_delay): Rename into... + (eligible_for_call_delay): ...this. Return false if the instruction + cannot be put in the delay slot of a branch. + (eligible_for_restore_insn): Simplify. + (eligible_for_return_delay): Return false if the instruction cannot be + put in the delay slot of a branch and simplify. + (eligible_for_sibcall_delay): Return false if the instruction cannot be + put in the delay slot of a branch. + * config/sparc/sparc.md (fix_ut699): New attribute. + (tls_call_delay): Delete. + (in_call_delay): Reimplement. + (eligible_for_sibcall_delay): Rename into... + (in_sibcall_delay): ...this. + (eligible_for_return_delay): Rename into... + (in_return_delay): ...this. + (in_branch_delay): Reimplement. + (in_uncond_branch_delay): Delete. + (in_annul_branch_delay): Delete. + + 2014-03-14 Georg-Johann Lay + + Backport from 2014-03-14 trunk r208562. + + PR target/59396 + * config/avr/avr.c (avr_set_current_function): Pass function name + through default_strip_name_encoding before sanity checking instead + of skipping the first char of the assembler name. + + 2014-03-13 Georg-Johann Lay + + Backport from 2014-03-13 trunk r208532. + + PR target/60486 + * config/avr/avr.c (avr_out_plus): Swap cc_plus and cc_minus in + calls of avr_out_plus_1. + + 2014-03-13 Joey Ye + + Backport from mainline + 2014-03-12 Thomas Preud'homme + + PR tree-optimization/60454 + * tree-ssa-math-opts.c (find_bswap_1): Fix bswap detection. + + 2014-03-06 Matthias Klose + + * Makefile.in (s-mlib): Only pass MULTIARCH_DIRNAME if + MULTILIB_OSDIRNAMES is not defined. + + 2014-03-06 Jakub Jelinek + + PR tree-optimization/60276 + * tree-vect-data-refs.c (vect_analyze_data_ref_dependence): Avoid + a -Wsign-compare warning. + + * Makefile.in (tree-ssa-uninit.o): Depend on $(PARAMS_H). + + Backport from mainline + 2014-02-21 Jakub Jelinek + + PR tree-optimization/56490 + * params.def (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS): New param. + * tree-ssa-uninit.c: Include params.h. + (compute_control_dep_chain): Add num_calls argument, return false + if it exceed PARAM_UNINIT_CONTROL_DEP_ATTEMPTS param, pass + num_calls to recursive call. + (find_predicates): Change dep_chain into normal array, add num_calls + variable and adjust compute_control_dep_chain caller. + (find_def_preds): Likewise. + + 2014-02-13 Jakub Jelinek + + PR target/43546 + * expr.c (compress_float_constant): If x is a hard register, + extend into a pseudo and then move to x. + + 2014-02-11 Richard Henderson + Jakub Jelinek + + PR debug/59776 + * tree-sra.c (load_assign_lhs_subreplacements): Add VIEW_CONVERT_EXPR + around drhs if type conversion to lacc->type is not useless. + + 2014-02-08 Jakub Jelinek + + PR ipa/60026 + * ipa-cp.c (determine_versionability): Fail at -O0 + or __attribute__((optimize (0))) or -fno-ipa-cp functions. + * tree-sra.c (ipa_sra_preliminary_function_checks): Similarly. + + 2014-02-06 Jakub Jelinek + + PR target/60062 + * tree.h (opts_for_fn): New inline function. + (opt_for_fn): Define. + * config/i386/i386.c (ix86_function_regparm): Use + opt_for_fn (decl, optimize) instead of optimize. + + 2014-02-05 Jakub Jelinek + + PR middle-end/57499 + * tree-eh.c (cleanup_empty_eh): Bail out on totally empty + bb with no successors. + + 2014-03-04 Richard Biener + + PR tree-optimization/60382 + * tree-vect-loop.c (vect_is_simple_reduction_1): Do not consider + dead PHIs a reduction. + + 2014-02-25 Richard Biener + + Backport from mainline + 2014-02-21 Richard Biener + + PR tree-optimization/60276 + * tree-vectorizer.h (struct _stmt_vec_info): Add min_neg_dist field. + (STMT_VINFO_MIN_NEG_DIST): New macro. + * tree-vect-data-refs.c (vect_analyze_data_ref_dependence): Record + STMT_VINFO_MIN_NEG_DIST. + * tree-vect-stmts.c (vectorizable_load): Verify if assumptions + made for negative dependence distances still hold. + + 2014-02-25 Richard Biener + + Backport from mainline + 2014-02-21 Richard Biener + + PR middle-end/60291 + * tree-ssa-live.c (mark_all_vars_used_1): Do not walk + DECL_INITIAL for globals not in the current function context. + + 2014-02-20 Richard Biener + + PR middle-end/60221 + * tree-eh.c (execute_cleanup_eh_1): Also cleanup empty EH + regions at -O0. + + 2014-02-14 Richard Biener + + PR tree-optimization/60183 + * tree-ssa-phiprop.c (propagate_with_phi): Avoid speculating + loads. + (tree_ssa_phiprop): Calculate and free post-dominators. + + 2014-02-25 Kyrylo Tkachov + + PR target/55426 + * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Allow 128 to 64-bit + conversions. + + 2014-02-24 John David Anglin + + * config/pa/pa.c (pa_output_move_double): Don't valididate when + adjusting offsetable addresses. + + 2014-02-23 David Holsgrove + + * config/microblaze/microblaze.md: Correct ashrsi_reg / lshrsi_reg names + + 2014-02-23 Edgar E. Iglesias + + * config/microblaze/microblaze.h: Remove SECONDARY_MEMORY_NEEDED + definition. + + 2014-02-23 David Holsgrove + + * /config/microblaze/microblaze.c: Add microblaze_asm_output_mi_thunk + and define TARGET_ASM_OUTPUT_MI_THUNK and + TARGET_ASM_CAN_OUTPUT_MI_THUNK. + + 2014-02-23 David Holsgrove + + * config/microblaze/predicates.md: Add cmp_op predicate. + * config/microblaze/microblaze.md: Add branch_compare instruction + which uses cmp_op predicate and emits cmp insn before branch. + * config/microblaze/microblaze.c (microblaze_emit_compare): Rename + to microblaze_expand_conditional_branch and consolidate logic. + (microblaze_expand_conditional_branch): emit branch_compare + insn instead of handling cmp op separate from branch insn. + + 2014-02-21 Martin Jambor + + PR ipa/55260 + * ipa-cp.c (cgraph_edge_brings_all_agg_vals_for_node): Uce correct + info when checking whether lattices are bottom. + + 2014-02-21 Jakub Jelinek + + * config/i386/i386.c (ix86_expand_vec_perm): Use V8SImode + mode for mask of V8SFmode permutation. + + 2014-02-20 Richard Henderson + + PR c++/60272 + * builtins.c (expand_builtin_atomic_compare_exchange): Conditionalize + on failure the store back into EXPECT. Always make a new pseudo for + OLDVAL. + + 2014-02-20 Jakub Jelinek + + PR target/57896 + * config/i386/i386.c (expand_vec_perm_interleave2): Don't call + gen_reg_rtx if d->testing_p. + (expand_vec_perm_pshufb2, expand_vec_perm_even_odd_1, + expand_vec_perm_broadcast_1): Return early if d->testing_p and + we will certainly return true. + + 2014-02-20 Richard Biener + + * tree-cfg.c (replace_uses_by): Mark altered BBs before + doing the substitution. + + 2014-02-19 H.J. Lu + + Backport from mainline + 2014-02-19 H.J. Lu + + PR target/60207 + * config/i386/i386.c (construct_container): Remove TFmode check + for X86_64_INTEGER_CLASS. + + 2014-02-19 Uros Bizjak + + Backport from mainline + 2014-02-19 Uros Bizjak + + PR target/59794 + * config/i386/i386.c (type_natural_mode): Warn for ABI changes + only when -Wpsabi is enabled. + + 2014-02-19 Terry Guo + + Backport from mainline + 2014-02-08 Terry Guo + + * doc/invoke.texi: Document ARM -march=armv7e-m. + + 2014-02-18 Kai Tietz + + Backport from mainline + 2014-02-18 Kai Tietz + + PR target/60193 + * config/i386/i386.c (ix86_expand_prologue): Use + rax register as displacement for restoring %r10, %rax. + Additional fix wrong offset for restoring both-registers. + + 2014-02-18 Eric Botcazou + + * ipa-prop.c (compute_complex_ancestor_jump_func): Replace overzealous + assertion with conditional return. + + 2014-02-18 Jakub Jelinek + Uros Bizjak + + PR driver/60233 + * config/i386/driver-i386.c (host_detect_local_cpu): If + YMM state is not saved by the OS, also clear has_f16c. Move + CPUID 0x80000001 handling before YMM state saving checking. + + 2014-02-14 Roland McGrath + + * configure.ac (HAVE_AS_IX86_UD2): New test for 'ud2' mnemonic. + * configure: Regenerated. + * config.in: Regenerated. + * config/i386/i386.md (trap) [HAVE_AS_IX86_UD2]: Use the mnemonic + instead of ASM_SHORT. + + 2014-02-13 Uros Bizjak + + Backport from mainline + 2014-02-13 Uros Bizjak + + * config/i386/sse.md (xop_vmfrcz2): Generate const0 in + operands[2], not operands[3]. + + 2014-02-13 Dominik Vogt + + * config/s390/s390.c (s390_asm_output_function_label): Fix crash + caused by bad second argument to warning_at() with -mhotpatch and + nested functions (e.g. with gfortran). + + 2014-02-12 H.J. Lu + + Backport from mainline + 2014-02-12 H.J. Lu + Uros Bizjak + + PR target/60151 + * configure.ac (HAVE_AS_GOTOFF_IN_DATA): Pass --32 to GNU assembler. + + 2014-02-12 Eric Botcazou + + PR rtl-optimization/60116 + * combine.c (try_combine): Also remove dangling REG_DEAD notes on the + other_insn once the combination has been validated. + + 2014-02-10 Nagaraju Mekala + + * config/microblaze/microblaze.md: Add movsi4_rev insn pattern. + * config/microblaze/predicates.md: Add reg_or_mem_operand predicate. + + 2014-02-10 Nagaraju Mekala + + * config/microblaze/microblaze.c: Extend mcpu version format + + 2014-02-10 David Holsgrove + + * config/microblaze/microblaze.h: Define SIZE_TYPE and PTRDIFF_TYPE. + + 2014-02-10 Richard Biener + + Backport from mainline + 2014-01-30 Richard Biener + + PR tree-optimization/59903 + * tree-vect-loop.c (vect_transform_loop): Guard multiple-types + check properly. + + 2014-02-10 Richard Biener + + PR tree-optimization/60115 + * tree-eh.c (tree_could_trap_p): Unify TARGET_MEM_REF and + MEM_REF handling. Properly verify that the accesses are not + out of the objects bound. + + 2014-02-05 James Greenhalgh + + Backport from mainline. + 2014-02-05 James Greenhalgh + + PR target/59718 + * doc/invoke.texi (-march): Clarify documentation for ARM. + (-mtune): Likewise. + (-mcpu): Likewise. + + 2014-02-04 John David Anglin + + PR target/59777 + * config/pa/pa.c (legitimize_tls_address): Return original address + if not passed a SYMBOL_REF rtx. + (hppa_legitimize_address): Call legitimize_tls_address for all TLS + addresses. + (pa_emit_move_sequence): Simplify TLS source operands. + (pa_legitimate_constant_p): Reject all TLS constants. + * config/pa/pa.h (PA_SYMBOL_REF_TLS_P): Correct comment. + (CONSTANT_ADDRESS_P): Reject TLS CONST addresses. + + 2014-02-04 Uros Bizjak + + Backport from mainline + 2014-02-02 Uros Bizjak + + PR target/60017 + * config/i386/i386.c (classify_argument): Fix handling of bit_offset + when calculating size of integer atomic types. + + 2014-02-02 Uros Bizjak + + Backport from mainline + 2014-01-30 Jakub Jelinek + + * config/i386/f16cintrin.h (_cvtsh_ss): Avoid -Wnarrowing warning. + + 2014-01-31 Richard Henderson + + PR middle-end/60004 + * tree-eh.c (lower_try_finally_switch): Delay lowering finally block + until after else_eh is processed. + + 2014-01-30 David Holsgrove + + Backport from mainline + * config/microblaze/microblaze.md(cstoresf4, cbranchsf4): Replace + comparison_operator with ordered_comparison_operator. + + 2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/sync.md (atomic_fetch_sub): Fix negation and + avoid clobbering a live register. + + 2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/tilegx-c.c (tilegx_cpu_cpp_builtins): + Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2}. + * config/tilegx/tilepro-c.c (tilepro_cpu_cpp_builtins): + Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2,4,8}. + + 2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/tilegx.c (tilegx_gen_bundles): Delete barrier + insns before bundling. + * config/tilegx/tilegx.md (tile_network_barrier): Update comment. + + 2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/tilegx.c (tilegx_expand_builtin): Set + PREFETCH_SCHEDULE_BARRIER_P to true for prefetches. + * config/tilepro/tilepro.c (tilepro_expand_builtin): Ditto. + + 2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilepro/tilepro.md (ctzdi2): Use register_operand + predicate. + (clzdi2): Ditto. + (ffsdi2): Ditto. + + 2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/tilegx.c (tilegx_expand_to_rtl_hook): New. + (TARGET_EXPAND_TO_RTL_HOOK): Define. + + 2014-01-24 H.J. Lu + + Backport from mainline + 2014-01-23 H.J. Lu + + PR target/59929 + * config/i386/i386.md (pushsf splitter): Get stack adjustment + from push operand if code of push isn't PRE_DEC. + + 2014-01-23 David Holsgrove + + Backport from mainline. + * config/microblaze/microblaze.md: Add trap insn and attribute + + 2014-01-23 Marek Polacek + + Backport from mainline + 2013-10-21 Marek Polacek + + PR middle-end/58809 + * fold-const.c (fold_range_test): Return 0 if the type is not + an integral type. + + 2014-01-22 David Holsgrove + + * config/microblaze/microblaze.md: Correct bswaphi2 insn. + + 2014-01-22 Uros Bizjak + + Backport from mainline + 2014-01-20 Uros Bizjak + + * config/i386/i386.c (ix86_avoid_lea_for_addr): Return false + for SImode_address_operand operands, having only a REG argument. + + 2014-01-20 Jakub Jelinek + + PR target/59880 + * config/i386/i386.c (ix86_avoid_lea_for_addr): Return false + if operands[1] is a REG or ZERO_EXTEND of a REG. + + 2014-01-18 Uros Bizjak + H.J. Lu + + PR target/59379 + * config/i386/i386.md (*lea): Zero-extend return register + to DImode for zero-extended addresses. + + 2014-01-21 Andrew Pinski + Steve Ellcey + + PR target/59462 + * config/mips/mips.c (mips_print_operand): Check operand mode instead + of operator mode. + + 2014-01-21 Andrey Belevantsev + + Backport from mainline + 2013-12-23 Andrey Belevantsev + + PR rtl-optimization/57422 + * sel-sched.c (mark_unavailable_hard_regs): Fix typo when calling + add_to_hard_reg_set. + + 2014-01-20 Jakub Jelinek + + PR middle-end/59860 + * tree.h (fold_builtin_strcat): New prototype. + * builtins.c (fold_builtin_strcat): No longer static. Add len + argument, if non-NULL, don't call c_strlen. Optimize + directly into __builtin_memcpy instead of __builtin_strcpy. + (fold_builtin_2): Adjust fold_builtin_strcat caller. + * gimple-fold.c (gimple_fold_builtin): Handle BUILT_IN_STRCAT. + + 2014-01-20 Richard Biener + + PR middle-end/59860 + * builtins.c (fold_builtin_strcat): Remove case better handled + by tree-ssa-strlen.c. + + 2014-01-19 John David Anglin + + * config/pa/pa.c (pa_attr_length_millicode_call): Correct length of + long non-pic millicode calls. + + 2014-01-17 John David Anglin + + * config/pa/pa.c (pa_attr_length_indirect_call): Don't output a short + call to $$dyncall when TARGET_LONG_CALLS is true. + + 2014-01-17 H.J. Lu + + Backport from mainline + 2014-01-14 H.J. Lu + + PR target/59794 + * config/i386/i386.c (type_natural_mode): Add a bool parameter + to indicate if type is used for function return value. Warn + ABI change if the vector mode isn't available for function + return value. + (ix86_function_arg_advance): Pass false to type_natural_mode. + (ix86_function_arg): Likewise. + (ix86_gimplify_va_arg): Likewise. + (function_arg_32): Don't warn ABI change. + (ix86_function_value): Pass true to type_natural_mode. + (ix86_return_in_memory): Likewise. + (ix86_struct_value_rtx): Removed. + (TARGET_STRUCT_VALUE_RTX): Likewise. + + 2014-01-17 Charles Baylis + + Backport from mainline + 2013-12-19 Charles Baylis + + PR target/59142 + * config/arm/arm-ldmstm.ml: Use low_register_operand for Thumb + patterns. + * config/arm/ldmstm.md: Regenerate. + + 2013-12-19 Charles Baylis + + PR target/59142 + * config/arm/predicates.md (arm_hard_general_register_operand): + New predicate. + (arm_hard_register_operand): Remove. + * config/arm/arm-ldmstm.ml: Use arm_hard_general_register_operand + for all patterns. + * config/arm/ldmstm.md: Regenerate. + + 2013-12-19 Charles Baylis + + PR target/59142 + * config/arm/predicates.md (vfp_hard_register_operand): New predicate. + * config/arm/arm.md (vfp_pop_multiple_with_writeback): Use + vfp_hard_register_operand. + + 2014-01-17 Kugan Vivekanandarajah + + Backport from mainline + 2014-01-15 Matthew Gretton-Dann + Kugan Vivekanandarajah + + PR target/59695 + * config/aarch64/aarch64.c (aarch64_build_constant): Fix incorrect + truncation. + + 2014-01-17 Terry Guo + + PR target/59826 + * config/arm/arm.md (prefetch): Set insn type attribute to load1. + + 2014-01-16 Jakub Jelinek + + PR target/59839 + * config/i386/i386.c (ix86_expand_builtin): If target doesn't + satisfy operand 0 predicate for gathers, use a new pseudo as + subtarget. + + 2014-01-16 Richard Henderson + + PR debug/54694 + * reginfo.c (global_regs_decl): Globalize. + * rtl.h (global_regs_decl): Declare. + * ira.c (do_reload): Diagnose frame_pointer_needed and it + reserved via global_regs. + + 2014-01-16 Peter Bergner + + Backport from mainline + 2014-01-15 Uros Bizjak + + * config/i386/i386.c (ix86_hard_regno_mode_ok): Use + VALID_AVX256_REG_OR_OI_MODE. + + 2013-09-05 Peter Bergner + + PR target/58139 + * reginfo.c (choose_hard_reg_mode): Scan through all mode classes + looking for widest mode. + + 2014-01-16 Marek Polacek + + Backported from mainline + 2014-01-16 Marek Polacek + + PR middle-end/59827 + * gimple-low.c (gimple_check_call_args): Don't use DECL_ARG_TYPE if + it is error_mark_node. + + 2014-01-15 Andreas Krebbel + + PR target/59803 + * config/s390/s390.c (s390_preferred_reload_class): Don't return + ADDR_REGS for invalid symrefs in non-PIC code. + + 2014-01-14 Uros Bizjak + + Revert: + 2014-01-08 Uros Bizjak + + * config/i386/i386.c (ix86_data_alignment): Calculate max_align + from prefetch_block tune setting. + + 2014-01-13 Jakub Jelinek + + Backported from mainline + 2014-01-10 Jakub Jelinek + + PR tree-optimization/59745 + * tree-predcom.c (tree_predictive_commoning_loop): Call + free_affine_expand_cache if giving up because components is NULL. + + 2014-01-10 Yufeng Zhang + + * config/arm/arm.c (arm_expand_neon_args): Call expand_expr + with EXPAND_MEMORY for NEON_ARG_MEMORY; check if the returned + rtx is const0_rtx or not. + + 2014-01-10 Andreas Krebbel + + * config/s390/s390.c (s390_expand_tbegin): Remove jump over CC + extraction in good case. + + 2014-01-10 Huacai Chen + + * config/mips/driver-native.c (host_detect_local_cpu): Handle new + kernel strings for Loongson-2E/2F/3A. + + 2014-01-10 Richard Biener + + PR tree-optimization/59715 + * tree-flow.h (split_critical_edges): Declare. + * tree-cfg.c (split_critical_edges): Export. + * tree-ssa-sink.c (execute_sink_code): Split critical edges. + + 2014-01-09 Richard Sandiford + + * config/mips/mips.h (ISA_HAS_WSBH): Define. + * config/mips/mips.md (UNSPEC_WSBH, UNSPEC_DSBH, UNSPEC_DSHD): New + constants. + (bswaphi2, bswapsi2, bswapdi2, wsbh, dsbh, dshd): New patterns. + + 2014-01-09 Richard Sandiford + + PR rtl-optimization/59137 + * reorg.c (steal_delay_list_from_target): Call update_block for + elided insns. + (steal_delay_list_from_fallthrough, relax_delay_slots): Likewise. + + 2014-01-09 Richard Sandiford + + Revert: + 2012-10-07 Richard Sandiford + + * config/mips/mips.c (mips_truncated_op_cost): New function. + (mips_rtx_costs): Adjust test for BADDU. + * config/mips/mips.md (*baddu_di): Push truncates to operands. + + 2012-10-02 Richard Sandiford + + * config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into... + (*baddu_si): ...this new pattern. + + 2014-01-09 Richard Biener + + Backport from mainline + 2013-11-18 Richard Biener + + PR tree-optimization/59125 + PR tree-optimization/54570 + * tree-ssa-sccvn.c (copy_reference_ops_from_ref): When inlining + is not complete do not treat component-references with offset zero + but different fields as equal. + * tree-object-size.c: Include tree-phinodes.h and ssa-iterators.h. + (compute_object_sizes): Apply TLC. Propagate the constant + results into all uses and fold their stmts. + * passes.def (pass_all_optimizations): Move pass_object_sizes + after the first pass_forwprop and before pass_fre. + + 2013-12-03 Jakub Jelinek + + PR tree-optimization/59362 + * tree-object-size.c (object_sizes): Change into array of + vec. + (compute_builtin_object_size): Check computed bitmap for + non-NULL instead of object_sizes. Call safe_grow on object_sizes + vector if new SSA_NAMEs appeared. + (init_object_sizes): Check computed bitmap for non-NULL. + Call safe_grow on object_sizes elements instead of initializing + it with XNEWVEC. + (fini_object_sizes): Call release on object_sizes elements, don't + set it to NULL. + + 2014-01-09 Richard Earnshaw + + PR rtl-optimization/54300 + * regcprop.c (copyprop_hardreg_forward_1): Ensure any unused + outputs in a single-set are killed from the value chains. + + 2014-01-09 Jakub Jelinek + + PR rtl-optimization/59724 + * ifcvt.c (cond_exec_process_if_block): Don't call + flow_find_head_matching_sequence with 0 longest_match. + * cfgcleanup.c (flow_find_head_matching_sequence): Count even + non-active insns if !stop_after. + (try_head_merge_bb): Revert 2014-01-07 changes. + + 2014-01-09 Hans-Peter Nilsson + + Backport from mainline + 2013-12-23 Hans-Peter Nilsson + + PR middle-end/59584 + * config/cris/predicates.md (cris_nonsp_register_operand): + New define_predicate. + * config/cris/cris.md: Replace register_operand with + cris_nonsp_register_operand for destinations in all + define_splits where a register is set more than once. + + 2014-01-08 H.J. Lu + + Backport from mainline + 2013-12-25 H.J. Lu + + PR target/59587 + * config/i386/i386.c (struct ptt): Add a field for processor name. + (processor_target_table): Sync with processor_type. Add + processor names. + (cpu_names): Removed. + (ix86_option_override_internal): Default x_ix86_tune_string + to processor_target_table[TARGET_CPU_DEFAULT].name. + (ix86_function_specific_print): Assert arch and tune < + PROCESSOR_max. Use processor_target_table to print arch and + tune names. + * config/i386/i386.h (TARGET_CPU_DEFAULT): Default to + PROCESSOR_GENERIC32. + (target_cpu_default): Removed. + (processor_type): Reordered. + + 2014-01-08 Uros Bizjak + + Backport from mainline + 2014-01-05 Uros Bizjak + + * config/i386/i386.c (ix86_data_alignment): Calculate max_align + from prefetch_block tune setting. + (nocona_cost): Correct size of prefetch block to 64. + + 2014-01-08 Martin Jambor + + PR ipa/59610 + * ipa-prop.c (ipa_compute_jump_functions): Bail out if not optimizing. + (parm_preserved_before_stmt_p): Assume modification present when not + optimizing. + + 2014-01-07 John David Anglin + + PR target/59652 + * config/pa/pa.c (pa_legitimate_address_p): Return false before reload + for 14-bit register offsets when INT14_OK_STRICT is false. + + 2014-01-07 Roland Stigge + Michael Meissner + + PR 57386/target + * config/rs6000/rs6000.c (rs6000_legitimate_offset_address_p): + Only check TFmode for SPE constants. Don't check TImode or TDmode. + + 2014-01-07 Jakub Jelinek + + PR rtl-optimization/58668 + * cfgcleanup.c (flow_find_cross_jump): Don't count + any jumps if dir_p is NULL. Remove p1 variable and make USE/CLOBBER + check consistent with other places. + (flow_find_head_matching_sequence): Don't count USE or CLOBBER insns. + (try_head_merge_bb): Adjust for the flow_find_head_matching_sequence + counting change. + * ifcvt.c (count_bb_insns): Don't count USE or CLOBBER insns. + + 2014-01-07 Mike Stump + Jakub Jelinek + + PR pch/59436 + * tree.h (struct tree_optimization_option): Change optabs + type from unsigned char * to void *. + * optabs.c (init_tree_optimization_optabs): Adjust + TREE_OPTIMIZATION_OPTABS initialization. + + 2014-01-07 Jakub Jelinek + + Backported from mainline + 2013-12-16 Jakub Jelinek + + PR middle-end/58956 + PR middle-end/59470 + * gimple.h (walk_stmt_load_store_addr_fn): New typedef. + (walk_stmt_load_store_addr_ops, walk_stmt_load_store_ops): Use it + for callback params. + * gimple.c (walk_stmt_load_store_ops): Likewise. + (walk_stmt_load_store_addr_ops): Likewise. Adjust all callback + calls to supply the gimple operand containing the base tree + as an extra argument. + * tree-ssa-ter.c (find_ssaname, find_ssaname_in_store): New helper + functions. + (find_replaceable_in_bb): For calls or GIMPLE_ASM, only set + same_root_var if USE is used somewhere in the stores of the stmt. + * ipa-prop.c (visit_ref_for_mod_analysis): Remove name of the stmt + argument and ATTRIBUTE_UNUSED, add another unnamed tree argument. + * ipa-pure-const.c (check_load, check_store, check_ipa_load, + check_ipa_store): Likewise. + * gimple.c (gimple_ior_addresses_taken_1): Likewise. + * ipa-split.c (test_nonssa_use, mark_nonssa_use): Likewise. + (verify_non_ssa_vars, visit_bb): Adjust their callers. + * cfgexpand.c (add_scope_conflicts_1): Use + walk_stmt_load_store_addr_fn type for visit variable. + (visit_op, visit_conflict): Remove name of the stmt + argument and ATTRIBUTE_UNUSED, add another unnamed tree argument. + * tree-sra.c (asm_visit_addr): Likewise. Remove name of the data + argument and ATTRIBUTE_UNUSED. + * cgraphbuild.c (mark_address, mark_load, mark_store): Add another + unnamed tree argument. + + 2014-01-03 Andreas Schwab + + * config/m68k/m68k.c (handle_move_double): Handle pushes with + overlapping registers also for registers other than the stack + pointer. + + 2014-01-03 Jakub Jelinek + + PR target/59625 + * config/i386/i386.c (ix86_avoid_jump_mispredicts): Don't consider + asm goto as jump. + + 2014-01-01 Jakub Jelinek + + PR rtl-optimization/59647 + * cse.c (cse_process_notes_1): Don't substitute negative VOIDmode + new_rtx into UNSIGNED_FLOAT rtxes. + + 2013-12-28 Eric Botcazou + + * doc/invoke.texi (output file options): Document -fada-spec-parent. + + 2013-12-26 Uros Bizjak + + * config/i386/driver-i386.c (decode_caches_intel): Add missing entries. + + 2013-12-20 Jakub Jelinek + + PR c++/59255 + Backported from mainline + 2013-08-19 Dehao Chen + + * value-prof.c (gimple_ic): Fix the bug of adding EH edge. + + 2013-12-19 James Greenhalgh + + Backport from Mainline. + 2013-05-01 James Greenhalgh + + * config/aarch64/aarch64-simd-builtins.def (cmhs): Rename to... + (cmgeu): ...This. + (cmhi): Rename to... + (cmgtu): ...This. + * config/aarch64/aarch64-simd.md + (simd_mode): Add SF. + (aarch64_vcond_internal): Use new names for unsigned comparison insns. + (aarch64_cm): Rewrite to not use UNSPECs. + * config/aarch64/aarch64.md (*cstore_neg): Rename to... + (cstore_neg): ...This. + * config/aarch64/iterators.md + (VALLF): new. + (unspec): Remove UNSPEC_CM. + (COMPARISONS): New. + (UCOMPARISONS): Likewise. + (optab): Add missing comparisons. + (n_optab): New. + (cmp_1): Likewise. + (cmp_2): Likewise. + (CMP): Likewise. + (cmp): Remove. + (VCMP_S): Likewise. + (VCMP_U): Likewise. + (V_cmp_result): Add DF, SF modes. + (v_cmp_result): Likewise. + (v): Likewise. + (vmtype): Likewise. + * config/aarch64/predicates.md (aarch64_reg_or_fp_zero): New. + + Partial Backport from mainline. + 2013-05-01 James Greenhalgh + + * config/aarch64/arm_neon.h + (vc_<8,16,32,64>): Remap + to builtins or C as appropriate. + + 2013-12-19 Dominik Vogt + Andreas Krebbel + + Backport from mainline + 2013-12-19 Dominik Vogt + * config/s390/s390.c (s390_hotpatch_trampoline_halfwords_default): New + constant + (s390_hotpatch_trampoline_halfwords_max): New constant + (s390_hotpatch_trampoline_halfwords): New static variable + (get_hotpatch_attribute): New function + (s390_handle_hotpatch_attribute): New function + (s390_attribute_table): New target specific attribute table to implement + the hotpatch attribute + (s390_option_override): Parse hotpatch options + (s390_function_num_hotpatch_trampoline_halfwords): New function + (s390_can_inline_p): Implement target hook to + suppress hotpatching for explicitly inlined functions + (s390_asm_output_function_label): Generate hotpatch prologue + (TARGET_ATTRIBUTE_TABLE): Define to implement target attribute table + (TARGET_CAN_INLINE_P): Define to implement target hook + * config/s390/s390.opt (mhotpatch): New options -mhotpatch, -mhotpatch= + * config/s390/s390-protos.h (s390_asm_output_function_label): Add + prototype + * config/s390/s390.h (ASM_OUTPUT_FUNCTION_LABEL): Target specific + function label generation for hotpatching + (FUNCTION_BOUNDARY): Align functions to eight bytes + * doc/extend.texi: Document hotpatch attribute + * doc/invoke.texi: Document -mhotpatch option + + 2013-12-18 Eric Botcazou + + * config/arm/arm.c (arm_expand_epilogue_apcs_frame): Fix thinko. + + 2013-12-12 Vladimir Makarov + + PR middle-end/59470 + * lra-coalesce.c (lra_coalesce): Invalidate inheritance pseudo + values if necessary. + + 2013-12-12 Jakub Jelinek + + PR libgomp/59467 + * gimplify.c (omp_check_private): Add copyprivate argument, if it + is true, don't check omp_privatize_by_reference. + (gimplify_scan_omp_clauses): For OMP_CLAUSE_COPYPRIVATE verify + decl is private in outer context. Adjust omp_check_private caller. + + 2013-12-10 Eric Botcazou + + PR rtl-optimization/58295 + * simplify-rtx.c (simplify_truncation): Restrict the distribution for + WORD_REGISTER_OPERATIONS targets. + + 2013-12-10 Kai Tietz + + PR target/56807 + * config/i386/i386.c (ix86_expand_prologue): Address saved + registers stack-relative, not via frame-pointer. + + 2013-12-09 Alan Modra + + Apply from mainline + 2013-12-05 Alan Modra + * configure.ac (BUILD_CXXFLAGS) Don't use ALL_CXXFLAGS for + build != host. + : Clear GMPINC. Don't bother + saving CFLAGS. + * configure: Regenerate. + + 2013-12-08 Uros Bizjak + + Backport from mainline + 2013-12-06 Uros Bizjak + + PR target/59405 + * config/i386/i386.c (type_natural_mode): Properly handle + size 8 for !TARGET_64BIT. + + 2013-12-07 Ralf Corsépius + + * config.gcc (microblaze*-*-rtems*): Add TARGET_BIG_ENDIAN_DEFAULT. + + 2013-12-06 Jakub Jelinek + + PR tree-optimization/59388 + * tree-ssa-reassoc.c (update_range_test): If op == range->exp, + gimplify tem after stmt rather than before it. + + 2013-12-06 Oleg Endo + + Backport from mainline + 2013-11-26 Oleg Endo + + PR target/58314 + PR target/50751 + * config/sh/sh.c (max_mov_insn_displacement, disp_addr_displacement): + Prefix function names with 'sh_'. Make them non-static. + * config/sh/sh-protos.h (sh_disp_addr_displacement, + sh_max_mov_insn_displacement): Add declarations. + * config/sh/constraints.md (Q): Reject QImode. + (Sdd): Use match_code "mem". + (Snd): Fix erroneous matching of non-memory operands. + * config/sh/predicates.md (short_displacement_mem_operand): New + predicate. + (general_movsrc_operand): Disallow PC relative QImode loads. + * config/sh/sh.md (*mov_reg_reg): Remove it. + (*movqi, *movhi): Merge both insns into... + (*mov): ... this new insn. Replace generic 'm' constraints with + 'Snd' and 'Sdd' constraints. Calculate insn length dynamically based + on the operand types. + + 2013-12-06 Richard Biener + + Backport from mainline + 2013-11-29 Richard Biener + + PR tree-optimization/59334 + * tree-ssa-dce.c (eliminate_unnecessary_stmts): Fix bug + in previous commit. + + 2013-11-28 Richard Biener + + PR tree-optimization/59330 + * tree-ssa-dce.c (eliminate_unnecessary_stmts): Simplify + and fix delayed marking of free calls not necessary. + + 2013-12-06 Richard Biener + + Backport from mainline + 2013-11-27 Richard Biener + + PR tree-optimization/59288 + * tree-vect-loop.c (get_initial_def_for_induction): Do not + re-analyze the PHI but use STMT_VINFO_LOOP_PHI_EVOLUTION_PART. + + 2013-11-19 Richard Biener + + PR tree-optimization/59164 + * tree-vect-loop.c (vect_analyze_loop_operations): Adjust + check whether we can create an epilogue loop to reflect the + cases where we create one. + + 2013-09-05 Richard Biener + + PR tree-optimization/58137 + * tree-vect-stmts.c (get_vectype_for_scalar_type_and_size): + Do not create vectors of pointers. + * tree-vect-loop.c (get_initial_def_for_induction): Use proper + types for the components of the vector initializer. + * tree-cfg.c (verify_gimple_assign_binary): Remove special-casing + allowing pointer vectors with PLUS_EXPR/MINUS_EXPR. + + 2013-12-06 Oleg Endo + + PR target/51244 + PR target/59343 + * config/sh/sh.md (*cbranch_t): Check that there are no labels between + the s1 insn and the testing insn. Remove REG_DEAD note from s1 insn. + + 2013-12-05 Richard Biener + + Backport from mainline + 2013-11-19 Richard Biener + + PR middle-end/58956 + * tree-ssa-ter.c (find_replaceable_in_bb): Avoid forwarding + loads into stmts that may clobber it. + + 2013-12-04 Jakub Jelinek + + PR rtl-optimization/58726 + * combine.c (force_to_mode): Fix comment typo. Don't destructively + modify x for ROTATE, ROTATERT and IF_THEN_ELSE. + + 2013-12-04 Jakub Jelinek + Uros Bizjak + + PR target/59163 + * config/i386/i386.c (ix86_legitimate_combined_insn): If for + !TARGET_AVX there is misaligned MEM operand with vector mode + and get_attr_ssememalign is 0, return false. + (ix86_expand_special_args_builtin): Add get_pointer_alignment + computed alignment and for non-temporal loads/stores also + at least GET_MODE_ALIGNMENT as MEM_ALIGN. + * config/i386/sse.md + (_loadu, + _storeu, + _loaddqu, + _storedqu, _lddqu, + sse_vmrcpv4sf2, sse_vmrsqrtv4sf2, sse2_cvtdq2pd, sse_movhlps, + sse_movlhps, sse_storehps, sse_loadhps, sse_loadlps, + *vec_interleave_highv2df, *vec_interleave_lowv2df, + *vec_extractv2df_1_sse, sse2_loadhpd, sse2_loadlpd, sse2_movsd, + sse4_1_v8qiv8hi2, sse4_1_v4qiv4si2, + sse4_1_v4hiv4si2, sse4_1_v2qiv2di2, + sse4_1_v2hiv2di2, sse4_1_v2siv2di2, sse4_2_pcmpestr, + *sse4_2_pcmpestr_unaligned, sse4_2_pcmpestri, sse4_2_pcmpestrm, + sse4_2_pcmpestr_cconly, sse4_2_pcmpistr, *sse4_2_pcmpistr_unaligned, + sse4_2_pcmpistri, sse4_2_pcmpistrm, sse4_2_pcmpistr_cconly): Add + ssememalign attribute. + * config/i386/i386.md (ssememalign): New define_attr. + + 2013-12-03 Jakub Jelinek + + PR middle-end/59011 + * gimplify.c (nonlocal_vla_vars): New variable. + (gimplify_var_or_parm_decl): Put VAR_DECLs for VLAs into + nonlocal_vla_vars chain. + (gimplify_body): Call declare_vars on nonlocal_vla_vars chain + if outer_bind has DECL_INITIAL (current_function_decl) block. + + PR target/58864 + * optabs.c (emit_conditional_move): Save and restore + pending_stack_adjust and stack_pointer_delta if cmove can't be used. + + 2013-12-02 Jakub Jelinek + + PR tree-optimization/59358 + * tree-vrp.c (union_ranges): To check for the partially + overlapping ranges or adjacent ranges, also compare *vr0max + with vr1max. + + 2013-12-02 Richard Biener + + PR tree-optimization/59139 + * tree-ssa-loop-niter.c (chain_of_csts_start): Properly match + code in get_val_for. + (get_val_for): Use gcc_checking_asserts. + + 2013-11-27 Tom de Vries + Marc Glisse + + PR middle-end/59037 + * fold-const.c (fold_indirect_ref_1): Don't create out-of-bounds + BIT_FIELD_REF. + * gimplify.c (gimple_fold_indirect_ref): Same. + + 2013-12-01 Eric Botcazou + + * config/i386/winnt.c (i386_pe_asm_named_section): Be prepared for an + identifier node. + + 2013-12-01 Bernd Edlinger + + * expr.c (emit_group_store): Fix off-by-one BITFIELD_END argument. + + 2013-11-28 Kyrylo Tkachov + + Backport from mainline + 2013-11-28 Kyrylo Tkachov + + * config/arm/iterators.md (vrint_conds): New int attribute. + * config/arm/vfp.md (2): Set conds attribute. + (smax3): Likewise. + (smin3): Likewise. + + 2013-11-28 Uros Bizjak + + Backport from mainline + 2013-11-27 Uros Bizjak + Ganesh Gopalasubramanian + + PR target/56788 + * gcc.target/i386/xop-frczX.c: New test. + + 2013-11-28 Terry Guo + + Backport mainline r205391 + 2013-11-26 Terry Guo + + * config/arm/arm.c (require_pic_register): Handle high pic base + register for thumb-1. + (arm_load_pic_register): Also initialize high pic base register. + * doc/invoke.texi: Update documentation for option -mpic-register. + + 2013-11-27 Jakub Jelinek + + Backported from mainline + 2013-11-26 Jakub Jelinek + + PR tree-optimization/59014 + * tree-vrp.c (register_edge_assert_for_1): Don't look + through conversions from non-integral types or through + narrowing conversions. + + 2013-11-27 Eric Botcazou + + PR middle-end/59138 + * expr.c (emit_group_store): Don't write past the end of the structure. + (store_bit_field): Fix formatting. + + 2013-11-24 Sebastian Huber + + Backport from mainline + 2013-09-17 Sebastian Huber + + * config/sparc/t-rtems: Add leon3 multilibs. + + 2013-11-24 Sebastian Huber + + Backport from mainline + 2013-08-09 Eric Botcazou + + * configure.ac: Add GAS check for LEON instructions on SPARC. + * configure: Regenerate. + * config.in: Likewise. + * config.gcc (with_cpu): Remove sparc-leon*-* and deal with LEON in the + sparc*-*-* block. + * config/sparc/sparc.opt (LEON, LEON3): New masks. + * config/sparc/sparc.h (ASM_CPU32_DEFAULT_SPEC): Set to AS_LEON_FLAG + for LEON or LEON3. + (ASM_CPU_SPEC): Pass AS_LEON_FLAG if -mcpu=leon or -mcpu=leon3. + (AS_LEON_FLAG): New macro. + * config/sparc/sparc.c (sparc_option_override): Set MASK_LEON for leon + and MASK_LEON3 for leon3 and unset them if HAVE_AS_LEON is not defined. + Deal with LEON and LEON3 for the memory model. + * config/sparc/sync.md (atomic_compare_and_swap): Enable if LEON3 + (atomic_compare_and_swap_1): Likewise. + (*atomic_compare_and_swap_1): Likewise. + + 2013-11-24 Sebastian Huber + + Backport from mainline + 2013-07-23 Eric Botcazou + + * doc/invoke.texi (SPARC Options): Document new leon3 processor value. + + 2013-11-24 Sebastian Huber + + Backport from mainline + 2013-07-22 Eric Botcazou + + * config.gcc (sparc*-*-*): Accept leon3 processor. + (sparc-leon*-*): Merge with sparc*-*-* and add leon3 support. + * doc/invoke.texi (SPARC Options): Adjust -mfix-ut699 entry. + * config/sparc/sparc-opts.h (enum processor_type): Add PROCESSOR_LEON3. + * config/sparc/sparc.opt (enum processor_type): Add leon3. + (mfix-ut699): Adjust comment. + * config/sparc/sparc.h (TARGET_CPU_leon3): New define. + (CPP_CPU32_DEFAULT_SPEC): Add leon3 support. + (CPP_CPU_SPEC): Likewise. + (ASM_CPU_SPEC): Likewise. + * config/sparc/sparc.c (leon3_cost): New constant. + (sparc_option_override): Add leon3 support. + (mem_ref): New function. + (sparc_gate_work_around_errata): Return true if -mfix-ut699 is enabled. + (sparc_do_work_around_errata): Look into the instruction in the delay + slot and adjust accordingly. Add fix for the data cache nullify issues + of the UT699. Change insertion position for the NOP. + * config/sparc/leon.md (leon_fpalu, leon_fpmds, write_buf): Delete. + (leon3_load): New reservation. + (leon_store): Bump latency to 2. + (grfpu): New automaton. + (grfpu_alu): New unit. + (grfpu_ds): Likewise. + (leon_fp_alu): Adjust. + (leon_fp_mult): Delete. + (leon_fp_div): Split into leon_fp_divs and leon_fp_divd. + (leon_fp_sqrt): Split into leon_fp_sqrts and leon_fp_sqrtd. + * config/sparc/sparc.md (cpu): Add leon3. + * config/sparc/sync.md (atomic_exchangesi): Disable if -mfix-ut699. + (swapsi): Likewise. + (atomic_test_and_set): Likewise. + (ldstub): Likewise. + + 2013-11-24 Sebastian Huber + + Backport from mainline + 2013-04-10 Steven Bosscher + + * config/sparc/sparc.c: Include tree-pass.h. + (TARGET_MACHINE_DEPENDENT_REORG): Do not redefine. + (sparc_reorg): Rename to sparc_do_work_around_errata. Move to + head of file. Change return type. Split off gate function. + (sparc_gate_work_around_errata): New function. + (pass_work_around_errata): New pass definition. + (insert_pass_work_around_errata) New pass insert definition to + insert pass_work_around_errata just after delayed-branch scheduling. + (sparc_option_override): Insert the pass. + * config/sparc/t-sparc (sparc.o): Add TREE_PASS_H dependence. + + 2013-11-24 Sebastian Huber + + Backport from mainline + 2013-05-28 Eric Botcazou + + * doc/invoke.texi (SPARC Options): Document -mfix-ut699. + * builtins.c (expand_builtin_mathfn) : Try to widen the + mode if the instruction isn't available in the original mode. + * config/sparc/sparc.opt (mfix-ut699): New option. + * config/sparc/sparc.md (muldf3_extend): Disable if -mfix-ut699. + (divdf3): Turn into expander. + (divdf3_nofix): New insn. + (divdf3_fix): Likewise. + (divsf3): Disable if -mfix-ut699. + (sqrtdf2): Turn into expander. + (sqrtdf2_nofix): New insn. + (sqrtdf2_fix): Likewise. + (sqrtsf2): Disable if -mfix-ut699. + + 2013-11-22 Eric Botcazou + + * print-rtl.c (print_rtx) : Output a space if no MEM_EXPR. + + 2013-11-21 Zhenqiang Chen + + PR bootstrap/57683 + Backport from mainline: r197467 and r198999. + 2013-04-03 Jeff Law + + * Makefile.in (lra-constraints.o): Depend on $(OPTABS_H). + (lra-eliminations.o): Likewise. + + 2013-05-16 Jeff Law + + * Makefile.in (tree-switch-conversion.o): Depend on $(OPTABS_H). + + 2013-11-20 Eric Botcazou + + PR target/59207 + * config/sparc/sparc.c (sparc_fold_builtin) : + Make sure neg2_ovf is set before being used. + + 2013-11-20 Andreas Krebbel + Dominik Vogt + + Backport from mainline + * config/s390/s390.c (s390_canonicalize_comparison): Don't fold + int comparisons with an out of range condition code. + (s390_optimize_nonescaping_tx): Skip empty BBs. + Generate the new tbegin RTX when removing the FPR clobbers (with + two SETs). + (s390_expand_tbegin): Fix the retry loop counter. Copy CC to the + result before doing the retry calculations. + (s390_init_builtins): Make tbegin "returns_twice" and tabort + "noreturn". + * config/s390/s390.md (UNSPECV_TBEGIN_TDB): New constant used for + the TDB setting part of an tbegin. + ("tbegin_1", "tbegin_nofloat_1"): Add a set for the TDB. + ("tx_assist"): Set unused argument to an immediate zero instead of + loading zero into a GPR and pass it as argument. + * config/s390/htmxlintrin.h (__TM_simple_begin, __TM_begin): + Remove inline and related attributes. + (__TM_nesting_depth, __TM_is_user_abort, __TM_is_named_user_abort) + (__TM_is_illegal, __TM_is_footprint_exceeded) + (__TM_is_nested_too_deep, __TM_is_conflict): Fix format value + check. + + 2013-11-19 Uros Bizjak + + Backport from mainline + 2013-11-18 Uros Bizjak + + * config/i386/i386.c (ix86_decompose_address): Use REG_P instead of + ix86_address_subreg_operand. Move subreg checks to + ix86_validate_address_register. Move address override check to + ix86_legitimate_address_p. + (ix86_validate_address_register): New function. + (ix86_legitimate_address_p): Call ix86_validate_address_register + to validate base and index registers. Add address override check + from ix86_decompose_address. + (ix86_decompose_address): Remove. + + Backport from mainline + 2013-11-17 Uros Bizjak + + PR target/59153 + * config/i386/i386.c (ix86_address_subreg_operand): Do not + reject non-integer subregs. + (ix86_decompose_address): Do not reject invalid CONST_INT RTXes. + Move check for invalid x32 constant addresses ... + (ix86_legitimate_address_p): ... here. + + 2013-11-19 Richard Biener + + Backport from mainline + 2013-11-07 Richard Biener + + * tree-dfa.c (get_ref_base_and_extent): Fix casting. + + 2013-11-19 Richard Biener + + PR tree-optimization/57517 + * tree-predcom.c (combinable_refs_p): Verify the combination + is always executed when the refs are. + + 2013-11-19 Richard Biener + + Backport from mainline + 2013-11-05 Richard Biener + + PR middle-end/58941 + * tree-dfa.c (get_ref_base_and_extent): Merge common code + in MEM_REF and TARGET_MEM_REF handling. Make sure to + process trailing array detection before diving into the + view-converted object (and possibly apply some extra offset). + + 2013-11-18 Richard Biener + + Backport from mainline + 2013-10-21 Richard Biener + + PR tree-optimization/58794 + * fold-const.c (operand_equal_p): Compare FIELD_DECL operand + of COMPONENT_REFs with OEP_CONSTANT_ADDRESS_OF left in place. + + 2013-10-21 Richard Biener + + PR middle-end/58742 + * fold-const.c (fold_binary_loc): Fold ((T) (X /[ex] C)) * C + to (T) X for sign-changing conversions (or no conversion). + + 2013-11-06 Richard Biener + + PR tree-optimization/58653 + * tree-predcom.c (ref_at_iteration): Rewrite to generate + a MEM_REF. + (prepare_initializers_chain): Adjust. + + PR tree-optimization/59047 + * tree-predcom.c (ref_at_iteration): Handle bitfield accesses + properly. + + 2013-10-15 Richard Biener + + PR tree-optimization/58143 + * tree-ssa-loop-im.c (arith_code_with_undefined_signed_overflow): + New function. + (rewrite_to_defined_overflow): Likewise. + (move_computations_dom_walker::before_dom): Rewrite stmts + with undefined signed overflow that are not always executed + into unsigned arithmetic. + + 2013-11-14 Uros Bizjak + + Backport from mainline + 2013-11-10 Uros Bizjak + + * mode-switching.c (optimize_mode_switching): Mark block as + nontransparent, if last_mode at block exit is different from no_mode. + + Backport from mainline + 2013-11-06 Uros Bizjak + + PR target/59021 + * config/i386/i386.c (ix86_avx_u128_mode_needed): Require + AVX_U128_DIRTY mode for call_insn RTXes that use AVX256 registers. + (ix86_avx_u128_mode_needed): Return AVX_U128_DIRTY mode for call_insn + RTXes that return in AVX256 register. + + 2013-11-14 Jakub Jelinek + Uros Bizjak + + PR target/59101 + * config/i386/i386.md (*anddi_2): Only allow CCZmode if + operands[2] satisfies_constraint_Z that might have bit 31 set. + + 2013-11-12 H.J. Lu + + Backported from mainline + 2013-11-12 H.J. Lu + + PR target/59088 + * config/i386/i386.c (initial_ix86_tune_features): Set + X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL and + X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL for m_HASWELL. + + 2013-11-11 Ramana Radhakrishnan + + Backported from mainline + 2013-10-30 Ramana Radhakrishnan + + PR target/58854 + * config/arm/arm.c (arm_expand_epilogue_apcs_frame): Emit blockage + + 2013-11-11 Jakub Jelinek + + Backported from mainline + 2013-11-06 Jakub Jelinek + + PR middle-end/58970 + * expr.c (get_bit_range): Handle *offset == NULL_TREE. + (expand_assignment): If *bitpos is negative, set *offset + and adjust *bitpos, so that it is not negative. + + 2013-11-05 Jakub Jelinek + + PR rtl-optimization/58997 + * loop-iv.c (iv_subreg): For IV_UNKNOWN_EXTEND, expect + get_iv_value to be in iv->mode rather than iv->extend_mode. + (iv_extend): Likewise. Otherwise, if iv->extend != extend, + use lowpart_subreg on get_iv_value before calling simplify_gen_unary. + * loop-unswitch.c (may_unswitch_on): Make sure op[i] is in the right + mode. + + 2013-11-10 Karlson2k + Kai Tietz + + Merged from trunk + PR plugins/52872 + * configure.ac: Adding for exported symbols check + and for rdynamic-check executable-extension. + * configure: Regenerated. + + 2013-11-07 H.J. Lu + + PR target/59034 + * config/i386/i386.md (push peepholer/splitter): Use Pmode + with stack_pointer_rtx. + + 2013-11-05 Uros Bizjak + + * config/i386/t-rtems (MULTILIB_MATCHES): Fix option typos. + + 2013-11-05 Jakub Jelinek + + PR tree-optimization/58984 + * ipa-prop.c (ipa_load_from_parm_agg_1): Add SIZE_P argument, + set *SIZE_P if non-NULL on success. + (ipa_load_from_parm_agg, ipa_analyze_indirect_call_uses): Adjust + callers. + (ipcp_transform_function): Likewise. Punt if size of access + is different from TYPE_SIZE on v->value's type. + + 2013-11-03 H.J. Lu + + Backport from mainline + 2013-10-12 H.J. Lu + + PR target/58690 + * config/i386/i386.c (ix86_copy_addr_to_reg): New function. + (ix86_expand_movmem): Replace copy_addr_to_reg with + ix86_copy_addr_to_reg. + (ix86_expand_setmem): Likewise. + + 2013-10-29 Uros Bizjak + + Backport from mainline + 2013-08-08 Richard Sandiford + + PR rtl-optimization/58079 + * combine.c (combine_simplify_rtx): Avoid using SUBST if + simplify_comparison has widened a comparison with an integer. + + 2013-10-29 Martin Jambor + + PR middle-end/58789 + Backport from mainline + 2013-05-09 Martin Jambor + + PR lto/57084 + * gimple-fold.c (canonicalize_constructor_val): Call + cgraph_get_create_real_symbol_node instead of cgraph_get_create_node. + + Backport from mainline + 2013-03-16 Jan Hubicka + + * cgraph.h (cgraph_get_create_real_symbol_node): Declare. + * cgraph.c (cgraph_get_create_real_symbol_node): New function. + * cgrpahbuild.c: Use cgraph_get_create_real_symbol_node instead + of cgraph_get_create_node. + * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise. + + 2013-10-28 Tom de Vries + + * cfgexpand.c (gimple_expand_cfg): Remove test for parm_birth_insn. + Don't commit insertions after NOTE_INSN_FUNCTION_BEG. + + 2013-10-26 Uros Bizjak + + Backport from mainline + 2013-10-22 Uros Bizjak + + PR target/58779 + * config/i386/i386.c (put_condition_code) : + Remove CCCmode handling. + : Return 'c' suffix for CCCmode. + : Return 'nc' suffix for CCCmode. + (ix86_cc_mode) : Do not generate overflow checks. + * config/i386/i386.md (*sub3_cconly_overflow): Remove. + (*sub3_cc_overflow): Ditto. + (*subsi3_zext_cc_overflow): Ditto. + + 2013-10-26 Uros Bizjak + + Backport from mainline + 2013-10-19 Uros Bizjak + + PR target/58792 + * config/i386/i386.c (ix86_function_value_regno): Add DX_REG, + ST1_REG and XMM1_REG for 32bit and 64bit targets. Also add DI_REG + and SI_REG for 64bit SYSV ABI targets. + + 2013-08-25 Richard Henderson + + PR rtl/58542 + * optabs.c (maybe_emit_atomic_exchange): Use create_input_operand + instead of create_convert_operand_to. + (maybe_emit_sync_lock_test_and_set): Likewise. + (expand_atomic_compare_and_swap): Likewise. + (maybe_emit_compare_and_swap_exchange_loop): Don't convert_modes. + + 2013-10-25 Eric Botcazou + + PR rtl-optimization/58831 + * alias.c (init_alias_analysis): At the beginning of each iteration, set + the reg_seen[N] bit if static_reg_base_value[N] is non-null. + + 2013-10-25 Eric Botcazou + + * recog.c (search_ofs): New static variable moved from... + (peep2_find_free_register): ...here. + (peephole2_optimize): Initialize it. + + 2013-10-24 David Edelsohn + + Backport from mainline + 2013-10-23 David Edelsohn + + PR target/58838 + * config/rs6000/rs6000.md (mulsi3_internal1 and splitter): Add + TARGET_32BIT final condition. + (mulsi3_internal2 and splitter): Same. + + 2013-10-23 Tom de Vries + + PR tree-optimization/58805 + * tree-ssa-tail-merge.c (stmt_local_def): Add gimple_vdef check. + + 2013-10-23 Richard Biener + + Backport from mainline + 2013-06-24 Richard Biener + + PR tree-optimization/57488 + * tree-ssa-pre.c (insert): Clear NEW sets before each iteration. + + 2013-10-16 Ganesh Gopalasubramanian + + Backport from mainline + 2013-10-16 Ganesh Gopalasubramanian + + + * config/i386/i386.c (ix86_option_override_internal): Enable FMA4 + for AMD bdver3. + + 2013-10-16 Jakub Jelinek + + * BASE-VER: Set to 4.8.3. + * DEV-PHASE: Set to prerelease. + 2013-10-16 Release Manager * GCC 4.8.2 released. *************** *** 639,645 **** 2013-07-31 Andreas Krebbel Backport from mainline ! 2013-03-27 Andreas Krebbel * config/s390/s390.h (TARGET_FLT_EVAL_METHOD): Define. --- 6119,6125 ---- 2013-07-31 Andreas Krebbel Backport from mainline ! 2013-03-27 Andreas Krebbel * config/s390/s390.h (TARGET_FLT_EVAL_METHOD): Define. diff -Nrcpad gcc-4.8.2/gcc/DATESTAMP gcc-4.8.3/gcc/DATESTAMP *** gcc-4.8.2/gcc/DATESTAMP Wed Oct 16 00:16:34 2013 --- gcc-4.8.3/gcc/DATESTAMP Thu May 22 00:16:46 2014 *************** *** 1 **** ! 20131016 --- 1 ---- ! 20140522 diff -Nrcpad gcc-4.8.2/gcc/Makefile.in gcc-4.8.3/gcc/Makefile.in *** gcc-4.8.2/gcc/Makefile.in Mon Jul 8 09:14:34 2013 --- gcc-4.8.3/gcc/Makefile.in Sat Apr 5 10:26:19 2014 *************** BUILD_LINKERFLAGS = $(BUILD_CXXFLAGS) *** 747,753 **** # Native linker and preprocessor flags. For x-fragment overrides. BUILD_LDFLAGS=@BUILD_LDFLAGS@ ! BUILD_CPPFLAGS=$(ALL_CPPFLAGS) # Actual name to use when installing a native compiler. GCC_INSTALL_NAME := $(shell echo gcc|sed '$(program_transform_name)') --- 747,754 ---- # Native linker and preprocessor flags. For x-fragment overrides. BUILD_LDFLAGS=@BUILD_LDFLAGS@ ! BUILD_CPPFLAGS= -I. -I$(@D) -I$(srcdir) -I$(srcdir)/$(@D) \ ! -I$(srcdir)/../include @INCINTL@ $(CPPINC) $(CPPFLAGS) # Actual name to use when installing a native compiler. GCC_INSTALL_NAME := $(shell echo gcc|sed '$(program_transform_name)') *************** s-mlib: $(srcdir)/genmultilib Makefile *** 1827,1833 **** "$(MULTILIB_EXCLUSIONS)" \ "$(MULTILIB_OSDIRNAMES)" \ "$(MULTILIB_REQUIRED)" \ ! "$(MULTIARCH_DIRNAME)" \ "$(MULTILIB_REUSE)" \ "@enable_multilib@" \ > tmp-mlib.h; \ --- 1828,1834 ---- "$(MULTILIB_EXCLUSIONS)" \ "$(MULTILIB_OSDIRNAMES)" \ "$(MULTILIB_REQUIRED)" \ ! "$(if $(MULTILIB_OSDIRNAMES),,$(MULTIARCH_DIRNAME))" \ "$(MULTILIB_REUSE)" \ "@enable_multilib@" \ > tmp-mlib.h; \ *************** tree-ssa-uninit.o : tree-ssa-uninit.c $( *** 2256,2262 **** $(FUNCTION_H) $(TM_H) coretypes.h \ $(TREE_PASS_H) $(BASIC_BLOCK_H) $(BITMAP_H) \ $(FLAGS_H) $(HASHTAB_H) pointer-set.h \ ! $(GIMPLE_H) $(TREE_INLINE_H) $(GIMPLE_PRETTY_PRINT_H) tree-ssa.o : tree-ssa.c $(TREE_FLOW_H) $(CONFIG_H) $(SYSTEM_H) \ $(TREE_H) $(TM_P_H) $(EXPR_H) $(DIAGNOSTIC_H) \ toplev.h $(FUNCTION_H) $(TM_H) coretypes.h \ --- 2257,2263 ---- $(FUNCTION_H) $(TM_H) coretypes.h \ $(TREE_PASS_H) $(BASIC_BLOCK_H) $(BITMAP_H) \ $(FLAGS_H) $(HASHTAB_H) pointer-set.h \ ! $(GIMPLE_H) $(TREE_INLINE_H) $(GIMPLE_PRETTY_PRINT_H) $(PARAMS_H) tree-ssa.o : tree-ssa.c $(TREE_FLOW_H) $(CONFIG_H) $(SYSTEM_H) \ $(TREE_H) $(TM_P_H) $(EXPR_H) $(DIAGNOSTIC_H) \ toplev.h $(FUNCTION_H) $(TM_H) coretypes.h \ *************** tree-switch-conversion.o : tree-switch-c *** 3037,3043 **** $(TM_H) coretypes.h $(GIMPLE_H) \ $(TREE_PASS_H) $(FLAGS_H) $(EXPR_H) $(BASIC_BLOCK_H) \ $(GGC_H) $(OBSTACK_H) $(PARAMS_H) $(CPPLIB_H) $(PARAMS_H) \ ! $(GIMPLE_PRETTY_PRINT_H) langhooks.h tree-complex.o : tree-complex.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TREE_H) \ $(TM_H) $(FLAGS_H) $(TREE_FLOW_H) $(GIMPLE_H) \ tree-iterator.h $(TREE_PASS_H) tree-ssa-propagate.h --- 3038,3044 ---- $(TM_H) coretypes.h $(GIMPLE_H) \ $(TREE_PASS_H) $(FLAGS_H) $(EXPR_H) $(BASIC_BLOCK_H) \ $(GGC_H) $(OBSTACK_H) $(PARAMS_H) $(CPPLIB_H) $(PARAMS_H) \ ! $(GIMPLE_PRETTY_PRINT_H) langhooks.h $(OPTABS_H) tree-complex.o : tree-complex.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TREE_H) \ $(TM_H) $(FLAGS_H) $(TREE_FLOW_H) $(GIMPLE_H) \ tree-iterator.h $(TREE_PASS_H) tree-ssa-propagate.h *************** lra-constraints.o : lra-constraints.c $( *** 3276,3287 **** $(TM_H) $(RTL_H) $(REGS_H) insn-config.h insn-codes.h $(DF_H) \ $(RECOG_H) output.h addresses.h $(REGS_H) hard-reg-set.h $(FLAGS_H) \ $(FUNCTION_H) $(EXPR_H) $(BASIC_BLOCK_H) $(TM_P_H) $(EXCEPT_H) \ ! ira.h rtl-error.h $(LRA_INT_H) lra-eliminations.o : lra-eliminations.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ $(TM_H) $(RTL_H) $(REGS_H) insn-config.h $(DF_H) \ $(RECOG_H) output.h $(REGS_H) hard-reg-set.h $(FLAGS_H) $(FUNCTION_H) \ $(EXPR_H) $(BASIC_BLOCK_H) $(TM_P_H) $(EXCEPT_H) ira.h \ ! rtl-error.h $(LRA_INT_H) lra-lives.o : lra-lives.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(RTL_H) $(REGS_H) insn-config.h $(DF_H) \ $(RECOG_H) output.h $(REGS_H) hard-reg-set.h $(FLAGS_H) $(FUNCTION_H) \ --- 3277,3288 ---- $(TM_H) $(RTL_H) $(REGS_H) insn-config.h insn-codes.h $(DF_H) \ $(RECOG_H) output.h addresses.h $(REGS_H) hard-reg-set.h $(FLAGS_H) \ $(FUNCTION_H) $(EXPR_H) $(BASIC_BLOCK_H) $(TM_P_H) $(EXCEPT_H) \ ! ira.h rtl-error.h $(LRA_INT_H) $(OPTABS_H) lra-eliminations.o : lra-eliminations.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ $(TM_H) $(RTL_H) $(REGS_H) insn-config.h $(DF_H) \ $(RECOG_H) output.h $(REGS_H) hard-reg-set.h $(FLAGS_H) $(FUNCTION_H) \ $(EXPR_H) $(BASIC_BLOCK_H) $(TM_P_H) $(EXCEPT_H) ira.h \ ! rtl-error.h $(LRA_INT_H) $(OPTABS_H) lra-lives.o : lra-lives.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(RTL_H) $(REGS_H) insn-config.h $(DF_H) \ $(RECOG_H) output.h $(REGS_H) hard-reg-set.h $(FLAGS_H) $(FUNCTION_H) \ diff -Nrcpad gcc-4.8.2/gcc/ada/ChangeLog gcc-4.8.3/gcc/ada/ChangeLog *** gcc-4.8.2/gcc/ada/ChangeLog Wed Oct 16 07:20:16 2013 --- gcc-4.8.3/gcc/ada/ChangeLog Thu May 22 09:09:43 2014 *************** *** 1,3 **** --- 1,64 ---- + 2014-05-22 Release Manager + + * GCC 4.8.3 released. + + 2014-03-30 Eric Botcazou + + PR ada/60703 + * system-linux-alpha.ads: Adjust for Ada 2005. + * system-linux-mips.ads: Likewise. + * system-linux-mips64el.ads: Likewise. + * system-linux-mipsel.ads: Likewise. + * system-linux-s390.ads: Likewise. + * system-linux-s390x.ads: Likewise. + * system-linux-sparc.ads: Likewise. + * system-linux-sparcv9.ads: Likewise. + * system-rtems.ads: Likewise. + * system-vxworks-arm.ads: Likewise. + + 2014-03-13 Eric Botcazou + + PR ada/51483 + * back_end.ads (Register_Type_Proc): Add 'precision' parameter. + * cstand.adb (Register_Float_Type): Add 'precision' parameter and use + it to set the RM size. Use directly 'size' for the Esize. + * gcc-interface/gigi.h (enumerate_modes): Add integer parameter. + * gcc-interface/misc.c (enumerate_modes): Likewise. Do not register + types for vector modes, pass the size in addition to the precision. + + 2014-01-12 Eric Botcazou + + PR ada/59772 + * gcc-interface/cuintp.c (build_cst_from_int): Use 32-bit integer type + as intermediate type. + (UI_To_gnu): Likewise. + + 2013-12-12 Eric Botcazou + Iain Sandoe + + PR ada/55946 + * gcc-interface/Make-lang.in (ada/doctools/xgnatugn): Use gnatmake. + * gcc-interface/Makefile.in (GCC_LINK): Add LDFLAGS. + (../../gnatmake): Remove LDFLAGS. + (../../gnatlink): Likewise. + + 2013-12-04 Eric Botcazou + + PR ada/59382 + * indepsw-darwin.adb: New file. + + 2013-10-19 Eric Botcazou + + * gcc-interface/utils.c (scale_by_factor_of): New function. + (rest_of_record_type_compilation): Use scale_by_factor_of in order to + scale the original offset for both rounding cases; in the second case, + take into accout the addend to compute the alignment. Tidy up. + + 2013-10-19 Eric Botcazou + + * gcc-interface/utils.c (gnat_set_type_context): New function. + (gnat_pushdecl): Use it to set the context of the type. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff -Nrcpad gcc-4.8.2/gcc/ada/back_end.ads gcc-4.8.3/gcc/ada/back_end.ads *** gcc-4.8.2/gcc/ada/back_end.ads Thu Aug 4 08:33:14 2011 --- gcc-4.8.3/gcc/ada/back_end.ads Thu Mar 13 15:42:42 2014 *************** package Back_End is *** 55,60 **** --- 55,61 ---- Complex : Boolean; -- True iff type has real and imaginary parts Count : Natural; -- Number of elements in vector, 0 otherwise Float_Rep : Float_Rep_Kind; -- Representation used for fpt type + Precision : Positive; -- Precision of representation in bits Size : Positive; -- Size of representation in bits Alignment : Natural); -- Required alignment in bits pragma Convention (C, Register_Type_Proc); diff -Nrcpad gcc-4.8.2/gcc/ada/cstand.adb gcc-4.8.3/gcc/ada/cstand.adb *** gcc-4.8.2/gcc/ada/cstand.adb Mon Oct 1 09:41:22 2012 --- gcc-4.8.3/gcc/ada/cstand.adb Thu Mar 13 15:42:42 2014 *************** package body CStand is *** 151,156 **** --- 151,157 ---- Complex : Boolean; -- True iff type has real and imaginary parts Count : Natural; -- Number of elements in vector, 0 otherwise Float_Rep : Float_Rep_Kind; -- Representation used for fpt type + Precision : Positive; -- Precision of representation in bits Size : Positive; -- Size of representation in bits Alignment : Natural); -- Required alignment in bits pragma Convention (C, Register_Float_Type); *************** package body CStand is *** 2014,2019 **** --- 2015,2021 ---- Complex : Boolean; Count : Natural; Float_Rep : Float_Rep_Kind; + Precision : Positive; Size : Positive; Alignment : Natural) is *************** package body CStand is *** 2063,2075 **** else Write_Str ("mod 2**"); ! Write_Int (Int (Size / Positive'Max (1, Count))); Write_Line (";"); end if; ! Write_Str ("for " & T & "'Size use "); ! Write_Int (Int (Size)); ! Write_Line (";"); Write_Str ("for " & T & "'Alignment use "); Write_Int (Int (Alignment / 8)); --- 2065,2088 ---- else Write_Str ("mod 2**"); ! Write_Int (Int (Precision / Positive'Max (1, Count))); Write_Line (";"); end if; ! if Precision = Size then ! Write_Str ("for " & T (1 .. Last) & "'Size use "); ! Write_Int (Int (Size)); ! Write_Line (";"); ! ! else ! Write_Str ("for " & T (1 .. Last) & "'Value_Size use "); ! Write_Int (Int (Precision)); ! Write_Line (";"); ! ! Write_Str ("for " & T (1 .. Last) & "'Object_Size use "); ! Write_Int (Int (Size)); ! Write_Line (";"); ! end if; Write_Str ("for " & T & "'Alignment use "); Write_Int (Int (Alignment / 8)); *************** package body CStand is *** 2092,2106 **** if Digs > 0 and then not Complex and then Count = 0 then declare Ent : constant Entity_Id := New_Standard_Entity; - Esize : constant Pos := Pos ((Size + Alignment - 1) - / Alignment * Alignment); begin Set_Defining_Identifier (New_Node (N_Full_Type_Declaration, Stloc), Ent); Make_Name (Ent, T (1 .. Last)); Set_Scope (Ent, Standard_Standard); ! Build_Float_Type (Ent, Esize, Float_Rep, Pos (Digs)); ! Set_RM_Size (Ent, UI_From_Int (Int (Size))); Set_Alignment (Ent, UI_From_Int (Int (Alignment / 8))); if No (Back_End_Float_Types) then --- 2105,2117 ---- if Digs > 0 and then not Complex and then Count = 0 then declare Ent : constant Entity_Id := New_Standard_Entity; begin Set_Defining_Identifier (New_Node (N_Full_Type_Declaration, Stloc), Ent); Make_Name (Ent, T (1 .. Last)); Set_Scope (Ent, Standard_Standard); ! Build_Float_Type (Ent, Int (Size), Float_Rep, Pos (Digs)); ! Set_RM_Size (Ent, UI_From_Int (Int (Precision))); Set_Alignment (Ent, UI_From_Int (Int (Alignment / 8))); if No (Back_End_Float_Types) then diff -Nrcpad gcc-4.8.2/gcc/ada/gcc-interface/Make-lang.in gcc-4.8.3/gcc/ada/gcc-interface/Make-lang.in *** gcc-4.8.2/gcc/ada/gcc-interface/Make-lang.in Wed Feb 6 11:13:07 2013 --- gcc-4.8.3/gcc/ada/gcc-interface/Make-lang.in Thu Dec 12 22:53:43 2013 *************** ada.tags: force *** 625,631 **** ada/doctools/xgnatugn$(build_exeext): ada/xgnatugn.adb -$(MKDIR) ada/doctools $(CP) $^ ada/doctools ! cd ada/doctools && $(GNATMAKE) -q xgnatugn # Note that doc/gnat_ugn.texi and doc/projects.texi do not depend on # xgnatugn being built so we can distribute a pregenerated doc/gnat_ugn.info --- 625,631 ---- ada/doctools/xgnatugn$(build_exeext): ada/xgnatugn.adb -$(MKDIR) ada/doctools $(CP) $^ ada/doctools ! cd ada/doctools && gnatmake -q xgnatugn # Note that doc/gnat_ugn.texi and doc/projects.texi do not depend on # xgnatugn being built so we can distribute a pregenerated doc/gnat_ugn.info diff -Nrcpad gcc-4.8.2/gcc/ada/gcc-interface/Makefile.in gcc-4.8.3/gcc/ada/gcc-interface/Makefile.in *** gcc-4.8.2/gcc/ada/gcc-interface/Makefile.in Wed Feb 6 11:19:08 2013 --- gcc-4.8.3/gcc/ada/gcc-interface/Makefile.in Thu Dec 12 22:53:43 2013 *************** TOOLS_FLAGS_TO_PASS= \ *** 2397,2403 **** "GNATLINK=$(GNATLINK)" \ "GNATBIND=$(GNATBIND)" ! GCC_LINK=$(CC) $(GCC_LINK_FLAGS) $(ADA_INCLUDES) # Build directory for the tools. Let's copy the target-dependent # sources using the same mechanism as for gnatlib. The other sources are --- 2397,2403 ---- "GNATLINK=$(GNATLINK)" \ "GNATBIND=$(GNATBIND)" ! GCC_LINK=$(CC) $(GCC_LINK_FLAGS) $(ADA_INCLUDES) $(LDFLAGS) # Build directory for the tools. Let's copy the target-dependent # sources using the same mechanism as for gnatlib. The other sources are *************** gnatlink-re: ../stamp-tools link.o targe *** 2519,2530 **** # Likewise for the tools ../../gnatmake$(exeext): $(P) b_gnatm.o link.o targext.o $(GNATMAKE_OBJS) ! $(GCC_LINK) $(ALL_CFLAGS) $(LDFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) \ ! $(TOOLS_LIBS) ../../gnatlink$(exeext): $(P) b_gnatl.o link.o targext.o $(GNATLINK_OBJS) ! $(GCC_LINK) $(ALL_CFLAGS) $(LDFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) \ ! $(TOOLS_LIBS) ../stamp-gnatlib-$(RTSDIR): @if [ ! -f stamp-gnatlib-$(RTSDIR) ] ; \ --- 2519,2528 ---- # Likewise for the tools ../../gnatmake$(exeext): $(P) b_gnatm.o link.o targext.o $(GNATMAKE_OBJS) ! +$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) $(TOOLS_LIBS) ../../gnatlink$(exeext): $(P) b_gnatl.o link.o targext.o $(GNATLINK_OBJS) ! +$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) $(TOOLS_LIBS) ../stamp-gnatlib-$(RTSDIR): @if [ ! -f stamp-gnatlib-$(RTSDIR) ] ; \ diff -Nrcpad gcc-4.8.2/gcc/ada/gcc-interface/cuintp.c gcc-4.8.3/gcc/ada/gcc-interface/cuintp.c *** gcc-4.8.2/gcc/ada/gcc-interface/cuintp.c Thu May 10 15:05:39 2012 --- gcc-4.8.3/gcc/ada/gcc-interface/cuintp.c Sun Jan 12 14:29:44 2014 *************** *** 6,12 **** * * * C Implementation File * * * ! * Copyright (C) 1992-2012, Free Software Foundation, Inc. * * * * GNAT is free software; you can redistribute it and/or modify it under * * terms of the GNU General Public License as published by the Free Soft- * --- 6,12 ---- * * * C Implementation File * * * ! * Copyright (C) 1992-2014, Free Software Foundation, Inc. * * * * GNAT is free software; you can redistribute it and/or modify it under * * terms of the GNU General Public License as published by the Free Soft- * *************** *** 59,66 **** static tree build_cst_from_int (tree type, HOST_WIDE_INT low) { ! if (TREE_CODE (type) == REAL_TYPE) ! return convert (type, build_int_cst (NULL_TREE, low)); else return build_int_cst_type (type, low); } --- 59,66 ---- static tree build_cst_from_int (tree type, HOST_WIDE_INT low) { ! if (SCALAR_FLOAT_TYPE_P (type)) ! return convert (type, build_int_cst (gnat_type_for_size (32, 0), low)); else return build_int_cst_type (type, low); } *************** UI_To_gnu (Uint Input, tree type) *** 99,117 **** gcc_assert (Length > 0); /* The computations we perform below always require a type at least as ! large as an integer not to overflow. REAL types are always fine, but INTEGER or ENUMERAL types we are handed may be too short. We use a base integer type node for the computations in this case and will ! convert the final result back to the incoming type later on. ! The base integer precision must be superior than 16. */ ! ! if (TREE_CODE (comp_type) != REAL_TYPE ! && TYPE_PRECISION (comp_type) ! < TYPE_PRECISION (long_integer_type_node)) ! { ! comp_type = long_integer_type_node; ! gcc_assert (TYPE_PRECISION (comp_type) > 16); ! } gnu_base = build_cst_from_int (comp_type, Base); --- 99,110 ---- gcc_assert (Length > 0); /* The computations we perform below always require a type at least as ! large as an integer not to overflow. FP types are always fine, but INTEGER or ENUMERAL types we are handed may be too short. We use a base integer type node for the computations in this case and will ! convert the final result back to the incoming type later on. */ ! if (!SCALAR_FLOAT_TYPE_P (comp_type) && TYPE_PRECISION (comp_type) < 32) ! comp_type = gnat_type_for_size (32, 0); gnu_base = build_cst_from_int (comp_type, Base); diff -Nrcpad gcc-4.8.2/gcc/ada/gcc-interface/gigi.h gcc-4.8.3/gcc/ada/gcc-interface/gigi.h *** gcc-4.8.2/gcc/ada/gcc-interface/gigi.h Thu Jun 13 07:51:32 2013 --- gcc-4.8.3/gcc/ada/gcc-interface/gigi.h Thu Mar 13 15:42:42 2014 *************** extern Nat get_target_double_scalar_alig *** 1014,1020 **** /* This function is called by the front-end to enumerate all the supported modes for the machine, as well as some predefined C types. */ extern void enumerate_modes (void (*f) (const char *, int, int, int, int, int, ! int)); #ifdef __cplusplus } --- 1014,1020 ---- /* This function is called by the front-end to enumerate all the supported modes for the machine, as well as some predefined C types. */ extern void enumerate_modes (void (*f) (const char *, int, int, int, int, int, ! int, int)); #ifdef __cplusplus } diff -Nrcpad gcc-4.8.2/gcc/ada/gcc-interface/misc.c gcc-4.8.3/gcc/ada/gcc-interface/misc.c *** gcc-4.8.2/gcc/ada/gcc-interface/misc.c Wed Jan 2 10:45:00 2013 --- gcc-4.8.3/gcc/ada/gcc-interface/misc.c Thu Mar 13 15:42:42 2014 *************** must_pass_by_ref (tree gnu_type) *** 648,654 **** /* This function is called by the front-end to enumerate all the supported modes for the machine, as well as some predefined C types. F is a function which is called back with the parameters as listed below, first a string, ! then six ints. The name is any arbitrary null-terminated string and has no particular significance, except for the case of predefined C types, where it should be the name of the C type. For integer types, only signed types should be listed, unsigned versions are assumed. The order of types should --- 648,654 ---- /* This function is called by the front-end to enumerate all the supported modes for the machine, as well as some predefined C types. F is a function which is called back with the parameters as listed below, first a string, ! then seven ints. The name is any arbitrary null-terminated string and has no particular significance, except for the case of predefined C types, where it should be the name of the C type. For integer types, only signed types should be listed, unsigned versions are assumed. The order of types should *************** must_pass_by_ref (tree gnu_type) *** 664,674 **** COMPLEX_P nonzero is this represents a complex mode COUNT count of number of items, nonzero for vector mode FLOAT_REP Float_Rep_Kind for FP, otherwise undefined ! SIZE number of bits used to store data ALIGN number of bits to which mode is aligned. */ void ! enumerate_modes (void (*f) (const char *, int, int, int, int, int, int)) { const tree c_types[] = { float_type_node, double_type_node, long_double_type_node }; --- 664,675 ---- COMPLEX_P nonzero is this represents a complex mode COUNT count of number of items, nonzero for vector mode FLOAT_REP Float_Rep_Kind for FP, otherwise undefined ! PRECISION number of bits used to store data ! SIZE number of bits occupied by the mode ALIGN number of bits to which mode is aligned. */ void ! enumerate_modes (void (*f) (const char *, int, int, int, int, int, int, int)) { const tree c_types[] = { float_type_node, double_type_node, long_double_type_node }; *************** enumerate_modes (void (*f) (const char * *** 742,769 **** /* First register any C types for this mode that the front end may need to know about, unless the mode should be skipped. */ ! ! if (!skip_p) for (nameloop = 0; nameloop < ARRAY_SIZE (c_types); nameloop++) { ! tree typ = c_types[nameloop]; ! const char *nam = c_names[nameloop]; ! if (TYPE_MODE (typ) == i) { ! f (nam, digs, complex_p, ! vector_p ? GET_MODE_NUNITS (i) : 0, float_rep, ! TYPE_PRECISION (typ), TYPE_ALIGN (typ)); skip_p = true; } } /* If no predefined C types were found, register the mode itself. */ - if (!skip_p) f (GET_MODE_NAME (i), digs, complex_p, vector_p ? GET_MODE_NUNITS (i) : 0, float_rep, ! GET_MODE_PRECISION (i), GET_MODE_ALIGNMENT (i)); } } --- 743,768 ---- /* First register any C types for this mode that the front end may need to know about, unless the mode should be skipped. */ ! if (!skip_p && !vector_p) for (nameloop = 0; nameloop < ARRAY_SIZE (c_types); nameloop++) { ! tree type = c_types[nameloop]; ! const char *name = c_names[nameloop]; ! if (TYPE_MODE (type) == i) { ! f (name, digs, complex_p, 0, float_rep, TYPE_PRECISION (type), ! TREE_INT_CST_LOW (TYPE_SIZE (type)), TYPE_ALIGN (type)); skip_p = true; } } /* If no predefined C types were found, register the mode itself. */ if (!skip_p) f (GET_MODE_NAME (i), digs, complex_p, vector_p ? GET_MODE_NUNITS (i) : 0, float_rep, ! GET_MODE_PRECISION (i), GET_MODE_BITSIZE (i), ! GET_MODE_ALIGNMENT (i)); } } diff -Nrcpad gcc-4.8.2/gcc/ada/gcc-interface/utils.c gcc-4.8.3/gcc/ada/gcc-interface/utils.c *** gcc-4.8.2/gcc/ada/gcc-interface/utils.c Thu Jun 13 07:51:32 2013 --- gcc-4.8.3/gcc/ada/gcc-interface/utils.c Sat Oct 19 11:11:47 2013 *************** static tree compute_related_constant (tr *** 232,237 **** --- 232,238 ---- static tree split_plus (tree, tree *); static tree float_type_for_precision (int, enum machine_mode); static tree convert_to_fat_pointer (tree, tree); + static unsigned int scale_by_factor_of (tree, unsigned int); static bool potential_alignment_gap (tree, tree, tree); static void process_attributes (tree, struct attrib *); *************** gnat_zaplevel (void) *** 532,537 **** --- 533,554 ---- free_binding_level = level; } + /* Set the context of TYPE and its parallel types (if any) to CONTEXT. */ + + static void + gnat_set_type_context (tree type, tree context) + { + tree decl = TYPE_STUB_DECL (type); + + TYPE_CONTEXT (type) = context; + + while (decl && DECL_PARALLEL_TYPE (decl)) + { + TYPE_CONTEXT (DECL_PARALLEL_TYPE (decl)) = context; + decl = TYPE_STUB_DECL (DECL_PARALLEL_TYPE (decl)); + } + } + /* Record DECL as belonging to the current lexical scope and use GNAT_NODE for location information and flag propagation. */ *************** gnat_pushdecl (tree decl, Node_Id gnat_n *** 613,619 **** if (TREE_CODE (t) == POINTER_TYPE) TYPE_NEXT_PTR_TO (t) = tt; TYPE_NAME (tt) = DECL_NAME (decl); ! TYPE_CONTEXT (tt) = DECL_CONTEXT (decl); TYPE_STUB_DECL (tt) = TYPE_STUB_DECL (t); DECL_ORIGINAL_TYPE (decl) = tt; } --- 630,636 ---- if (TREE_CODE (t) == POINTER_TYPE) TYPE_NEXT_PTR_TO (t) = tt; TYPE_NAME (tt) = DECL_NAME (decl); ! gnat_set_type_context (tt, DECL_CONTEXT (decl)); TYPE_STUB_DECL (tt) = TYPE_STUB_DECL (t); DECL_ORIGINAL_TYPE (decl) = tt; } *************** gnat_pushdecl (tree decl, Node_Id gnat_n *** 623,629 **** /* We need a variant for the placeholder machinery to work. */ tree tt = build_variant_type_copy (t); TYPE_NAME (tt) = decl; ! TYPE_CONTEXT (tt) = DECL_CONTEXT (decl); TREE_USED (tt) = TREE_USED (t); TREE_TYPE (decl) = tt; if (DECL_ORIGINAL_TYPE (TYPE_NAME (t))) --- 640,646 ---- /* We need a variant for the placeholder machinery to work. */ tree tt = build_variant_type_copy (t); TYPE_NAME (tt) = decl; ! gnat_set_type_context (tt, DECL_CONTEXT (decl)); TREE_USED (tt) = TREE_USED (t); TREE_TYPE (decl) = tt; if (DECL_ORIGINAL_TYPE (TYPE_NAME (t))) *************** gnat_pushdecl (tree decl, Node_Id gnat_n *** 645,651 **** if (!(TYPE_NAME (t) && TREE_CODE (TYPE_NAME (t)) == TYPE_DECL)) { TYPE_NAME (t) = decl; ! TYPE_CONTEXT (t) = DECL_CONTEXT (decl); } } } --- 662,668 ---- if (!(TYPE_NAME (t) && TREE_CODE (TYPE_NAME (t)) == TYPE_DECL)) { TYPE_NAME (t) = decl; ! gnat_set_type_context (t, DECL_CONTEXT (decl)); } } } *************** rest_of_record_type_compilation (tree re *** 1692,1784 **** TYPE_SIZE_UNIT (new_record_type) = size_int (TYPE_ALIGN (record_type) / BITS_PER_UNIT); ! /* Now scan all the fields, replacing each field with a new ! field corresponding to the new encoding. */ for (old_field = TYPE_FIELDS (record_type); old_field; old_field = DECL_CHAIN (old_field)) { tree field_type = TREE_TYPE (old_field); tree field_name = DECL_NAME (old_field); - tree new_field; tree curpos = bit_position (old_field); bool var = false; unsigned int align = 0; - tree pos; - - /* See how the position was modified from the last position. ! There are two basic cases we support: a value was added ! to the last position or the last position was rounded to ! a boundary and they something was added. Check for the ! first case first. If not, see if there is any evidence ! of rounding. If so, round the last position and try ! again. ! If this is a union, the position can be taken as zero. */ ! /* Some computations depend on the shape of the position expression, ! so strip conversions to make sure it's exposed. */ ! curpos = remove_conversions (curpos, true); if (TREE_CODE (new_record_type) == UNION_TYPE) ! pos = bitsize_zero_node, align = 0; else pos = compute_related_constant (curpos, last_pos); ! if (!pos && TREE_CODE (curpos) == MULT_EXPR && host_integerp (TREE_OPERAND (curpos, 1), 1)) { tree offset = TREE_OPERAND (curpos, 0); align = tree_low_cst (TREE_OPERAND (curpos, 1), 1); ! ! /* An offset which is a bitwise AND with a mask increases the ! alignment according to the number of trailing zeros. */ ! offset = remove_conversions (offset, true); ! if (TREE_CODE (offset) == BIT_AND_EXPR ! && TREE_CODE (TREE_OPERAND (offset, 1)) == INTEGER_CST) ! { ! unsigned HOST_WIDE_INT mask ! = TREE_INT_CST_LOW (TREE_OPERAND (offset, 1)); ! unsigned int i; ! ! for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) ! { ! if (mask & 1) ! break; ! mask >>= 1; ! align *= 2; ! } ! } ! ! pos = compute_related_constant (curpos, ! round_up (last_pos, align)); } ! else if (!pos && TREE_CODE (curpos) == PLUS_EXPR ! && TREE_CODE (TREE_OPERAND (curpos, 1)) == INTEGER_CST && TREE_CODE (TREE_OPERAND (curpos, 0)) == MULT_EXPR ! && host_integerp (TREE_OPERAND ! (TREE_OPERAND (curpos, 0), 1), ! 1)) { align ! = tree_low_cst ! (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1); ! pos = compute_related_constant (curpos, ! round_up (last_pos, align)); } ! else if (potential_alignment_gap (prev_old_field, old_field, ! pos)) { align = TYPE_ALIGN (field_type); ! pos = compute_related_constant (curpos, ! round_up (last_pos, align)); } /* If we can't compute a position, set it to zero. ! ??? We really should abort here, but it's too much work ! to get this correct for all cases. */ ! if (!pos) pos = bitsize_zero_node; --- 1709,1782 ---- TYPE_SIZE_UNIT (new_record_type) = size_int (TYPE_ALIGN (record_type) / BITS_PER_UNIT); ! /* Now scan all the fields, replacing each field with a new field ! corresponding to the new encoding. */ for (old_field = TYPE_FIELDS (record_type); old_field; old_field = DECL_CHAIN (old_field)) { tree field_type = TREE_TYPE (old_field); tree field_name = DECL_NAME (old_field); tree curpos = bit_position (old_field); + tree pos, new_field; bool var = false; unsigned int align = 0; ! /* We're going to do some pattern matching below so remove as many ! conversions as possible. */ ! curpos = remove_conversions (curpos, true); ! /* See how the position was modified from the last position. ! There are two basic cases we support: a value was added ! to the last position or the last position was rounded to ! a boundary and they something was added. Check for the ! first case first. If not, see if there is any evidence ! of rounding. If so, round the last position and retry. + If this is a union, the position can be taken as zero. */ if (TREE_CODE (new_record_type) == UNION_TYPE) ! pos = bitsize_zero_node; else pos = compute_related_constant (curpos, last_pos); ! if (!pos ! && TREE_CODE (curpos) == MULT_EXPR && host_integerp (TREE_OPERAND (curpos, 1), 1)) { tree offset = TREE_OPERAND (curpos, 0); align = tree_low_cst (TREE_OPERAND (curpos, 1), 1); ! align = scale_by_factor_of (offset, align); ! last_pos = round_up (last_pos, align); ! pos = compute_related_constant (curpos, last_pos); } ! else if (!pos ! && TREE_CODE (curpos) == PLUS_EXPR ! && host_integerp (TREE_OPERAND (curpos, 1), 1) && TREE_CODE (TREE_OPERAND (curpos, 0)) == MULT_EXPR ! && host_integerp ! (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1)) { + tree offset = TREE_OPERAND (TREE_OPERAND (curpos, 0), 0); + unsigned HOST_WIDE_INT addend + = tree_low_cst (TREE_OPERAND (curpos, 1), 1); align ! = tree_low_cst (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1); ! align = scale_by_factor_of (offset, align); ! align = MIN (align, addend & -addend); ! last_pos = round_up (last_pos, align); ! pos = compute_related_constant (curpos, last_pos); } ! else if (potential_alignment_gap (prev_old_field, old_field, pos)) { align = TYPE_ALIGN (field_type); ! last_pos = round_up (last_pos, align); ! pos = compute_related_constant (curpos, last_pos); } /* If we can't compute a position, set it to zero. ! ??? We really should abort here, but it's too much work ! to get this correct for all cases. */ if (!pos) pos = bitsize_zero_node; *************** value_factor_p (tree value, HOST_WIDE_IN *** 2553,2558 **** --- 2551,2582 ---- return false; } + /* Return VALUE scaled by the biggest power-of-2 factor of EXPR. */ + + static unsigned int + scale_by_factor_of (tree expr, unsigned int value) + { + expr = remove_conversions (expr, true); + + /* An expression which is a bitwise AND with a mask has a power-of-2 factor + corresponding to the number of trailing zeros of the mask. */ + if (TREE_CODE (expr) == BIT_AND_EXPR + && TREE_CODE (TREE_OPERAND (expr, 1)) == INTEGER_CST) + { + unsigned HOST_WIDE_INT mask = TREE_INT_CST_LOW (TREE_OPERAND (expr, 1)); + unsigned int i = 0; + + while ((mask & 1) == 0 && i < HOST_BITS_PER_WIDE_INT) + { + mask >>= 1; + value *= 2; + i++; + } + } + + return value; + } + /* Given two consecutive field decls PREV_FIELD and CURR_FIELD, return true unless we can prove these 2 fields are laid out in such a way that no gap exist between the end of PREV_FIELD and the beginning of CURR_FIELD. OFFSET diff -Nrcpad gcc-4.8.2/gcc/ada/indepsw-darwin.adb gcc-4.8.3/gcc/ada/indepsw-darwin.adb *** gcc-4.8.2/gcc/ada/indepsw-darwin.adb Thu Jan 1 00:00:00 1970 --- gcc-4.8.3/gcc/ada/indepsw-darwin.adb Wed Dec 4 21:28:21 2013 *************** *** 0 **** --- 1,67 ---- + ------------------------------------------------------------------------------ + -- -- + -- GNAT COMPILER COMPONENTS -- + -- -- + -- I N D E P S W -- + -- -- + -- B o d y -- + -- (Darwin version) -- + -- -- + -- Copyright (C) 2013, Free Software Foundation, Inc. -- + -- -- + -- GNAT is free software; you can redistribute it and/or modify it under -- + -- terms of the GNU General Public License as published by the Free Soft- -- + -- ware Foundation; either version 3, or (at your option) any later ver- -- + -- sion. GNAT is distributed in the hope that it will be useful, but WITH- -- + -- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- + -- or FITNESS FOR A PARTICULAR PURPOSE. -- + -- -- + -- As a special exception under Section 7 of GPL version 3, you are granted -- + -- additional permissions described in the GCC Runtime Library Exception, -- + -- version 3.1, as published by the Free Software Foundation. -- + -- -- + -- You should have received a copy of the GNU General Public License and -- + -- a copy of the GCC Runtime Library Exception along with this program; -- + -- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- + -- . -- + -- -- + -- GNAT was originally developed by the GNAT team at New York University. -- + -- Extensive contributions were provided by Ada Core Technologies Inc. -- + -- -- + ------------------------------------------------------------------------------ + + -- This is the Darwin version + + package body Indepsw is + + Map_Switch : aliased constant String := "-Wl,-map,"; + + ------------- + -- Convert -- + ------------- + + procedure Convert + (Switch : Switch_Kind; + Argument : String; + To : out String_List_Access) + is + begin + case Switch is + when Map_File => + To := new Argument_List'(1 => new String'(Map_Switch & Argument)); + end case; + end Convert; + + ------------------ + -- Is_Supported -- + ------------------ + + function Is_Supported (Switch : Switch_Kind) return Boolean is + begin + case Switch is + when Map_File => + return True; + end case; + end Is_Supported; + + end Indepsw; diff -Nrcpad gcc-4.8.2/gcc/ada/system-linux-alpha.ads gcc-4.8.3/gcc/ada/system-linux-alpha.ads *** gcc-4.8.2/gcc/ada/system-linux-alpha.ads Mon Aug 6 08:12:10 2012 --- gcc-4.8.3/gcc/ada/system-linux-alpha.ads Sun Mar 30 15:48:19 2014 *************** *** 7,13 **** -- S p e c -- -- (GNU-Linux/alpha Version) -- -- -- ! -- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- --- 7,13 ---- -- S p e c -- -- (GNU-Linux/alpha Version) -- -- -- ! -- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- *************** *** 35,43 **** ------------------------------------------------------------------------------ package System is ! pragma Pure (System); ! -- Note that we take advantage of the implementation permission to ! -- make this unit Pure instead of Preelaborable, see RM 13.7(36) type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; --- 35,44 ---- ------------------------------------------------------------------------------ package System is ! pragma Pure; ! -- Note that we take advantage of the implementation permission to make ! -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada ! -- 2005, this is Pure in any case (AI-362). type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; *************** pragma Pure (System); *** 61,66 **** --- 62,68 ---- -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff -Nrcpad gcc-4.8.2/gcc/ada/system-linux-mips.ads gcc-4.8.3/gcc/ada/system-linux-mips.ads *** gcc-4.8.2/gcc/ada/system-linux-mips.ads Tue Oct 23 14:40:07 2012 --- gcc-4.8.3/gcc/ada/system-linux-mips.ads Sun Mar 30 15:48:19 2014 *************** *** 7,13 **** -- S p e c -- -- (GNU-Linux/MIPS Version) -- -- -- ! -- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- --- 7,13 ---- -- S p e c -- -- (GNU-Linux/MIPS Version) -- -- -- ! -- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- *************** package System is *** 62,67 **** --- 62,68 ---- -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff -Nrcpad gcc-4.8.2/gcc/ada/system-linux-mips64el.ads gcc-4.8.3/gcc/ada/system-linux-mips64el.ads *** gcc-4.8.2/gcc/ada/system-linux-mips64el.ads Tue Oct 23 14:40:07 2012 --- gcc-4.8.3/gcc/ada/system-linux-mips64el.ads Sun Mar 30 15:48:19 2014 *************** *** 7,13 **** -- S p e c -- -- (GNU-Linux/MIPS64EL Version) -- -- -- ! -- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- --- 7,13 ---- -- S p e c -- -- (GNU-Linux/MIPS64EL Version) -- -- -- ! -- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- *************** package System is *** 62,67 **** --- 62,68 ---- -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff -Nrcpad gcc-4.8.2/gcc/ada/system-linux-mipsel.ads gcc-4.8.3/gcc/ada/system-linux-mipsel.ads *** gcc-4.8.2/gcc/ada/system-linux-mipsel.ads Tue Oct 23 14:40:07 2012 --- gcc-4.8.3/gcc/ada/system-linux-mipsel.ads Sun Mar 30 15:48:19 2014 *************** *** 7,13 **** -- S p e c -- -- (GNU-Linux/MIPSEL Version) -- -- -- ! -- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- --- 7,13 ---- -- S p e c -- -- (GNU-Linux/MIPSEL Version) -- -- -- ! -- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- *************** package System is *** 62,67 **** --- 62,68 ---- -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff -Nrcpad gcc-4.8.2/gcc/ada/system-linux-s390.ads gcc-4.8.3/gcc/ada/system-linux-s390.ads *** gcc-4.8.2/gcc/ada/system-linux-s390.ads Mon Aug 6 08:12:10 2012 --- gcc-4.8.3/gcc/ada/system-linux-s390.ads Sun Mar 30 15:48:19 2014 *************** *** 7,13 **** -- S p e c -- -- (GNU-Linux/s390 Version) -- -- -- ! -- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- --- 7,13 ---- -- S p e c -- -- (GNU-Linux/s390 Version) -- -- -- ! -- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- *************** *** 35,43 **** ------------------------------------------------------------------------------ package System is ! pragma Pure (System); ! -- Note that we take advantage of the implementation permission to ! -- make this unit Pure instead of Preelaborable, see RM 13.7(36) type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; --- 35,44 ---- ------------------------------------------------------------------------------ package System is ! pragma Pure; ! -- Note that we take advantage of the implementation permission to make ! -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada ! -- 2005, this is Pure in any case (AI-362). type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; *************** pragma Pure (System); *** 61,66 **** --- 62,68 ---- -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff -Nrcpad gcc-4.8.2/gcc/ada/system-linux-s390x.ads gcc-4.8.3/gcc/ada/system-linux-s390x.ads *** gcc-4.8.2/gcc/ada/system-linux-s390x.ads Mon Aug 6 08:12:10 2012 --- gcc-4.8.3/gcc/ada/system-linux-s390x.ads Sun Mar 30 15:48:19 2014 *************** *** 7,13 **** -- S p e c -- -- (GNU-Linux/s390x Version) -- -- -- ! -- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- --- 7,13 ---- -- S p e c -- -- (GNU-Linux/s390x Version) -- -- -- ! -- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- *************** *** 35,43 **** ------------------------------------------------------------------------------ package System is ! pragma Pure (System); ! -- Note that we take advantage of the implementation permission to ! -- make this unit Pure instead of Preelaborable, see RM 13.7(36) type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; --- 35,44 ---- ------------------------------------------------------------------------------ package System is ! pragma Pure; ! -- Note that we take advantage of the implementation permission to make ! -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada ! -- 2005, this is Pure in any case (AI-362). type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; *************** pragma Pure (System); *** 61,66 **** --- 62,68 ---- -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff -Nrcpad gcc-4.8.2/gcc/ada/system-linux-sparc.ads gcc-4.8.3/gcc/ada/system-linux-sparc.ads *** gcc-4.8.2/gcc/ada/system-linux-sparc.ads Mon Aug 6 08:12:10 2012 --- gcc-4.8.3/gcc/ada/system-linux-sparc.ads Sun Mar 30 15:48:19 2014 *************** *** 7,13 **** -- S p e c -- -- (GNU/Linux-SPARC Version) -- -- -- ! -- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- --- 7,13 ---- -- S p e c -- -- (GNU/Linux-SPARC Version) -- -- -- ! -- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- *************** *** 35,43 **** ------------------------------------------------------------------------------ package System is ! pragma Pure (System); ! -- Note that we take advantage of the implementation permission to ! -- make this unit Pure instead of Preelaborable, see RM 13.7(36) type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; --- 35,44 ---- ------------------------------------------------------------------------------ package System is ! pragma Pure; ! -- Note that we take advantage of the implementation permission to make ! -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada ! -- 2005, this is Pure in any case (AI-362). type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; *************** pragma Pure (System); *** 61,66 **** --- 62,68 ---- -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff -Nrcpad gcc-4.8.2/gcc/ada/system-linux-sparcv9.ads gcc-4.8.3/gcc/ada/system-linux-sparcv9.ads *** gcc-4.8.2/gcc/ada/system-linux-sparcv9.ads Tue Aug 30 16:49:06 2011 --- gcc-4.8.3/gcc/ada/system-linux-sparcv9.ads Sun Mar 30 15:48:19 2014 *************** *** 7,13 **** -- S p e c -- -- (GNU/Linux-SPARCV9 Version) -- -- -- ! -- Copyright (C) 1992-2011, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- --- 7,13 ---- -- S p e c -- -- (GNU/Linux-SPARCV9 Version) -- -- -- ! -- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- *************** *** 35,43 **** ------------------------------------------------------------------------------ package System is ! pragma Pure (System); ! -- Note that we take advantage of the implementation permission to ! -- make this unit Pure instead of Preelaborable, see RM 13.7(36) type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; --- 35,44 ---- ------------------------------------------------------------------------------ package System is ! pragma Pure; ! -- Note that we take advantage of the implementation permission to make ! -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada ! -- 2005, this is Pure in any case (AI-362). type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; *************** pragma Pure (System); *** 61,66 **** --- 62,68 ---- -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff -Nrcpad gcc-4.8.2/gcc/ada/system-rtems.ads gcc-4.8.3/gcc/ada/system-rtems.ads *** gcc-4.8.2/gcc/ada/system-rtems.ads Tue Aug 30 16:49:06 2011 --- gcc-4.8.3/gcc/ada/system-rtems.ads Sun Mar 30 15:48:19 2014 *************** *** 7,13 **** -- S p e c -- -- (Compiler Version) -- -- -- ! -- Copyright (C) 1992-2011 Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- --- 7,13 ---- -- S p e c -- -- (Compiler Version) -- -- -- ! -- Copyright (C) 1992-2014 Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- *************** *** 34,42 **** -- -- ------------------------------------------------------------------------------ ! -- This version of System is a RTEMS version that is used in building ! -- the compiler. This is based as closely as possible on the generic ! -- version with the following exceptions: -- + priority definitions package System is --- 34,41 ---- -- -- ------------------------------------------------------------------------------ ! -- This version is for RTEMS. It is based as closely as possible on the ! -- generic version with the following exceptions: -- + priority definitions package System is *************** package System is *** 67,72 **** --- 66,72 ---- -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := Standard'Storage_Unit; diff -Nrcpad gcc-4.8.2/gcc/ada/system-vxworks-arm.ads gcc-4.8.3/gcc/ada/system-vxworks-arm.ads *** gcc-4.8.2/gcc/ada/system-vxworks-arm.ads Mon Aug 6 08:12:10 2012 --- gcc-4.8.3/gcc/ada/system-vxworks-arm.ads Sun Mar 30 15:48:19 2014 *************** *** 7,13 **** -- S p e c -- -- (VxWorks Version ARM) -- -- -- ! -- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- --- 7,13 ---- -- S p e c -- -- (VxWorks Version ARM) -- -- -- ! -- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- *************** *** 35,44 **** ------------------------------------------------------------------------------ package System is ! pragma Pure (System); ! -- Note that we take advantage of the implementation permission to make this ! -- unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada 2005, this is ! -- Pure in any case (AI-362). type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; --- 35,44 ---- ------------------------------------------------------------------------------ package System is ! pragma Pure; ! -- Note that we take advantage of the implementation permission to make ! -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada ! -- 2005, this is Pure in any case (AI-362). type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; diff -Nrcpad gcc-4.8.2/gcc/alias.c gcc-4.8.3/gcc/alias.c *** gcc-4.8.2/gcc/alias.c Tue Mar 5 09:40:38 2013 --- gcc-4.8.3/gcc/alias.c Mon Mar 17 15:31:43 2014 *************** static int insert_subset_children (splay *** 156,162 **** static alias_set_entry get_alias_set_entry (alias_set_type); static bool nonoverlapping_component_refs_p (const_rtx, const_rtx); static tree decl_for_component_ref (tree); ! static int write_dependence_p (const_rtx, const_rtx, int); static void memory_modified_1 (rtx, const_rtx, void *); --- 156,164 ---- static alias_set_entry get_alias_set_entry (alias_set_type); static bool nonoverlapping_component_refs_p (const_rtx, const_rtx); static tree decl_for_component_ref (tree); ! static int write_dependence_p (const_rtx, ! const_rtx, enum machine_mode, rtx, ! bool, bool, bool); static void memory_modified_1 (rtx, const_rtx, void *); *************** canon_true_dependence (const_rtx mem, en *** 2558,2572 **** } /* Returns nonzero if a write to X might alias a previous read from ! (or, if WRITEP is nonzero, a write to) MEM. */ static int ! write_dependence_p (const_rtx mem, const_rtx x, int writep) { ! rtx x_addr, mem_addr; rtx base; int ret; if (MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem)) return 1; --- 2560,2583 ---- } /* Returns nonzero if a write to X might alias a previous read from ! (or, if WRITEP is true, a write to) MEM. ! If X_CANONCALIZED is true, then X_ADDR is the canonicalized address of X, ! and X_MODE the mode for that access. ! If MEM_CANONICALIZED is true, MEM is canonicalized. */ static int ! write_dependence_p (const_rtx mem, ! const_rtx x, enum machine_mode x_mode, rtx x_addr, ! bool mem_canonicalized, bool x_canonicalized, bool writep) { ! rtx mem_addr; rtx base; int ret; + gcc_checking_assert (x_canonicalized + ? (x_addr != NULL_RTX && x_mode != VOIDmode) + : (x_addr == NULL_RTX && x_mode == VOIDmode)); + if (MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem)) return 1; *************** write_dependence_p (const_rtx mem, const *** 2590,2606 **** if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x)) return 1; - x_addr = XEXP (x, 0); mem_addr = XEXP (mem, 0); ! if (!((GET_CODE (x_addr) == VALUE ! && GET_CODE (mem_addr) != VALUE ! && reg_mentioned_p (x_addr, mem_addr)) ! || (GET_CODE (x_addr) != VALUE ! && GET_CODE (mem_addr) == VALUE ! && reg_mentioned_p (mem_addr, x_addr)))) { ! x_addr = get_addr (x_addr); ! mem_addr = get_addr (mem_addr); } if (! writep) --- 2601,2621 ---- if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x)) return 1; mem_addr = XEXP (mem, 0); ! if (!x_addr) { ! x_addr = XEXP (x, 0); ! if (!((GET_CODE (x_addr) == VALUE ! && GET_CODE (mem_addr) != VALUE ! && reg_mentioned_p (x_addr, mem_addr)) ! || (GET_CODE (x_addr) != VALUE ! && GET_CODE (mem_addr) == VALUE ! && reg_mentioned_p (mem_addr, x_addr)))) ! { ! x_addr = get_addr (x_addr); ! if (!mem_canonicalized) ! mem_addr = get_addr (mem_addr); ! } } if (! writep) *************** write_dependence_p (const_rtx mem, const *** 2616,2626 **** GET_MODE (mem))) return 0; ! x_addr = canon_rtx (x_addr); ! mem_addr = canon_rtx (mem_addr); if ((ret = memrefs_conflict_p (SIZE_FOR_MODE (mem), mem_addr, ! SIZE_FOR_MODE (x), x_addr, 0)) != -1) return ret; if (nonoverlapping_memrefs_p (x, mem, false)) --- 2631,2646 ---- GET_MODE (mem))) return 0; ! if (!x_canonicalized) ! { ! x_addr = canon_rtx (x_addr); ! x_mode = GET_MODE (x); ! } ! if (!mem_canonicalized) ! mem_addr = canon_rtx (mem_addr); if ((ret = memrefs_conflict_p (SIZE_FOR_MODE (mem), mem_addr, ! GET_MODE_SIZE (x_mode), x_addr, 0)) != -1) return ret; if (nonoverlapping_memrefs_p (x, mem, false)) *************** write_dependence_p (const_rtx mem, const *** 2634,2640 **** int anti_dependence (const_rtx mem, const_rtx x) { ! return write_dependence_p (mem, x, /*writep=*/0); } /* Output dependence: X is written after store in MEM takes place. */ --- 2654,2676 ---- int anti_dependence (const_rtx mem, const_rtx x) { ! return write_dependence_p (mem, x, VOIDmode, NULL_RTX, ! /*mem_canonicalized=*/false, ! /*x_canonicalized*/false, /*writep=*/false); ! } ! ! /* Likewise, but we already have a canonicalized MEM, and X_ADDR for X. ! Also, consider X in X_MODE (which might be from an enclosing ! STRICT_LOW_PART / ZERO_EXTRACT). ! If MEM_CANONICALIZED is true, MEM is canonicalized. */ ! ! int ! canon_anti_dependence (const_rtx mem, bool mem_canonicalized, ! const_rtx x, enum machine_mode x_mode, rtx x_addr) ! { ! return write_dependence_p (mem, x, x_mode, x_addr, ! mem_canonicalized, /*x_canonicalized=*/true, ! /*writep=*/false); } /* Output dependence: X is written after store in MEM takes place. */ *************** anti_dependence (const_rtx mem, const_rt *** 2642,2648 **** int output_dependence (const_rtx mem, const_rtx x) { ! return write_dependence_p (mem, x, /*writep=*/1); } --- 2678,2686 ---- int output_dependence (const_rtx mem, const_rtx x) { ! return write_dependence_p (mem, x, VOIDmode, NULL_RTX, ! /*mem_canonicalized=*/false, ! /*x_canonicalized*/false, /*writep=*/true); } *************** init_alias_analysis (void) *** 2871,2886 **** /* Wipe the reg_seen array clean. */ bitmap_clear (reg_seen); ! /* Mark all hard registers which may contain an address. ! The stack, frame and argument pointers may contain an address. ! An argument register which can hold a Pmode value may contain ! an address even if it is not in BASE_REGS. ! ! The address expression is VOIDmode for an argument and ! Pmode for other registers. */ ! ! memcpy (new_reg_base_value, static_reg_base_value, ! FIRST_PSEUDO_REGISTER * sizeof (rtx)); /* Walk the insns adding values to the new_reg_base_value array. */ for (i = 0; i < rpo_cnt; i++) --- 2909,2921 ---- /* Wipe the reg_seen array clean. */ bitmap_clear (reg_seen); ! /* Initialize the alias information for this pass. */ ! for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) ! if (static_reg_base_value[i]) ! { ! new_reg_base_value[i] = static_reg_base_value[i]; ! bitmap_set_bit (reg_seen, i); ! } /* Walk the insns adding values to the new_reg_base_value array. */ for (i = 0; i < rpo_cnt; i++) diff -Nrcpad gcc-4.8.2/gcc/bb-reorder.c gcc-4.8.3/gcc/bb-reorder.c *** gcc-4.8.2/gcc/bb-reorder.c Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/bb-reorder.c Sun Mar 23 11:30:57 2014 *************** fix_up_fall_thru_edges (void) *** 1685,1693 **** edge e; edge_iterator ei; - /* Find EDGE_CAN_FALLTHRU edge. */ FOR_EACH_EDGE (e, ei, cur_bb->succs) ! if (e->flags & EDGE_CAN_FALLTHRU) { fall_thru = e; break; --- 1685,1692 ---- edge e; edge_iterator ei; FOR_EACH_EDGE (e, ei, cur_bb->succs) ! if (e->flags & EDGE_FALLTHRU) { fall_thru = e; break; diff -Nrcpad gcc-4.8.2/gcc/builtins.c gcc-4.8.3/gcc/builtins.c *** gcc-4.8.2/gcc/builtins.c Fri May 3 08:55:08 2013 --- gcc-4.8.3/gcc/builtins.c Fri May 9 10:16:14 2014 *************** static tree fold_builtin_varargs (locati *** 180,186 **** static tree fold_builtin_strpbrk (location_t, tree, tree, tree); static tree fold_builtin_strstr (location_t, tree, tree, tree); static tree fold_builtin_strrchr (location_t, tree, tree, tree); - static tree fold_builtin_strcat (location_t, tree, tree); static tree fold_builtin_strncat (location_t, tree, tree, tree); static tree fold_builtin_strspn (location_t, tree, tree); static tree fold_builtin_strcspn (location_t, tree, tree); --- 180,185 ---- *************** expand_builtin_setjmp_receiver (rtx rece *** 906,914 **** if (! HAVE_nonlocal_goto) #endif { emit_move_insn (virtual_stack_vars_rtx, hard_frame_pointer_rtx); ! /* This might change the hard frame pointer in ways that aren't ! apparent to early optimization passes, so force a clobber. */ emit_clobber (hard_frame_pointer_rtx); } --- 905,928 ---- if (! HAVE_nonlocal_goto) #endif { + /* First adjust our frame pointer to its actual value. It was + previously set to the start of the virtual area corresponding to + the stacked variables when we branched here and now needs to be + adjusted to the actual hardware fp value. + + Assignments to virtual registers are converted by + instantiate_virtual_regs into the corresponding assignment + to the underlying register (fp in this case) that makes + the original assignment true. + So the following insn will actually be decrementing fp by + STARTING_FRAME_OFFSET. */ emit_move_insn (virtual_stack_vars_rtx, hard_frame_pointer_rtx); ! ! /* Restoring the frame pointer also modifies the hard frame pointer. ! Mark it used (so that the previous assignment remains live once ! the frame pointer is eliminated) and clobbered (to represent the ! implicit update from the assignment). */ ! emit_use (hard_frame_pointer_rtx); emit_clobber (hard_frame_pointer_rtx); } *************** expand_builtin_setjmp_receiver (rtx rece *** 949,956 **** /* We must not allow the code we just generated to be reordered by scheduling. Specifically, the update of the frame pointer must ! happen immediately, not later. Similarly, we must block ! (frame-related) register values to be used across this code. */ emit_insn (gen_blockage ()); } --- 963,969 ---- /* We must not allow the code we just generated to be reordered by scheduling. Specifically, the update of the frame pointer must ! happen immediately, not later. */ emit_insn (gen_blockage ()); } *************** expand_builtin_mathfn (tree exp, rtx tar *** 1958,1963 **** --- 1971,1977 ---- tree fndecl = get_callee_fndecl (exp); enum machine_mode mode; bool errno_set = false; + bool try_widening = false; tree arg; if (!validate_arglist (exp, REAL_TYPE, VOID_TYPE)) *************** expand_builtin_mathfn (tree exp, rtx tar *** 1969,1974 **** --- 1983,1989 ---- { CASE_FLT_FN (BUILT_IN_SQRT): errno_set = ! tree_expr_nonnegative_p (arg); + try_widening = true; builtin_optab = sqrt_optab; break; CASE_FLT_FN (BUILT_IN_EXP): *************** expand_builtin_mathfn (tree exp, rtx tar *** 2025,2032 **** if (! flag_errno_math || ! HONOR_NANS (mode)) errno_set = false; ! /* Before working hard, check whether the instruction is available. */ ! if (optab_handler (builtin_optab, mode) != CODE_FOR_nothing && (!errno_set || !optimize_insn_for_size_p ())) { rtx result = gen_reg_rtx (mode); --- 2040,2049 ---- if (! flag_errno_math || ! HONOR_NANS (mode)) errno_set = false; ! /* Before working hard, check whether the instruction is available, but try ! to widen the mode for specific operations. */ ! if ((optab_handler (builtin_optab, mode) != CODE_FOR_nothing ! || (try_widening && !excess_precision_type (TREE_TYPE (exp)))) && (!errno_set || !optimize_insn_for_size_p ())) { rtx result = gen_reg_rtx (mode); *************** static rtx *** 5347,5353 **** expand_builtin_atomic_compare_exchange (enum machine_mode mode, tree exp, rtx target) { ! rtx expect, desired, mem, oldval; enum memmodel success, failure; tree weak; bool is_weak; --- 5364,5370 ---- expand_builtin_atomic_compare_exchange (enum machine_mode mode, tree exp, rtx target) { ! rtx expect, desired, mem, oldval, label; enum memmodel success, failure; tree weak; bool is_weak; *************** expand_builtin_atomic_compare_exchange ( *** 5385,5398 **** if (host_integerp (weak, 0) && tree_low_cst (weak, 0) != 0) is_weak = true; ! oldval = expect; ! if (!expand_atomic_compare_and_swap ((target == const0_rtx ? NULL : &target), ! &oldval, mem, oldval, desired, is_weak, success, failure)) return NULL_RTX; ! if (oldval != expect) ! emit_move_insn (expect, oldval); return target; } --- 5402,5427 ---- if (host_integerp (weak, 0) && tree_low_cst (weak, 0) != 0) is_weak = true; ! if (target == const0_rtx) ! target = NULL; ! ! /* Lest the rtl backend create a race condition with an imporoper store ! to memory, always create a new pseudo for OLDVAL. */ ! oldval = NULL; ! ! if (!expand_atomic_compare_and_swap (&target, &oldval, mem, expect, desired, is_weak, success, failure)) return NULL_RTX; ! /* Conditionally store back to EXPECT, lest we create a race condition ! with an improper store to memory. */ ! /* ??? With a rearrangement of atomics at the gimple level, we can handle ! the normal case where EXPECT is totally private, i.e. a register. At ! which point the store can be unconditional. */ ! label = gen_label_rtx (); ! emit_cmp_and_jump_insns (target, const0_rtx, NE, NULL, VOIDmode, 1, label); ! emit_move_insn (expect, oldval); ! emit_label (label); return target; } *************** expand_builtin (tree exp, rtx target, rt *** 5846,5851 **** --- 5875,5883 ---- switch (fcode) { CASE_FLT_FN (BUILT_IN_FABS): + case BUILT_IN_FABSD32: + case BUILT_IN_FABSD64: + case BUILT_IN_FABSD128: target = expand_builtin_fabs (exp, target, subtarget); if (target) return target; *************** fold_builtin_1 (location_t loc, tree fnd *** 10298,10303 **** --- 10330,10338 ---- return fold_builtin_strlen (loc, type, arg0); CASE_FLT_FN (BUILT_IN_FABS): + case BUILT_IN_FABSD32: + case BUILT_IN_FABSD64: + case BUILT_IN_FABSD128: return fold_builtin_fabs (loc, arg0, type); case BUILT_IN_ABS: *************** fold_builtin_2 (location_t loc, tree fnd *** 10766,10772 **** return fold_builtin_strstr (loc, arg0, arg1, type); case BUILT_IN_STRCAT: ! return fold_builtin_strcat (loc, arg0, arg1); case BUILT_IN_STRSPN: return fold_builtin_strspn (loc, arg0, arg1); --- 10801,10807 ---- return fold_builtin_strstr (loc, arg0, arg1, type); case BUILT_IN_STRCAT: ! return fold_builtin_strcat (loc, arg0, arg1, NULL_TREE); case BUILT_IN_STRSPN: return fold_builtin_strspn (loc, arg0, arg1); *************** fold_builtin_strpbrk (location_t loc, tr *** 11809,11816 **** COMPOUND_EXPR in the chain will contain the tree for the simplified form of the builtin function call. */ ! static tree ! fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src) { if (!validate_arg (dst, POINTER_TYPE) || !validate_arg (src, POINTER_TYPE)) --- 11844,11852 ---- COMPOUND_EXPR in the chain will contain the tree for the simplified form of the builtin function call. */ ! tree ! fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src, ! tree len) { if (!validate_arg (dst, POINTER_TYPE) || !validate_arg (src, POINTER_TYPE)) *************** fold_builtin_strcat (location_t loc ATTR *** 11828,11849 **** /* See if we can store by pieces into (dst + strlen(dst)). */ tree newdst, call; tree strlen_fn = builtin_decl_implicit (BUILT_IN_STRLEN); ! tree strcpy_fn = builtin_decl_implicit (BUILT_IN_STRCPY); ! if (!strlen_fn || !strcpy_fn) return NULL_TREE; ! /* If we don't have a movstr we don't want to emit an strcpy ! call. We have to do that if the length of the source string ! isn't computable (in that case we can use memcpy probably ! later expanding to a sequence of mov instructions). If we ! have movstr instructions we can emit strcpy calls. */ ! if (!HAVE_movstr) ! { ! tree len = c_strlen (src, 1); ! if (! len || TREE_SIDE_EFFECTS (len)) ! return NULL_TREE; ! } /* Stabilize the argument list. */ dst = builtin_save_expr (dst); --- 11864,11880 ---- /* See if we can store by pieces into (dst + strlen(dst)). */ tree newdst, call; tree strlen_fn = builtin_decl_implicit (BUILT_IN_STRLEN); ! tree memcpy_fn = builtin_decl_implicit (BUILT_IN_MEMCPY); ! if (!strlen_fn || !memcpy_fn) return NULL_TREE; ! /* If the length of the source string isn't computable don't ! split strcat into strlen and memcpy. */ ! if (! len) ! len = c_strlen (src, 1); ! if (! len || TREE_SIDE_EFFECTS (len)) ! return NULL_TREE; /* Stabilize the argument list. */ dst = builtin_save_expr (dst); *************** fold_builtin_strcat (location_t loc ATTR *** 11855,11861 **** newdst = fold_build_pointer_plus_loc (loc, dst, newdst); newdst = builtin_save_expr (newdst); ! call = build_call_expr_loc (loc, strcpy_fn, 2, newdst, src); return build2 (COMPOUND_EXPR, TREE_TYPE (dst), call, dst); } return NULL_TREE; --- 11886,11896 ---- newdst = fold_build_pointer_plus_loc (loc, dst, newdst); newdst = builtin_save_expr (newdst); ! len = fold_convert_loc (loc, size_type_node, len); ! len = size_binop_loc (loc, PLUS_EXPR, len, ! build_int_cst (size_type_node, 1)); ! ! call = build_call_expr_loc (loc, memcpy_fn, 3, newdst, src, len); return build2 (COMPOUND_EXPR, TREE_TYPE (dst), call, dst); } return NULL_TREE; diff -Nrcpad gcc-4.8.2/gcc/builtins.def gcc-4.8.3/gcc/builtins.def *** gcc-4.8.2/gcc/builtins.def Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/builtins.def Fri Apr 4 14:27:06 2014 *************** DEF_C99_BUILTIN (BUILT_IN_EXPM1L, *** 252,257 **** --- 252,260 ---- DEF_LIB_BUILTIN (BUILT_IN_FABS, "fabs", BT_FN_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSF, "fabsf", BT_FN_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSL, "fabsl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) + DEF_GCC_BUILTIN (BUILT_IN_FABSD32, "fabsd32", BT_FN_DFLOAT32_DFLOAT32, ATTR_CONST_NOTHROW_LEAF_LIST) + DEF_GCC_BUILTIN (BUILT_IN_FABSD64, "fabsd64", BT_FN_DFLOAT64_DFLOAT64, ATTR_CONST_NOTHROW_LEAF_LIST) + DEF_GCC_BUILTIN (BUILT_IN_FABSD128, "fabsd128", BT_FN_DFLOAT128_DFLOAT128, ATTR_CONST_NOTHROW_LEAF_LIST) DEF_C99_BUILTIN (BUILT_IN_FDIM, "fdim", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) DEF_C99_BUILTIN (BUILT_IN_FDIMF, "fdimf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) DEF_C99_BUILTIN (BUILT_IN_FDIML, "fdiml", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) diff -Nrcpad gcc-4.8.2/gcc/c/ChangeLog gcc-4.8.3/gcc/c/ChangeLog *** gcc-4.8.2/gcc/c/ChangeLog Wed Oct 16 07:19:52 2013 --- gcc-4.8.3/gcc/c/ChangeLog Thu May 22 09:10:45 2014 *************** *** 1,3 **** --- 1,53 ---- + 2014-05-22 Release Manager + + * GCC 4.8.3 released. + + 2014-04-10 Jakub Jelinek + + Backport from mainline + 2014-03-28 Jakub Jelinek + + PR c++/60689 + * c-tree.h (c_build_function_call_vec): New prototype. + * c-typeck.c (build_function_call_vec): Don't call + resolve_overloaded_builtin here. + (c_build_function_call_vec): New wrapper function around + build_function_call_vec. Call resolve_overloaded_builtin here. + (convert_lvalue_to_rvalue, build_function_call, build_atomic_assign): + Call c_build_function_call_vec instead of build_function_call_vec. + * c-parser.c (c_parser_postfix_expression_after_primary): Likewise. + * c-decl.c (finish_decl): Likewise. + + 2014-01-23 Jakub Jelinek + + PR middle-end/58809 + * c-typeck.c (c_finish_omp_clause): Reject MIN_EXPR, MAX_EXPR, + BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR on COMPLEX_TYPEs. + + 2014-01-22 Marek Polacek + + Backport from mainline + 2014-01-22 Marek Polacek + + PR c/59891 + * c-typeck.c (build_conditional_expr): Call c_fully_fold instead + of remove_c_maybe_const_expr on op1 and op2. + + 2013-12-03 Marek Polacek + + Backport from mainline + 2013-12-03 Marek Polacek + + PR c/59351 + * c-decl.c (build_compound_literal): Allow compound literals with + empty initial value. + + 2013-11-27 Tom de Vries + Marc Glisse + + PR c++/59032 + * c-typeck.c (build_unary_op): Allow vector increment and decrement. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff -Nrcpad gcc-4.8.2/gcc/c/c-decl.c gcc-4.8.3/gcc/c/c-decl.c *** gcc-4.8.2/gcc/c/c-decl.c Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/c/c-decl.c Thu Apr 10 07:54:08 2014 *************** finish_decl (tree decl, location_t init_ *** 4507,4514 **** cleanup = build_unary_op (input_location, ADDR_EXPR, decl, 0); vec_alloc (v, 1); v->quick_push (cleanup); ! cleanup = build_function_call_vec (DECL_SOURCE_LOCATION (decl), ! cleanup_decl, v, NULL); vec_free (v); /* Don't warn about decl unused; the cleanup uses it. */ --- 4507,4514 ---- cleanup = build_unary_op (input_location, ADDR_EXPR, decl, 0); vec_alloc (v, 1); v->quick_push (cleanup); ! cleanup = c_build_function_call_vec (DECL_SOURCE_LOCATION (decl), ! cleanup_decl, v, NULL); vec_free (v); /* Don't warn about decl unused; the cleanup uses it. */ *************** build_compound_literal (location_t loc, *** 4632,4638 **** { int failure = complete_array_type (&TREE_TYPE (decl), DECL_INITIAL (decl), true); ! gcc_assert (!failure); type = TREE_TYPE (decl); TREE_TYPE (DECL_INITIAL (decl)) = type; --- 4632,4640 ---- { int failure = complete_array_type (&TREE_TYPE (decl), DECL_INITIAL (decl), true); ! /* If complete_array_type returns 3, it means that the ! initial value of the compound literal is empty. Allow it. */ ! gcc_assert (failure == 0 || failure == 3); type = TREE_TYPE (decl); TREE_TYPE (DECL_INITIAL (decl)) = type; diff -Nrcpad gcc-4.8.2/gcc/c/c-parser.c gcc-4.8.3/gcc/c/c-parser.c *** gcc-4.8.2/gcc/c/c-parser.c Tue Feb 12 20:07:04 2013 --- gcc-4.8.3/gcc/c/c-parser.c Thu Apr 10 07:54:08 2014 *************** c_parser_postfix_expression_after_primar *** 6904,6911 **** sizeof_ptr_memacc_comptypes); /* FIXME diagnostics: Ideally we want the FUNCNAME, not the "(" after the FUNCNAME, which is what we have now. */ ! expr.value = build_function_call_vec (op_loc, expr.value, exprlist, ! origtypes); expr.original_code = ERROR_MARK; if (TREE_CODE (expr.value) == INTEGER_CST && TREE_CODE (orig_expr.value) == FUNCTION_DECL --- 6904,6911 ---- sizeof_ptr_memacc_comptypes); /* FIXME diagnostics: Ideally we want the FUNCNAME, not the "(" after the FUNCNAME, which is what we have now. */ ! expr.value = c_build_function_call_vec (op_loc, expr.value, exprlist, ! origtypes); expr.original_code = ERROR_MARK; if (TREE_CODE (expr.value) == INTEGER_CST && TREE_CODE (orig_expr.value) == FUNCTION_DECL diff -Nrcpad gcc-4.8.2/gcc/c/c-tree.h gcc-4.8.3/gcc/c/c-tree.h *** gcc-4.8.2/gcc/c/c-tree.h Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/c/c-tree.h Thu Apr 10 07:54:08 2014 *************** extern tree c_finish_omp_task (location_ *** 640,645 **** --- 640,647 ---- extern tree c_finish_omp_clauses (tree); extern tree c_build_va_arg (location_t, tree, tree); extern tree c_finish_transaction (location_t, tree, int); + extern tree c_build_function_call_vec (location_t, tree, vec *, + vec *); /* Set to 0 at beginning of a function definition, set to 1 if a return statement that specifies a return value is seen. */ diff -Nrcpad gcc-4.8.2/gcc/c/c-typeck.c gcc-4.8.3/gcc/c/c-typeck.c *** gcc-4.8.2/gcc/c/c-typeck.c Thu Jan 24 16:59:44 2013 --- gcc-4.8.3/gcc/c/c-typeck.c Thu Apr 10 07:54:08 2014 *************** build_function_call (location_t loc, tre *** 2666,2672 **** vec_alloc (v, list_length (params)); for (; params; params = TREE_CHAIN (params)) v->quick_push (TREE_VALUE (params)); ! ret = build_function_call_vec (loc, function, v, NULL); vec_free (v); return ret; } --- 2666,2672 ---- vec_alloc (v, list_length (params)); for (; params; params = TREE_CHAIN (params)) v->quick_push (TREE_VALUE (params)); ! ret = c_build_function_call_vec (loc, function, v, NULL); vec_free (v); return ret; } *************** build_function_call_vec (location_t loc, *** 2705,2718 **** /* Convert anything with function type to a pointer-to-function. */ if (TREE_CODE (function) == FUNCTION_DECL) { - /* Implement type-directed function overloading for builtins. - resolve_overloaded_builtin and targetm.resolve_overloaded_builtin - handle all the type checking. The result is a complete expression - that implements this function call. */ - tem = resolve_overloaded_builtin (loc, function, params); - if (tem) - return tem; - name = DECL_NAME (function); if (flag_tm) --- 2705,2710 ---- *************** build_function_call_vec (location_t loc, *** 2863,2868 **** --- 2855,2884 ---- } return require_complete_type (result); } + + /* Like build_function_call_vec, but call also resolve_overloaded_builtin. */ + + tree + c_build_function_call_vec (location_t loc, tree function, + vec *params, + vec *origtypes) + { + /* Strip NON_LVALUE_EXPRs, etc., since we aren't using as an lvalue. */ + STRIP_TYPE_NOPS (function); + + /* Convert anything with function type to a pointer-to-function. */ + if (TREE_CODE (function) == FUNCTION_DECL) + { + /* Implement type-directed function overloading for builtins. + resolve_overloaded_builtin and targetm.resolve_overloaded_builtin + handle all the type checking. The result is a complete expression + that implements this function call. */ + tree tem = resolve_overloaded_builtin (loc, function, params); + if (tem) + return tem; + } + return build_function_call_vec (loc, function, params, origtypes); + } /* Convert the argument expressions in the vector VALUES to the types in the list TYPELIST. *************** build_unary_op (location_t location, *** 3629,3635 **** /* Report invalid types. */ if (typecode != POINTER_TYPE && typecode != FIXED_POINT_TYPE ! && typecode != INTEGER_TYPE && typecode != REAL_TYPE) { if (code == PREINCREMENT_EXPR || code == POSTINCREMENT_EXPR) error_at (location, "wrong type argument to increment"); --- 3645,3652 ---- /* Report invalid types. */ if (typecode != POINTER_TYPE && typecode != FIXED_POINT_TYPE ! && typecode != INTEGER_TYPE && typecode != REAL_TYPE ! && typecode != VECTOR_TYPE) { if (code == PREINCREMENT_EXPR || code == POSTINCREMENT_EXPR) error_at (location, "wrong type argument to increment"); *************** build_unary_op (location_t location, *** 3694,3700 **** } else { ! inc = integer_one_node; inc = convert (argtype, inc); } --- 3711,3719 ---- } else { ! inc = (TREE_CODE (argtype) == VECTOR_TYPE ! ? build_one_cst (argtype) ! : integer_one_node); inc = convert (argtype, inc); } *************** build_conditional_expr (location_t colon *** 4331,4338 **** { if (int_operands) { ! op1 = remove_c_maybe_const_expr (op1); ! op2 = remove_c_maybe_const_expr (op2); } ret = build3 (COND_EXPR, result_type, ifexp, op1, op2); if (int_operands) --- 4350,4359 ---- { if (int_operands) { ! /* Use c_fully_fold here, since C_MAYBE_CONST_EXPR might be ! nested inside of the expression. */ ! op1 = c_fully_fold (op1, false, NULL); ! op2 = c_fully_fold (op2, false, NULL); } ret = build3 (COND_EXPR, result_type, ifexp, op1, op2); if (int_operands) *************** c_finish_omp_clauses (tree clauses) *** 10618,10624 **** "%qE has invalid type for %", t); remove = true; } ! else if (FLOAT_TYPE_P (TREE_TYPE (t))) { enum tree_code r_code = OMP_CLAUSE_REDUCTION_CODE (c); const char *r_name = NULL; --- 10639,10646 ---- "%qE has invalid type for %", t); remove = true; } ! else if (FLOAT_TYPE_P (TREE_TYPE (t)) ! || TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE) { enum tree_code r_code = OMP_CLAUSE_REDUCTION_CODE (c); const char *r_name = NULL; *************** c_finish_omp_clauses (tree clauses) *** 10628,10635 **** --- 10650,10663 ---- case PLUS_EXPR: case MULT_EXPR: case MINUS_EXPR: + break; case MIN_EXPR: + if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE) + r_name = "min"; + break; case MAX_EXPR: + if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE) + r_name = "max"; break; case BIT_AND_EXPR: r_name = "&"; *************** c_finish_omp_clauses (tree clauses) *** 10641,10650 **** r_name = "|"; break; case TRUTH_ANDIF_EXPR: ! r_name = "&&"; break; case TRUTH_ORIF_EXPR: ! r_name = "||"; break; default: gcc_unreachable (); --- 10669,10680 ---- r_name = "|"; break; case TRUTH_ANDIF_EXPR: ! if (FLOAT_TYPE_P (TREE_TYPE (t))) ! r_name = "&&"; break; case TRUTH_ORIF_EXPR: ! if (FLOAT_TYPE_P (TREE_TYPE (t))) ! r_name = "||"; break; default: gcc_unreachable (); diff -Nrcpad gcc-4.8.2/gcc/c-family/ChangeLog gcc-4.8.3/gcc/c-family/ChangeLog *** gcc-4.8.2/gcc/c-family/ChangeLog Wed Oct 16 07:20:26 2013 --- gcc-4.8.3/gcc/c-family/ChangeLog Thu May 22 09:10:04 2014 *************** *** 1,3 **** --- 1,82 ---- + 2014-05-22 Release Manager + + * GCC 4.8.3 released. + + 2014-05-06 Richard Biener + + * c-opts.c (c_common_post_options): For -freestanding, + -fno-hosted and -fno-builtin disable pattern recognition + if not enabled explicitely. + + 2014-04-10 Jakub Jelinek + + Backport from mainline + 2014-03-28 Jakub Jelinek + + PR c++/60689 + * c-common.c (add_atomic_size_parameter): When creating new + params vector, push the size argument first. + + 2014-03-22 Jakub Jelinek + + PR debug/60603 + * c-opts.c (c_finish_options): Restore cb_file_change call to + . + + 2014-03-13 Jakub Jelinek + + PR middle-end/36282 + * c-pragma.c (apply_pragma_weak): Only look at + TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) if + DECL_ASSEMBLER_NAME_SET_P (decl). + (maybe_apply_pending_pragma_weaks): Exit early if + vec_safe_is_empty (pending_weaks) rather than only when + !pending_weaks. + (maybe_apply_pragma_weak): Likewise. If !DECL_ASSEMBLER_NAME_SET_P, + set assembler name back to NULL afterwards. + + 2014-04-07 Dominique d'Humieres + + Backport from mainline + 2013-09-14 Iain Sandoe + + PR target/48094 + * c.opt (fgnu-runtime, fnext-runtime, fobjc-abi-version, + fobjc-gc, freplace-objc-classes): Accept for LTO. + + 2014-03-06 Jakub Jelinek + + Backport from mainline + 2014-02-19 Jakub Jelinek + + PR c/37743 + * c-common.c (c_common_nodes_and_builtins): When initializing + c_uint{16,32,64}_type_node, also set corresponding + uint{16,32,64}_type_node to the same value. + + 2014-02-12 Jakub Jelinek + + PR c/60101 + * c-common.c (merge_tlist): If copy is true, call new_tlist, + if false, add ADD itself, rather than vice versa. + (verify_tree): For COND_EXPR, don't call merge_tlist with non-zero + copy. For SAVE_EXPR, only call merge_tlist once. + + 2013-11-29 Jakub Jelinek + + PR c/59280 + * c-common.c (get_priority): If TREE_VALUE (args) is IDENTIFIER_NODE, + goto invalid. If it is error_mark_node, don't issue further + diagnostics. + + 2013-11-04 Marek Polacek + + Backport from mainline + 2013-11-04 Marek Polacek + + PR c++/58979 + * c-common.c (invalid_indirection_error): Handle RO_ARROW_STAR case. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff -Nrcpad gcc-4.8.2/gcc/c-family/c-common.c gcc-4.8.3/gcc/c-family/c-common.c *** gcc-4.8.2/gcc/c-family/c-common.c Tue May 14 20:52:27 2013 --- gcc-4.8.3/gcc/c-family/c-common.c Thu Apr 10 07:54:08 2014 *************** merge_tlist (struct tlist **to, struct t *** 2894,2900 **** } if (!found) { ! *end = copy ? add : new_tlist (NULL, add->expr, add->writer); end = &(*end)->next; *end = 0; } --- 2894,2900 ---- } if (!found) { ! *end = copy ? new_tlist (NULL, add->expr, add->writer) : add; end = &(*end)->next; *end = 0; } *************** verify_tree (tree x, struct tlist **pbef *** 3052,3058 **** verify_tree (TREE_OPERAND (x, 0), &tmp_before, &tmp_list2, NULL_TREE); warn_for_collisions (tmp_list2); merge_tlist (pbefore_sp, tmp_before, 0); ! merge_tlist (pbefore_sp, tmp_list2, 1); tmp_list3 = tmp_nosp = 0; verify_tree (TREE_OPERAND (x, 1), &tmp_list3, &tmp_nosp, NULL_TREE); --- 3052,3058 ---- verify_tree (TREE_OPERAND (x, 0), &tmp_before, &tmp_list2, NULL_TREE); warn_for_collisions (tmp_list2); merge_tlist (pbefore_sp, tmp_before, 0); ! merge_tlist (pbefore_sp, tmp_list2, 0); tmp_list3 = tmp_nosp = 0; verify_tree (TREE_OPERAND (x, 1), &tmp_list3, &tmp_nosp, NULL_TREE); *************** verify_tree (tree x, struct tlist **pbef *** 3156,3167 **** warn_for_collisions (tmp_nosp); tmp_list3 = 0; ! while (tmp_nosp) ! { ! struct tlist *t = tmp_nosp; ! tmp_nosp = t->next; ! merge_tlist (&tmp_list3, t, 0); ! } t->cache_before_sp = tmp_before; t->cache_after_sp = tmp_list3; } --- 3156,3162 ---- warn_for_collisions (tmp_nosp); tmp_list3 = 0; ! merge_tlist (&tmp_list3, tmp_nosp, 0); t->cache_before_sp = tmp_before; t->cache_after_sp = tmp_list3; } *************** c_common_nodes_and_builtins (void) *** 5511,5523 **** uint8_type_node = TREE_TYPE (identifier_global_value (c_get_ident (UINT8_TYPE))); if (UINT16_TYPE) ! c_uint16_type_node = TREE_TYPE (identifier_global_value (c_get_ident (UINT16_TYPE))); if (UINT32_TYPE) ! c_uint32_type_node = TREE_TYPE (identifier_global_value (c_get_ident (UINT32_TYPE))); if (UINT64_TYPE) ! c_uint64_type_node = TREE_TYPE (identifier_global_value (c_get_ident (UINT64_TYPE))); if (INT_LEAST8_TYPE) int_least8_type_node = --- 5506,5518 ---- uint8_type_node = TREE_TYPE (identifier_global_value (c_get_ident (UINT8_TYPE))); if (UINT16_TYPE) ! c_uint16_type_node = uint16_type_node = TREE_TYPE (identifier_global_value (c_get_ident (UINT16_TYPE))); if (UINT32_TYPE) ! c_uint32_type_node = uint32_type_node = TREE_TYPE (identifier_global_value (c_get_ident (UINT32_TYPE))); if (UINT64_TYPE) ! c_uint64_type_node = uint64_type_node = TREE_TYPE (identifier_global_value (c_get_ident (UINT64_TYPE))); if (INT_LEAST8_TYPE) int_least8_type_node = *************** get_priority (tree args, bool is_destruc *** 6917,6922 **** --- 6912,6921 ---- } arg = TREE_VALUE (args); + if (TREE_CODE (arg) == IDENTIFIER_NODE) + goto invalid; + if (arg == error_mark_node) + return DEFAULT_INIT_PRIORITY; arg = default_conversion (arg); if (!host_integerp (arg, /*pos=*/0) || !INTEGRAL_TYPE_P (TREE_TYPE (arg))) *************** invalid_indirection_error (location_t lo *** 9763,9768 **** --- 9762,9772 ---- "invalid type argument of %<->%> (have %qT)", type); break; + case RO_ARROW_STAR: + error_at (loc, + "invalid type argument of %<->*%> (have %qT)", + type); + break; case RO_IMPLICIT_CONVERSION: error_at (loc, "invalid type argument of implicit conversion (have %qT)", *************** add_atomic_size_parameter (unsigned n, l *** 10198,10203 **** --- 10202,10208 ---- len = params->length (); vec_alloc (v, len + 1); + v->quick_push (build_int_cst (size_type_node, n)); for (z = 0; z < len; z++) v->quick_push ((*params)[z]); f = build_function_call_vec (loc, function, v, NULL); diff -Nrcpad gcc-4.8.2/gcc/c-family/c-opts.c gcc-4.8.3/gcc/c-family/c-opts.c *** gcc-4.8.2/gcc/c-family/c-opts.c Mon Feb 18 19:42:56 2013 --- gcc-4.8.3/gcc/c-family/c-opts.c Tue May 6 10:48:55 2014 *************** c_common_post_options (const char **pfil *** 840,845 **** --- 840,851 ---- if (flag_objc_exceptions && !flag_objc_sjlj_exceptions) flag_exceptions = 1; + /* If -ffreestanding, -fno-hosted or -fno-builtin then disable + pattern recognition. */ + if (!global_options_set.x_flag_tree_loop_distribute_patterns + && flag_no_builtin) + flag_tree_loop_distribute_patterns = 0; + /* -Woverlength-strings is off by default, but is enabled by -Wpedantic. It is never enabled in C++, as the minimum limit is not normative in that standard. */ *************** c_finish_options (void) *** 1258,1274 **** { size_t i; ! { ! /* Make sure all of the builtins about to be declared have ! BUILTINS_LOCATION has their source_location. */ ! source_location builtins_loc = BUILTINS_LOCATION; ! cpp_force_token_locations (parse_in, &builtins_loc); ! cpp_init_builtins (parse_in, flag_hosted); ! c_cpp_builtins (parse_in); ! cpp_stop_forcing_token_locations (parse_in); ! } /* We're about to send user input to cpplib, so make it warn for things that we previously (when we sent it internal definitions) --- 1264,1281 ---- { size_t i; ! cb_file_change (parse_in, ! linemap_add (line_table, LC_RENAME, 0, ! _(""), 0)); ! /* Make sure all of the builtins about to be declared have ! BUILTINS_LOCATION has their source_location. */ ! source_location builtins_loc = BUILTINS_LOCATION; ! cpp_force_token_locations (parse_in, &builtins_loc); ! cpp_init_builtins (parse_in, flag_hosted); ! c_cpp_builtins (parse_in); ! cpp_stop_forcing_token_locations (parse_in); /* We're about to send user input to cpplib, so make it warn for things that we previously (when we sent it internal definitions) diff -Nrcpad gcc-4.8.2/gcc/c-family/c-pragma.c gcc-4.8.3/gcc/c-family/c-pragma.c *** gcc-4.8.2/gcc/c-family/c-pragma.c Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/c-family/c-pragma.c Thu Apr 10 07:47:55 2014 *************** apply_pragma_weak (tree decl, tree value *** 259,264 **** --- 259,265 ---- if (SUPPORTS_WEAK && DECL_EXTERNAL (decl) && TREE_USED (decl) && !DECL_WEAK (decl) /* Don't complain about a redundant #pragma. */ + && DECL_ASSEMBLER_NAME_SET_P (decl) && TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl))) warning (OPT_Wpragmas, "applying #pragma weak %q+D after first use " "results in unspecified behavior", decl); *************** maybe_apply_pragma_weak (tree decl) *** 276,282 **** /* Avoid asking for DECL_ASSEMBLER_NAME when it's not needed. */ /* No weak symbols pending, take the short-cut. */ ! if (!pending_weaks) return; /* If it's not visible outside this file, it doesn't matter whether it's weak. */ --- 277,283 ---- /* Avoid asking for DECL_ASSEMBLER_NAME when it's not needed. */ /* No weak symbols pending, take the short-cut. */ ! if (vec_safe_is_empty (pending_weaks)) return; /* If it's not visible outside this file, it doesn't matter whether it's weak. */ *************** maybe_apply_pragma_weak (tree decl) *** 288,294 **** if (TREE_CODE (decl) != FUNCTION_DECL && TREE_CODE (decl) != VAR_DECL) return; ! id = DECL_ASSEMBLER_NAME (decl); FOR_EACH_VEC_ELT (*pending_weaks, i, pe) if (id == pe->name) --- 289,301 ---- if (TREE_CODE (decl) != FUNCTION_DECL && TREE_CODE (decl) != VAR_DECL) return; ! if (DECL_ASSEMBLER_NAME_SET_P (decl)) ! id = DECL_ASSEMBLER_NAME (decl); ! else ! { ! id = DECL_ASSEMBLER_NAME (decl); ! SET_DECL_ASSEMBLER_NAME (decl, NULL_TREE); ! } FOR_EACH_VEC_ELT (*pending_weaks, i, pe) if (id == pe->name) *************** maybe_apply_pending_pragma_weaks (void) *** 309,315 **** pending_weak *pe; symtab_node target; ! if (!pending_weaks) return; FOR_EACH_VEC_ELT (*pending_weaks, i, pe) --- 316,322 ---- pending_weak *pe; symtab_node target; ! if (vec_safe_is_empty (pending_weaks)) return; FOR_EACH_VEC_ELT (*pending_weaks, i, pe) diff -Nrcpad gcc-4.8.2/gcc/c-family/c.opt gcc-4.8.3/gcc/c-family/c.opt *** gcc-4.8.2/gcc/c-family/c.opt Sat Jan 19 05:25:25 2013 --- gcc-4.8.3/gcc/c-family/c.opt Mon Apr 7 06:40:18 2014 *************** C++ ObjC++ Var(flag_no_gnu_keywords, 0) *** 933,939 **** Recognize GNU-defined keywords fgnu-runtime ! ObjC ObjC++ Report RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME) Generate code for GNU runtime environment fgnu89-inline --- 933,939 ---- Recognize GNU-defined keywords fgnu-runtime ! ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME) Generate code for GNU runtime environment fgnu89-inline *************** fnew-abi *** 1007,1013 **** C++ ObjC++ Ignore Warn(switch %qs is no longer supported) fnext-runtime ! ObjC ObjC++ Report RejectNegative Var(flag_next_runtime) Generate code for NeXT (Apple Mac OS X) runtime environment fnil-receivers --- 1007,1013 ---- C++ ObjC++ Ignore Warn(switch %qs is no longer supported) fnext-runtime ! ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime) Generate code for NeXT (Apple Mac OS X) runtime environment fnil-receivers *************** C++ ObjC++ Optimization Var(flag_nothrow *** 1025,1031 **** Treat a throw() exception specification as noexcept to improve code size fobjc-abi-version= ! ObjC ObjC++ Joined Report RejectNegative UInteger Var(flag_objc_abi) Specify which ABI to use for Objective-C family code and meta-data generation. ; Generate special '- .cxx_construct' and '- .cxx_destruct' methods --- 1025,1031 ---- Treat a throw() exception specification as noexcept to improve code size fobjc-abi-version= ! ObjC ObjC++ LTO Joined Report RejectNegative UInteger Var(flag_objc_abi) Specify which ABI to use for Objective-C family code and meta-data generation. ; Generate special '- .cxx_construct' and '- .cxx_destruct' methods *************** ObjC ObjC++ Var(flag_objc_exceptions) *** 1045,1051 **** Enable Objective-C exception and synchronization syntax fobjc-gc ! ObjC ObjC++ Var(flag_objc_gc) Enable garbage collection (GC) in Objective-C/Objective-C++ programs fobjc-nilcheck --- 1045,1051 ---- Enable Objective-C exception and synchronization syntax fobjc-gc ! ObjC ObjC++ LTO Var(flag_objc_gc) Enable garbage collection (GC) in Objective-C/Objective-C++ programs fobjc-nilcheck *************** C++ ObjC++ Var(flag_pretty_templates) In *** 1105,1111 **** -fno-pretty-templates Do not pretty-print template specializations as the template signature followed by the arguments freplace-objc-classes ! ObjC ObjC++ Var(flag_replace_objc_classes) Used in Fix-and-Continue mode to indicate that object files may be swapped in at runtime frepo --- 1105,1111 ---- -fno-pretty-templates Do not pretty-print template specializations as the template signature followed by the arguments freplace-objc-classes ! ObjC ObjC++ LTO Var(flag_replace_objc_classes) Used in Fix-and-Continue mode to indicate that object files may be swapped in at runtime frepo diff -Nrcpad gcc-4.8.2/gcc/calls.c gcc-4.8.3/gcc/calls.c *** gcc-4.8.2/gcc/calls.c Fri Jan 11 23:39:18 2013 --- gcc-4.8.3/gcc/calls.c Fri Apr 4 14:09:23 2014 *************** store_unaligned_arguments_into_pseudos ( *** 983,988 **** --- 983,989 ---- for (i = 0; i < num_actuals; i++) if (args[i].reg != 0 && ! args[i].pass_on_stack + && GET_CODE (args[i].reg) != PARALLEL && args[i].mode == BLKmode && MEM_P (args[i].value) && (MEM_ALIGN (args[i].value) *************** initialize_argument_information (int num *** 1327,1332 **** --- 1328,1334 ---- #else args[i].reg != 0, #endif + reg_parm_stack_space, args[i].pass_on_stack ? 0 : args[i].partial, fndecl, args_size, &args[i].locate); #ifdef BLOCK_REG_PADDING *************** expand_call (tree exp, rtx target, int i *** 3171,3177 **** --- 3173,3181 ---- group load/store machinery below. */ if (!structure_value_addr && !pcc_struct_value + && TYPE_MODE (rettype) != VOIDmode && TYPE_MODE (rettype) != BLKmode + && REG_P (valreg) && targetm.calls.return_in_msb (rettype)) { if (shift_return_value (TYPE_MODE (rettype), false, valreg)) *************** emit_library_call_value_1 (int retval, r *** 3734,3740 **** #else argvec[count].reg != 0, #endif ! 0, NULL_TREE, &args_size, &argvec[count].locate); if (argvec[count].reg == 0 || argvec[count].partial != 0 || reg_parm_stack_space > 0) --- 3738,3745 ---- #else argvec[count].reg != 0, #endif ! reg_parm_stack_space, 0, ! NULL_TREE, &args_size, &argvec[count].locate); if (argvec[count].reg == 0 || argvec[count].partial != 0 || reg_parm_stack_space > 0) *************** emit_library_call_value_1 (int retval, r *** 3821,3827 **** #else argvec[count].reg != 0, #endif ! argvec[count].partial, NULL_TREE, &args_size, &argvec[count].locate); args_size.constant += argvec[count].locate.size.constant; gcc_assert (!argvec[count].locate.size.var); --- 3826,3832 ---- #else argvec[count].reg != 0, #endif ! reg_parm_stack_space, argvec[count].partial, NULL_TREE, &args_size, &argvec[count].locate); args_size.constant += argvec[count].locate.size.constant; gcc_assert (!argvec[count].locate.size.var); diff -Nrcpad gcc-4.8.2/gcc/cfgcleanup.c gcc-4.8.3/gcc/cfgcleanup.c *** gcc-4.8.2/gcc/cfgcleanup.c Tue Sep 10 11:48:30 2013 --- gcc-4.8.3/gcc/cfgcleanup.c Thu Jan 9 07:30:16 2014 *************** flow_find_cross_jump (basic_block bb1, b *** 1293,1299 **** { rtx i1, i2, last1, last2, afterlast1, afterlast2; int ninsns = 0; - rtx p1; enum replace_direction dir, last_dir, afterlast_dir; bool follow_fallthru, did_fallthru; --- 1293,1298 ---- *************** flow_find_cross_jump (basic_block bb1, b *** 1321,1328 **** || (returnjump_p (i2) && !side_effects_p (PATTERN (i2)))) { last2 = i2; ! /* Count everything except for unconditional jump as insn. */ ! if (!simplejump_p (i2) && !returnjump_p (i2) && last1) ninsns++; i2 = PREV_INSN (i2); } --- 1320,1328 ---- || (returnjump_p (i2) && !side_effects_p (PATTERN (i2)))) { last2 = i2; ! /* Count everything except for unconditional jump as insn. ! Don't count any jumps if dir_p is NULL. */ ! if (!simplejump_p (i2) && !returnjump_p (i2) && last1 && dir_p) ninsns++; i2 = PREV_INSN (i2); } *************** flow_find_cross_jump (basic_block bb1, b *** 1373,1380 **** last1 = i1, last2 = i2; afterlast_dir = last_dir; last_dir = dir; ! p1 = PATTERN (i1); ! if (!(GET_CODE (p1) == USE || GET_CODE (p1) == CLOBBER)) ninsns++; } --- 1373,1380 ---- last1 = i1, last2 = i2; afterlast_dir = last_dir; last_dir = dir; ! if (GET_CODE (PATTERN (i1)) != USE ! && GET_CODE (PATTERN (i1)) != CLOBBER) ninsns++; } *************** flow_find_cross_jump (basic_block bb1, b *** 1420,1426 **** /* Like flow_find_cross_jump, except start looking for a matching sequence from the head of the two blocks. Do not include jumps at the end. If STOP_AFTER is nonzero, stop after finding that many matching ! instructions. */ int flow_find_head_matching_sequence (basic_block bb1, basic_block bb2, rtx *f1, --- 1420,1427 ---- /* Like flow_find_cross_jump, except start looking for a matching sequence from the head of the two blocks. Do not include jumps at the end. If STOP_AFTER is nonzero, stop after finding that many matching ! instructions. If STOP_AFTER is zero, count all INSN_P insns, if it is ! non-zero, only count active insns. */ int flow_find_head_matching_sequence (basic_block bb1, basic_block bb2, rtx *f1, *************** flow_find_head_matching_sequence (basic_ *** 1492,1498 **** beforelast1 = last1, beforelast2 = last2; last1 = i1, last2 = i2; ! ninsns++; } if (i1 == BB_END (bb1) || i2 == BB_END (bb2) --- 1493,1502 ---- beforelast1 = last1, beforelast2 = last2; last1 = i1, last2 = i2; ! if (!stop_after ! || (GET_CODE (PATTERN (i1)) != USE ! && GET_CODE (PATTERN (i1)) != CLOBBER)) ! ninsns++; } if (i1 == BB_END (bb1) || i2 == BB_END (bb2) diff -Nrcpad gcc-4.8.2/gcc/cfgexpand.c gcc-4.8.3/gcc/cfgexpand.c *** gcc-4.8.2/gcc/cfgexpand.c Tue Mar 5 22:31:50 2013 --- gcc-4.8.3/gcc/cfgexpand.c Tue Jan 7 16:49:22 2014 *************** stack_var_conflict_p (size_t x, size_t y *** 331,337 **** enter its partition number into bitmap DATA. */ static bool ! visit_op (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) { bitmap active = (bitmap)data; op = get_base_address (op); --- 331,337 ---- enter its partition number into bitmap DATA. */ static bool ! visit_op (gimple, tree op, tree, void *data) { bitmap active = (bitmap)data; op = get_base_address (op); *************** visit_op (gimple stmt ATTRIBUTE_UNUSED, *** 351,357 **** from bitmap DATA. */ static bool ! visit_conflict (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) { bitmap active = (bitmap)data; op = get_base_address (op); --- 351,357 ---- from bitmap DATA. */ static bool ! visit_conflict (gimple, tree op, tree, void *data) { bitmap active = (bitmap)data; op = get_base_address (op); *************** add_scope_conflicts_1 (basic_block bb, b *** 385,391 **** edge e; edge_iterator ei; gimple_stmt_iterator gsi; ! bool (*visit)(gimple, tree, void *); bitmap_clear (work); FOR_EACH_EDGE (e, ei, bb->preds) --- 385,391 ---- edge e; edge_iterator ei; gimple_stmt_iterator gsi; ! walk_stmt_load_store_addr_fn visit; bitmap_clear (work); FOR_EACH_EDGE (e, ei, bb->preds) *************** gimple_expand_cfg (void) *** 4707,4720 **** if (e->insns.r) { rebuild_jump_labels_chain (e->insns.r); ! /* Avoid putting insns before parm_birth_insn. */ if (e->src == ENTRY_BLOCK_PTR ! && single_succ_p (ENTRY_BLOCK_PTR) ! && parm_birth_insn) { rtx insns = e->insns.r; e->insns.r = NULL_RTX; ! emit_insn_after_noloc (insns, parm_birth_insn, e->dest); } else commit_one_edge_insertion (e); --- 4707,4724 ---- if (e->insns.r) { rebuild_jump_labels_chain (e->insns.r); ! /* Put insns after parm birth, but before ! NOTE_INSNS_FUNCTION_BEG. */ if (e->src == ENTRY_BLOCK_PTR ! && single_succ_p (ENTRY_BLOCK_PTR)) { rtx insns = e->insns.r; e->insns.r = NULL_RTX; ! if (NOTE_P (parm_birth_insn) ! && NOTE_KIND (parm_birth_insn) == NOTE_INSN_FUNCTION_BEG) ! emit_insn_before_noloc (insns, parm_birth_insn, e->dest); ! else ! emit_insn_after_noloc (insns, parm_birth_insn, e->dest); } else commit_one_edge_insertion (e); diff -Nrcpad gcc-4.8.2/gcc/cgraph.c gcc-4.8.3/gcc/cgraph.c *** gcc-4.8.2/gcc/cgraph.c Wed May 22 07:50:40 2013 --- gcc-4.8.3/gcc/cgraph.c Tue Oct 29 14:32:13 2013 *************** verify_cgraph (void) *** 2596,2599 **** --- 2596,2642 ---- FOR_EACH_FUNCTION (node) verify_cgraph_node (node); } + + /* Create external decl node for DECL. + The difference i nbetween cgraph_get_create_node and + cgraph_get_create_real_symbol_node is that cgraph_get_create_node + may return inline clone, while cgraph_get_create_real_symbol_node + will create a new node in this case. + FIXME: This function should be removed once clones are put out of decl + hash. */ + + struct cgraph_node * + cgraph_get_create_real_symbol_node (tree decl) + { + struct cgraph_node *first_clone = cgraph_get_node (decl); + struct cgraph_node *node; + /* create symbol table node. even if inline clone exists, we can not take + it as a target of non-inlined call. */ + node = cgraph_get_node (decl); + if (node && !node->global.inlined_to) + return node; + + node = cgraph_create_node (decl); + + /* ok, we previously inlined the function, then removed the offline copy and + now we want it back for external call. this can happen when devirtualizing + while inlining function called once that happens after extern inlined and + virtuals are already removed. in this case introduce the external node + and make it available for call. */ + if (first_clone) + { + first_clone->clone_of = node; + node->clones = first_clone; + symtab_prevail_in_asm_name_hash ((symtab_node) node); + symtab_insert_node_to_hashtable ((symtab_node) node); + if (dump_file) + fprintf (dump_file, "Introduced new external node " + "(%s/%i) and turned into root of the clone tree.\n", + xstrdup (cgraph_node_name (node)), node->uid); + } + else if (dump_file) + fprintf (dump_file, "Introduced new external node " + "(%s/%i).\n", xstrdup (cgraph_node_name (node)), node->uid); + return node; + } #include "gt-cgraph.h" diff -Nrcpad gcc-4.8.2/gcc/cgraph.h gcc-4.8.3/gcc/cgraph.h *** gcc-4.8.2/gcc/cgraph.h Thu Jan 17 11:43:14 2013 --- gcc-4.8.3/gcc/cgraph.h Tue Oct 29 14:32:13 2013 *************** struct cgraph_indirect_call_info *cgraph *** 575,580 **** --- 575,581 ---- struct cgraph_node * cgraph_create_node (tree); struct cgraph_node * cgraph_create_empty_node (void); struct cgraph_node * cgraph_get_create_node (tree); + struct cgraph_node * cgraph_get_create_real_symbol_node (tree); struct cgraph_node * cgraph_same_body_alias (struct cgraph_node *, tree, tree); struct cgraph_node * cgraph_add_thunk (struct cgraph_node *, tree, tree, bool, HOST_WIDE_INT, HOST_WIDE_INT, tree, tree); diff -Nrcpad gcc-4.8.2/gcc/cgraphbuild.c gcc-4.8.3/gcc/cgraphbuild.c *** gcc-4.8.2/gcc/cgraphbuild.c Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/cgraphbuild.c Tue Jan 7 16:49:22 2014 *************** record_reference (tree *tp, int *walk_su *** 73,79 **** decl = get_base_var (*tp); if (TREE_CODE (decl) == FUNCTION_DECL) { ! struct cgraph_node *node = cgraph_get_create_node (decl); if (!ctx->only_vars) cgraph_mark_address_taken_node (node); ipa_record_reference ((symtab_node)ctx->varpool_node, --- 73,79 ---- decl = get_base_var (*tp); if (TREE_CODE (decl) == FUNCTION_DECL) { ! struct cgraph_node *node = cgraph_get_create_real_symbol_node (decl); if (!ctx->only_vars) cgraph_mark_address_taken_node (node); ipa_record_reference ((symtab_node)ctx->varpool_node, *************** record_eh_tables (struct cgraph_node *no *** 143,149 **** { struct cgraph_node *per_node; ! per_node = cgraph_get_create_node (DECL_FUNCTION_PERSONALITY (node->symbol.decl)); ipa_record_reference ((symtab_node)node, (symtab_node)per_node, IPA_REF_ADDR, NULL); cgraph_mark_address_taken_node (per_node); } --- 143,149 ---- { struct cgraph_node *per_node; ! per_node = cgraph_get_create_real_symbol_node (DECL_FUNCTION_PERSONALITY (node->symbol.decl)); ipa_record_reference ((symtab_node)node, (symtab_node)per_node, IPA_REF_ADDR, NULL); cgraph_mark_address_taken_node (per_node); } *************** compute_call_stmt_bb_frequency (tree dec *** 218,229 **** /* Mark address taken in STMT. */ static bool ! mark_address (gimple stmt, tree addr, void *data) { addr = get_base_address (addr); if (TREE_CODE (addr) == FUNCTION_DECL) { ! struct cgraph_node *node = cgraph_get_create_node (addr); cgraph_mark_address_taken_node (node); ipa_record_reference ((symtab_node)data, (symtab_node)node, --- 218,229 ---- /* Mark address taken in STMT. */ static bool ! mark_address (gimple stmt, tree addr, tree, void *data) { addr = get_base_address (addr); if (TREE_CODE (addr) == FUNCTION_DECL) { ! struct cgraph_node *node = cgraph_get_create_real_symbol_node (addr); cgraph_mark_address_taken_node (node); ipa_record_reference ((symtab_node)data, (symtab_node)node, *************** mark_address (gimple stmt, tree addr, vo *** 245,258 **** /* Mark load of T. */ static bool ! mark_load (gimple stmt, tree t, void *data) { t = get_base_address (t); if (t && TREE_CODE (t) == FUNCTION_DECL) { /* ??? This can happen on platforms with descriptors when these are directly manipulated in the code. Pretend that it's an address. */ ! struct cgraph_node *node = cgraph_get_create_node (t); cgraph_mark_address_taken_node (node); ipa_record_reference ((symtab_node)data, (symtab_node)node, --- 245,258 ---- /* Mark load of T. */ static bool ! mark_load (gimple stmt, tree t, tree, void *data) { t = get_base_address (t); if (t && TREE_CODE (t) == FUNCTION_DECL) { /* ??? This can happen on platforms with descriptors when these are directly manipulated in the code. Pretend that it's an address. */ ! struct cgraph_node *node = cgraph_get_create_real_symbol_node (t); cgraph_mark_address_taken_node (node); ipa_record_reference ((symtab_node)data, (symtab_node)node, *************** mark_load (gimple stmt, tree t, void *da *** 273,279 **** /* Mark store of T. */ static bool ! mark_store (gimple stmt, tree t, void *data) { t = get_base_address (t); if (t && TREE_CODE (t) == VAR_DECL --- 273,279 ---- /* Mark store of T. */ static bool ! mark_store (gimple stmt, tree t, tree, void *data) { t = get_base_address (t); if (t && TREE_CODE (t) == VAR_DECL *************** build_cgraph_edges (void) *** 330,336 **** { tree fn = gimple_omp_parallel_child_fn (stmt); ipa_record_reference ((symtab_node)node, ! (symtab_node)cgraph_get_create_node (fn), IPA_REF_ADDR, stmt); } if (gimple_code (stmt) == GIMPLE_OMP_TASK) --- 330,336 ---- { tree fn = gimple_omp_parallel_child_fn (stmt); ipa_record_reference ((symtab_node)node, ! (symtab_node)cgraph_get_create_real_symbol_node (fn), IPA_REF_ADDR, stmt); } if (gimple_code (stmt) == GIMPLE_OMP_TASK) *************** build_cgraph_edges (void) *** 338,349 **** tree fn = gimple_omp_task_child_fn (stmt); if (fn) ipa_record_reference ((symtab_node)node, ! (symtab_node) cgraph_get_create_node (fn), IPA_REF_ADDR, stmt); fn = gimple_omp_task_copy_fn (stmt); if (fn) ipa_record_reference ((symtab_node)node, ! (symtab_node)cgraph_get_create_node (fn), IPA_REF_ADDR, stmt); } } --- 338,349 ---- tree fn = gimple_omp_task_child_fn (stmt); if (fn) ipa_record_reference ((symtab_node)node, ! (symtab_node) cgraph_get_create_real_symbol_node (fn), IPA_REF_ADDR, stmt); fn = gimple_omp_task_copy_fn (stmt); if (fn) ipa_record_reference ((symtab_node)node, ! (symtab_node)cgraph_get_create_real_symbol_node (fn), IPA_REF_ADDR, stmt); } } diff -Nrcpad gcc-4.8.2/gcc/combine.c gcc-4.8.3/gcc/combine.c *** gcc-4.8.2/gcc/combine.c Fri May 3 13:19:51 2013 --- gcc-4.8.3/gcc/combine.c Wed Feb 12 10:17:08 2014 *************** try_combine (rtx i3, rtx i2, rtx i1, rtx *** 3884,3898 **** PATTERN (undobuf.other_insn) = other_pat; ! /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they ! are still valid. Then add any non-duplicate notes added by ! recog_for_combine. */ for (note = REG_NOTES (undobuf.other_insn); note; note = next) { next = XEXP (note, 1); ! if (REG_NOTE_KIND (note) == REG_UNUSED ! && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) remove_note (undobuf.other_insn, note); } --- 3884,3902 ---- PATTERN (undobuf.other_insn) = other_pat; ! /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED, ! ensure that they are still valid. Then add any non-duplicate ! notes added by recog_for_combine. */ for (note = REG_NOTES (undobuf.other_insn); note; note = next) { next = XEXP (note, 1); ! if ((REG_NOTE_KIND (note) == REG_DEAD ! && !reg_referenced_p (XEXP (note, 0), ! PATTERN (undobuf.other_insn))) ! ||(REG_NOTE_KIND (note) == REG_UNUSED ! && !reg_set_p (XEXP (note, 0), ! PATTERN (undobuf.other_insn)))) remove_note (undobuf.other_insn, note); } *************** combine_simplify_rtx (rtx x, enum machin *** 5798,5805 **** return x; } ! /* If the code changed, return a whole new comparison. */ ! if (new_code != code) return gen_rtx_fmt_ee (new_code, mode, op0, op1); /* Otherwise, keep this operation, but maybe change its operands. --- 5802,5816 ---- return x; } ! /* If the code changed, return a whole new comparison. ! We also need to avoid using SUBST in cases where ! simplify_comparison has widened a comparison with a CONST_INT, ! since in that case the wider CONST_INT may fail the sanity ! checks in do_SUBST. */ ! if (new_code != code ! || (CONST_INT_P (op1) ! && GET_MODE (op0) != GET_MODE (XEXP (x, 0)) ! && GET_MODE (op0) != GET_MODE (XEXP (x, 1)))) return gen_rtx_fmt_ee (new_code, mode, op0, op1); /* Otherwise, keep this operation, but maybe change its operands. *************** force_to_mode (rtx x, enum machine_mode *** 7991,7997 **** if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) return x; ! /* We want to perform the operation is its present mode unless we know that the operation is valid in MODE, in which case we do the operation in MODE. */ op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) --- 8002,8008 ---- if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) return x; ! /* We want to perform the operation in its present mode unless we know that the operation is valid in MODE, in which case we do the operation in MODE. */ op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) *************** force_to_mode (rtx x, enum machine_mode *** 8427,8435 **** GET_MODE (x), GEN_INT (mask), XEXP (x, 1)); if (temp && CONST_INT_P (temp)) ! SUBST (XEXP (x, 0), ! force_to_mode (XEXP (x, 0), GET_MODE (x), ! INTVAL (temp), next_select)); } break; --- 8438,8447 ---- GET_MODE (x), GEN_INT (mask), XEXP (x, 1)); if (temp && CONST_INT_P (temp)) ! x = simplify_gen_binary (code, GET_MODE (x), ! force_to_mode (XEXP (x, 0), GET_MODE (x), ! INTVAL (temp), next_select), ! XEXP (x, 1)); } break; *************** force_to_mode (rtx x, enum machine_mode *** 8497,8510 **** /* We have no way of knowing if the IF_THEN_ELSE can itself be written in a narrower mode. We play it safe and do not do so. */ ! SUBST (XEXP (x, 1), ! gen_lowpart_or_truncate (GET_MODE (x), ! force_to_mode (XEXP (x, 1), mode, ! mask, next_select))); ! SUBST (XEXP (x, 2), ! gen_lowpart_or_truncate (GET_MODE (x), ! force_to_mode (XEXP (x, 2), mode, ! mask, next_select))); break; default: --- 8509,8524 ---- /* We have no way of knowing if the IF_THEN_ELSE can itself be written in a narrower mode. We play it safe and do not do so. */ ! op0 = gen_lowpart_or_truncate (GET_MODE (x), ! force_to_mode (XEXP (x, 1), mode, ! mask, next_select)); ! op1 = gen_lowpart_or_truncate (GET_MODE (x), ! force_to_mode (XEXP (x, 2), mode, ! mask, next_select)); ! if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2)) ! x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x), ! GET_MODE (XEXP (x, 0)), XEXP (x, 0), ! op0, op1); break; default: diff -Nrcpad gcc-4.8.2/gcc/config/aarch64/aarch64-simd-builtins.def gcc-4.8.3/gcc/config/aarch64/aarch64-simd-builtins.def *** gcc-4.8.2/gcc/config/aarch64/aarch64-simd-builtins.def Wed Jul 17 09:06:21 2013 --- gcc-4.8.3/gcc/config/aarch64/aarch64-simd-builtins.def Thu Dec 19 20:01:26 2013 *************** *** 217,224 **** BUILTIN_VSDQ_I_DI (BINOP, cmle) BUILTIN_VSDQ_I_DI (BINOP, cmlt) /* Implemented by aarch64_cm. */ ! BUILTIN_VSDQ_I_DI (BINOP, cmhs) ! BUILTIN_VSDQ_I_DI (BINOP, cmhi) BUILTIN_VSDQ_I_DI (BINOP, cmtst) /* Implemented by aarch64_. */ --- 217,224 ---- BUILTIN_VSDQ_I_DI (BINOP, cmle) BUILTIN_VSDQ_I_DI (BINOP, cmlt) /* Implemented by aarch64_cm. */ ! BUILTIN_VSDQ_I_DI (BINOP, cmgeu) ! BUILTIN_VSDQ_I_DI (BINOP, cmgtu) BUILTIN_VSDQ_I_DI (BINOP, cmtst) /* Implemented by aarch64_. */ diff -Nrcpad gcc-4.8.2/gcc/config/aarch64/aarch64-simd.md gcc-4.8.3/gcc/config/aarch64/aarch64-simd.md *** gcc-4.8.2/gcc/config/aarch64/aarch64-simd.md Wed Jul 17 09:06:21 2013 --- gcc-4.8.3/gcc/config/aarch64/aarch64-simd.md Thu Dec 19 20:01:26 2013 *************** *** 21,27 **** ; Main data types used by the insntructions ! (define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,HI,QI" (const_string "unknown")) --- 21,27 ---- ; Main data types used by the insntructions ! (define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,SF,HI,QI" (const_string "unknown")) *************** *** 1548,1559 **** case LTU: case GEU: ! emit_insn (gen_aarch64_cmhs (mask, operands[4], operands[5])); break; case LEU: case GTU: ! emit_insn (gen_aarch64_cmhi (mask, operands[4], operands[5])); break; case NE: --- 1548,1559 ---- case LTU: case GEU: ! emit_insn (gen_aarch64_cmgeu (mask, operands[4], operands[5])); break; case LEU: case GTU: ! emit_insn (gen_aarch64_cmgtu (mask, operands[4], operands[5])); break; case NE: *************** *** 3034,3081 **** ) ! ;; cm(eq|ge|le|lt|gt) ! (define_insn "aarch64_cm" [(set (match_operand: 0 "register_operand" "=w,w") ! (unspec: ! [(match_operand:VSDQ_I_DI 1 "register_operand" "w,w") ! (match_operand:VSDQ_I_DI 2 "aarch64_simd_reg_or_zero" "w,Z")] ! VCMP_S))] "TARGET_SIMD" "@ ! cm\t%0, %1, %2 ! cm\t%0, %1, #0" [(set_attr "simd_type" "simd_cmp") (set_attr "simd_mode" "")] ) ! ;; cm(hs|hi|tst) ! (define_insn "aarch64_cm" [(set (match_operand: 0 "register_operand" "=w") ! (unspec: ! [(match_operand:VSDQ_I_DI 1 "register_operand" "w") ! (match_operand:VSDQ_I_DI 2 "register_operand" "w")] ! VCMP_U))] "TARGET_SIMD" ! "cm\t%0, %1, %2" [(set_attr "simd_type" "simd_cmp") (set_attr "simd_mode" "")] ) ! ;; fcm(eq|ge|le|lt|gt) ! (define_insn "aarch64_cm" [(set (match_operand: 0 "register_operand" "=w,w") ! (unspec: ! [(match_operand:VDQF 1 "register_operand" "w,w") ! (match_operand:VDQF 2 "aarch64_simd_reg_or_zero" "w,Dz")] ! VCMP_S))] "TARGET_SIMD" "@ ! fcm\t%0, %1, %2 ! fcm\t%0, %1, 0" [(set_attr "simd_type" "simd_fcmp") (set_attr "simd_mode" "")] ) --- 3034,3214 ---- ) ! ;; cm(eq|ge|gt|lt|le) ! ;; Note, we have constraints for Dz and Z as different expanders ! ;; have different ideas of what should be passed to this pattern. ! (define_insn "aarch64_cm" [(set (match_operand: 0 "register_operand" "=w,w") ! (neg: ! (COMPARISONS: ! (match_operand:VDQ 1 "register_operand" "w,w") ! (match_operand:VDQ 2 "aarch64_simd_reg_or_zero" "w,ZDz") ! )))] "TARGET_SIMD" "@ ! cm\t%0, %, % ! cm\t%0, %1, #0" [(set_attr "simd_type" "simd_cmp") (set_attr "simd_mode" "")] ) ! (define_insn_and_split "aarch64_cmdi" ! [(set (match_operand:DI 0 "register_operand" "=w,w,r") ! (neg:DI ! (COMPARISONS:DI ! (match_operand:DI 1 "register_operand" "w,w,r") ! (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,ZDz,r") ! )))] ! "TARGET_SIMD" ! "@ ! cm\t%d0, %d, %d ! cm\t%d0, %d1, #0 ! #" ! "reload_completed ! /* We need to prevent the split from ! happening in the 'w' constraint cases. */ ! && GP_REGNUM_P (REGNO (operands[0])) ! && GP_REGNUM_P (REGNO (operands[1]))" ! [(set (reg:CC CC_REGNUM) ! (compare:CC ! (match_dup 1) ! (match_dup 2))) ! (set (match_dup 0) ! (neg:DI ! (COMPARISONS:DI ! (match_operand 3 "cc_register" "") ! (const_int 0))))] ! { ! enum machine_mode mode = SELECT_CC_MODE (, operands[1], operands[2]); ! rtx cc_reg = aarch64_gen_compare_reg (, operands[1], operands[2]); ! rtx comparison = gen_rtx_ (mode, operands[1], operands[2]); ! emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); ! DONE; ! } ! [(set_attr "simd_type" "simd_cmp") ! (set_attr "simd_mode" "DI")] ! ) ! ;; cm(hs|hi) ! ! (define_insn "aarch64_cm" [(set (match_operand: 0 "register_operand" "=w") ! (neg: ! (UCOMPARISONS: ! (match_operand:VDQ 1 "register_operand" "w") ! (match_operand:VDQ 2 "register_operand" "w") ! )))] "TARGET_SIMD" ! "cm\t%0, %, %" [(set_attr "simd_type" "simd_cmp") (set_attr "simd_mode" "")] ) ! (define_insn_and_split "aarch64_cmdi" ! [(set (match_operand:DI 0 "register_operand" "=w,r") ! (neg:DI ! (UCOMPARISONS:DI ! (match_operand:DI 1 "register_operand" "w,r") ! (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,r") ! )))] ! "TARGET_SIMD" ! "@ ! cm\t%d0, %d, %d ! #" ! "reload_completed ! /* We need to prevent the split from ! happening in the 'w' constraint cases. */ ! && GP_REGNUM_P (REGNO (operands[0])) ! && GP_REGNUM_P (REGNO (operands[1]))" ! [(set (reg:CC CC_REGNUM) ! (compare:CC ! (match_dup 1) ! (match_dup 2))) ! (set (match_dup 0) ! (neg:DI ! (UCOMPARISONS:DI ! (match_operand 3 "cc_register" "") ! (const_int 0))))] ! { ! enum machine_mode mode = SELECT_CC_MODE (, operands[1], operands[2]); ! rtx cc_reg = aarch64_gen_compare_reg (, operands[1], operands[2]); ! rtx comparison = gen_rtx_ (mode, operands[1], operands[2]); ! emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); ! DONE; ! } ! [(set_attr "simd_type" "simd_cmp") ! (set_attr "simd_mode" "DI")] ! ) ! ;; cmtst ! ! (define_insn "aarch64_cmtst" ! [(set (match_operand: 0 "register_operand" "=w") ! (neg: ! (ne: ! (and:VDQ ! (match_operand:VDQ 1 "register_operand" "w") ! (match_operand:VDQ 2 "register_operand" "w")) ! (vec_duplicate: (const_int 0)))))] ! "TARGET_SIMD" ! "cmtst\t%0, %1, %2" ! [(set_attr "simd_type" "simd_cmp") ! (set_attr "simd_mode" "")] ! ) ! ! (define_insn_and_split "aarch64_cmtstdi" ! [(set (match_operand:DI 0 "register_operand" "=w,r") ! (neg:DI ! (ne:DI ! (and:DI ! (match_operand:DI 1 "register_operand" "w,r") ! (match_operand:DI 2 "register_operand" "w,r")) ! (const_int 0))))] ! "TARGET_SIMD" ! "@ ! cmtst\t%d0, %d1, %d2 ! #" ! "reload_completed ! /* We need to prevent the split from ! happening in the 'w' constraint cases. */ ! && GP_REGNUM_P (REGNO (operands[0])) ! && GP_REGNUM_P (REGNO (operands[1]))" ! [(set (reg:CC_NZ CC_REGNUM) ! (compare:CC_NZ ! (and:DI (match_dup 1) ! (match_dup 2)) ! (const_int 0))) ! (set (match_dup 0) ! (neg:DI ! (ne:DI ! (match_operand 3 "cc_register" "") ! (const_int 0))))] ! { ! rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]); ! enum machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx); ! rtx cc_reg = aarch64_gen_compare_reg (NE, and_tree, const0_rtx); ! rtx comparison = gen_rtx_NE (mode, and_tree, const0_rtx); ! emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); ! DONE; ! } ! [(set_attr "simd_type" "simd_cmp") ! (set_attr "simd_mode" "DI")] ! ) ! ! ;; fcm(eq|ge|gt|le|lt) ! ! (define_insn "aarch64_cm" [(set (match_operand: 0 "register_operand" "=w,w") ! (neg: ! (COMPARISONS: ! (match_operand:VALLF 1 "register_operand" "w,w") ! (match_operand:VALLF 2 "aarch64_simd_reg_or_zero" "w,YDz") ! )))] "TARGET_SIMD" "@ ! fcm\t%0, %, % ! fcm\t%0, %1, 0" [(set_attr "simd_type" "simd_fcmp") (set_attr "simd_mode" "")] ) diff -Nrcpad gcc-4.8.2/gcc/config/aarch64/aarch64.c gcc-4.8.3/gcc/config/aarch64/aarch64.c *** gcc-4.8.2/gcc/config/aarch64/aarch64.c Mon Jun 3 15:33:09 2013 --- gcc-4.8.3/gcc/config/aarch64/aarch64.c Fri Apr 18 15:55:35 2014 *************** aarch64_build_constant (int regnum, HOST *** 2274,2280 **** if (ncount < zcount) { emit_move_insn (gen_rtx_REG (Pmode, regnum), ! GEN_INT ((~val) & 0xffff)); tval = 0xffff; } else --- 2274,2280 ---- if (ncount < zcount) { emit_move_insn (gen_rtx_REG (Pmode, regnum), ! GEN_INT (val | ~(HOST_WIDE_INT) 0xffff)); tval = 0xffff; } else *************** aarch64_address_cost (rtx x ATTRIBUTE_UN *** 4568,4576 **** } static int ! aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, ! reg_class_t from, reg_class_t to) { const struct cpu_regmove_cost *regmove_cost = aarch64_tune_params->regmove_cost; --- 4568,4578 ---- } static int ! aarch64_register_move_cost (enum machine_mode mode, ! reg_class_t from_i, reg_class_t to_i) { + enum reg_class from = (enum reg_class) from_i; + enum reg_class to = (enum reg_class) to_i; const struct cpu_regmove_cost *regmove_cost = aarch64_tune_params->regmove_cost; *************** aarch64_register_move_cost (enum machine *** 4586,4593 **** secondary reload. A general register is used as a scratch to move the upper DI value and the lower DI value is moved directly, hence the cost is the sum of three moves. */ ! ! if (! TARGET_SIMD && GET_MODE_SIZE (from) == 128 && GET_MODE_SIZE (to) == 128) return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP; return regmove_cost->FP2FP; --- 4588,4594 ---- secondary reload. A general register is used as a scratch to move the upper DI value and the lower DI value is moved directly, hence the cost is the sum of three moves. */ ! if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 128) return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP; return regmove_cost->FP2FP; diff -Nrcpad gcc-4.8.2/gcc/config/aarch64/aarch64.h gcc-4.8.3/gcc/config/aarch64/aarch64.h *** gcc-4.8.2/gcc/config/aarch64/aarch64.h Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/aarch64/aarch64.h Fri May 2 09:07:06 2014 *************** *** 73,81 **** #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) /* AdvSIMD is supported in the default configuration, unless disabled by ! -mgeneral-regs-only. */ ! #define TARGET_SIMD !TARGET_GENERAL_REGS_ONLY ! #define TARGET_FLOAT !TARGET_GENERAL_REGS_ONLY #define UNITS_PER_WORD 8 --- 73,81 ---- #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) /* AdvSIMD is supported in the default configuration, unless disabled by ! -mgeneral-regs-only or the +nosimd extension. */ ! #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) ! #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) #define UNITS_PER_WORD 8 diff -Nrcpad gcc-4.8.2/gcc/config/aarch64/aarch64.md gcc-4.8.3/gcc/config/aarch64/aarch64.md *** gcc-4.8.2/gcc/config/aarch64/aarch64.md Fri Oct 4 14:57:04 2013 --- gcc-4.8.3/gcc/config/aarch64/aarch64.md Thu Dec 19 20:01:26 2013 *************** *** 2211,2217 **** (set_attr "mode" "SI")] ) ! (define_insn "*cstore_neg" [(set (match_operand:ALLI 0 "register_operand" "=r") (neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)])))] --- 2211,2217 ---- (set_attr "mode" "SI")] ) ! (define_insn "cstore_neg" [(set (match_operand:ALLI 0 "register_operand" "=r") (neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)])))] diff -Nrcpad gcc-4.8.2/gcc/config/aarch64/arm_neon.h gcc-4.8.3/gcc/config/aarch64/arm_neon.h *** gcc-4.8.2/gcc/config/aarch64/arm_neon.h Sat Oct 12 08:23:31 2013 --- gcc-4.8.3/gcc/config/aarch64/arm_neon.h Thu Dec 19 20:01:26 2013 *************** vcge_s64 (int64x1_t __a, int64x1_t __b) *** 19551,19578 **** __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vcge_u8 (uint8x8_t __a, uint8x8_t __b) { ! return (uint8x8_t) __builtin_aarch64_cmhsv8qi ((int8x8_t) __a, (int8x8_t) __b); } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) vcge_u16 (uint16x4_t __a, uint16x4_t __b) { ! return (uint16x4_t) __builtin_aarch64_cmhsv4hi ((int16x4_t) __a, (int16x4_t) __b); } __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcge_u32 (uint32x2_t __a, uint32x2_t __b) { ! return (uint32x2_t) __builtin_aarch64_cmhsv2si ((int32x2_t) __a, (int32x2_t) __b); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcge_u64 (uint64x1_t __a, uint64x1_t __b) { ! return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __a, (int64x1_t) __b); } --- 19551,19578 ---- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vcge_u8 (uint8x8_t __a, uint8x8_t __b) { ! return (uint8x8_t) __builtin_aarch64_cmgeuv8qi ((int8x8_t) __a, (int8x8_t) __b); } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) vcge_u16 (uint16x4_t __a, uint16x4_t __b) { ! return (uint16x4_t) __builtin_aarch64_cmgeuv4hi ((int16x4_t) __a, (int16x4_t) __b); } __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcge_u32 (uint32x2_t __a, uint32x2_t __b) { ! return (uint32x2_t) __builtin_aarch64_cmgeuv2si ((int32x2_t) __a, (int32x2_t) __b); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcge_u64 (uint64x1_t __a, uint64x1_t __b) { ! return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __a, (int64x1_t) __b); } *************** vcgeq_s64 (int64x2_t __a, int64x2_t __b) *** 19603,19630 **** __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcgeq_u8 (uint8x16_t __a, uint8x16_t __b) { ! return (uint8x16_t) __builtin_aarch64_cmhsv16qi ((int8x16_t) __a, (int8x16_t) __b); } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) vcgeq_u16 (uint16x8_t __a, uint16x8_t __b) { ! return (uint16x8_t) __builtin_aarch64_cmhsv8hi ((int16x8_t) __a, (int16x8_t) __b); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcgeq_u32 (uint32x4_t __a, uint32x4_t __b) { ! return (uint32x4_t) __builtin_aarch64_cmhsv4si ((int32x4_t) __a, (int32x4_t) __b); } __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcgeq_u64 (uint64x2_t __a, uint64x2_t __b) { ! return (uint64x2_t) __builtin_aarch64_cmhsv2di ((int64x2_t) __a, (int64x2_t) __b); } --- 19603,19630 ---- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcgeq_u8 (uint8x16_t __a, uint8x16_t __b) { ! return (uint8x16_t) __builtin_aarch64_cmgeuv16qi ((int8x16_t) __a, (int8x16_t) __b); } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) vcgeq_u16 (uint16x8_t __a, uint16x8_t __b) { ! return (uint16x8_t) __builtin_aarch64_cmgeuv8hi ((int16x8_t) __a, (int16x8_t) __b); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcgeq_u32 (uint32x4_t __a, uint32x4_t __b) { ! return (uint32x4_t) __builtin_aarch64_cmgeuv4si ((int32x4_t) __a, (int32x4_t) __b); } __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcgeq_u64 (uint64x2_t __a, uint64x2_t __b) { ! return (uint64x2_t) __builtin_aarch64_cmgeuv2di ((int64x2_t) __a, (int64x2_t) __b); } *************** vcged_s64 (int64x1_t __a, int64x1_t __b) *** 19637,19643 **** __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcged_u64 (uint64x1_t __a, uint64x1_t __b) { ! return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __a, (int64x1_t) __b); } --- 19637,19643 ---- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcged_u64 (uint64x1_t __a, uint64x1_t __b) { ! return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __a, (int64x1_t) __b); } *************** vcgt_s64 (int64x1_t __a, int64x1_t __b) *** 19676,19703 **** __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vcgt_u8 (uint8x8_t __a, uint8x8_t __b) { ! return (uint8x8_t) __builtin_aarch64_cmhiv8qi ((int8x8_t) __a, (int8x8_t) __b); } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) vcgt_u16 (uint16x4_t __a, uint16x4_t __b) { ! return (uint16x4_t) __builtin_aarch64_cmhiv4hi ((int16x4_t) __a, (int16x4_t) __b); } __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcgt_u32 (uint32x2_t __a, uint32x2_t __b) { ! return (uint32x2_t) __builtin_aarch64_cmhiv2si ((int32x2_t) __a, (int32x2_t) __b); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcgt_u64 (uint64x1_t __a, uint64x1_t __b) { ! return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __a, (int64x1_t) __b); } --- 19676,19703 ---- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vcgt_u8 (uint8x8_t __a, uint8x8_t __b) { ! return (uint8x8_t) __builtin_aarch64_cmgtuv8qi ((int8x8_t) __a, (int8x8_t) __b); } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) vcgt_u16 (uint16x4_t __a, uint16x4_t __b) { ! return (uint16x4_t) __builtin_aarch64_cmgtuv4hi ((int16x4_t) __a, (int16x4_t) __b); } __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcgt_u32 (uint32x2_t __a, uint32x2_t __b) { ! return (uint32x2_t) __builtin_aarch64_cmgtuv2si ((int32x2_t) __a, (int32x2_t) __b); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcgt_u64 (uint64x1_t __a, uint64x1_t __b) { ! return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __a, (int64x1_t) __b); } *************** vcgtq_s64 (int64x2_t __a, int64x2_t __b) *** 19728,19755 **** __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcgtq_u8 (uint8x16_t __a, uint8x16_t __b) { ! return (uint8x16_t) __builtin_aarch64_cmhiv16qi ((int8x16_t) __a, (int8x16_t) __b); } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) vcgtq_u16 (uint16x8_t __a, uint16x8_t __b) { ! return (uint16x8_t) __builtin_aarch64_cmhiv8hi ((int16x8_t) __a, (int16x8_t) __b); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcgtq_u32 (uint32x4_t __a, uint32x4_t __b) { ! return (uint32x4_t) __builtin_aarch64_cmhiv4si ((int32x4_t) __a, (int32x4_t) __b); } __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcgtq_u64 (uint64x2_t __a, uint64x2_t __b) { ! return (uint64x2_t) __builtin_aarch64_cmhiv2di ((int64x2_t) __a, (int64x2_t) __b); } --- 19728,19755 ---- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcgtq_u8 (uint8x16_t __a, uint8x16_t __b) { ! return (uint8x16_t) __builtin_aarch64_cmgtuv16qi ((int8x16_t) __a, (int8x16_t) __b); } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) vcgtq_u16 (uint16x8_t __a, uint16x8_t __b) { ! return (uint16x8_t) __builtin_aarch64_cmgtuv8hi ((int16x8_t) __a, (int16x8_t) __b); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcgtq_u32 (uint32x4_t __a, uint32x4_t __b) { ! return (uint32x4_t) __builtin_aarch64_cmgtuv4si ((int32x4_t) __a, (int32x4_t) __b); } __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcgtq_u64 (uint64x2_t __a, uint64x2_t __b) { ! return (uint64x2_t) __builtin_aarch64_cmgtuv2di ((int64x2_t) __a, (int64x2_t) __b); } *************** vcgtd_s64 (int64x1_t __a, int64x1_t __b) *** 19762,19768 **** __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcgtd_u64 (uint64x1_t __a, uint64x1_t __b) { ! return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __a, (int64x1_t) __b); } --- 19762,19768 ---- __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcgtd_u64 (uint64x1_t __a, uint64x1_t __b) { ! return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __a, (int64x1_t) __b); } *************** vcle_s64 (int64x1_t __a, int64x1_t __b) *** 19801,19828 **** __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vcle_u8 (uint8x8_t __a, uint8x8_t __b) { ! return (uint8x8_t) __builtin_aarch64_cmhsv8qi ((int8x8_t) __b, (int8x8_t) __a); } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) vcle_u16 (uint16x4_t __a, uint16x4_t __b) { ! return (uint16x4_t) __builtin_aarch64_cmhsv4hi ((int16x4_t) __b, (int16x4_t) __a); } __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcle_u32 (uint32x2_t __a, uint32x2_t __b) { ! return (uint32x2_t) __builtin_aarch64_cmhsv2si ((int32x2_t) __b, (int32x2_t) __a); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcle_u64 (uint64x1_t __a, uint64x1_t __b) { ! return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __b, (int64x1_t) __a); } --- 19801,19828 ---- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vcle_u8 (uint8x8_t __a, uint8x8_t __b) { ! return (uint8x8_t) __builtin_aarch64_cmgeuv8qi ((int8x8_t) __b, (int8x8_t) __a); } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) vcle_u16 (uint16x4_t __a, uint16x4_t __b) { ! return (uint16x4_t) __builtin_aarch64_cmgeuv4hi ((int16x4_t) __b, (int16x4_t) __a); } __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcle_u32 (uint32x2_t __a, uint32x2_t __b) { ! return (uint32x2_t) __builtin_aarch64_cmgeuv2si ((int32x2_t) __b, (int32x2_t) __a); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcle_u64 (uint64x1_t __a, uint64x1_t __b) { ! return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __b, (int64x1_t) __a); } *************** vcleq_s64 (int64x2_t __a, int64x2_t __b) *** 19853,19880 **** __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcleq_u8 (uint8x16_t __a, uint8x16_t __b) { ! return (uint8x16_t) __builtin_aarch64_cmhsv16qi ((int8x16_t) __b, (int8x16_t) __a); } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) vcleq_u16 (uint16x8_t __a, uint16x8_t __b) { ! return (uint16x8_t) __builtin_aarch64_cmhsv8hi ((int16x8_t) __b, (int16x8_t) __a); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcleq_u32 (uint32x4_t __a, uint32x4_t __b) { ! return (uint32x4_t) __builtin_aarch64_cmhsv4si ((int32x4_t) __b, (int32x4_t) __a); } __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcleq_u64 (uint64x2_t __a, uint64x2_t __b) { ! return (uint64x2_t) __builtin_aarch64_cmhsv2di ((int64x2_t) __b, (int64x2_t) __a); } --- 19853,19880 ---- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcleq_u8 (uint8x16_t __a, uint8x16_t __b) { ! return (uint8x16_t) __builtin_aarch64_cmgeuv16qi ((int8x16_t) __b, (int8x16_t) __a); } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) vcleq_u16 (uint16x8_t __a, uint16x8_t __b) { ! return (uint16x8_t) __builtin_aarch64_cmgeuv8hi ((int16x8_t) __b, (int16x8_t) __a); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcleq_u32 (uint32x4_t __a, uint32x4_t __b) { ! return (uint32x4_t) __builtin_aarch64_cmgeuv4si ((int32x4_t) __b, (int32x4_t) __a); } __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcleq_u64 (uint64x2_t __a, uint64x2_t __b) { ! return (uint64x2_t) __builtin_aarch64_cmgeuv2di ((int64x2_t) __b, (int64x2_t) __a); } *************** vclt_s64 (int64x1_t __a, int64x1_t __b) *** 19919,19946 **** __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vclt_u8 (uint8x8_t __a, uint8x8_t __b) { ! return (uint8x8_t) __builtin_aarch64_cmhiv8qi ((int8x8_t) __b, (int8x8_t) __a); } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) vclt_u16 (uint16x4_t __a, uint16x4_t __b) { ! return (uint16x4_t) __builtin_aarch64_cmhiv4hi ((int16x4_t) __b, (int16x4_t) __a); } __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vclt_u32 (uint32x2_t __a, uint32x2_t __b) { ! return (uint32x2_t) __builtin_aarch64_cmhiv2si ((int32x2_t) __b, (int32x2_t) __a); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vclt_u64 (uint64x1_t __a, uint64x1_t __b) { ! return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __b, (int64x1_t) __a); } --- 19919,19946 ---- __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vclt_u8 (uint8x8_t __a, uint8x8_t __b) { ! return (uint8x8_t) __builtin_aarch64_cmgtuv8qi ((int8x8_t) __b, (int8x8_t) __a); } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) vclt_u16 (uint16x4_t __a, uint16x4_t __b) { ! return (uint16x4_t) __builtin_aarch64_cmgtuv4hi ((int16x4_t) __b, (int16x4_t) __a); } __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vclt_u32 (uint32x2_t __a, uint32x2_t __b) { ! return (uint32x2_t) __builtin_aarch64_cmgtuv2si ((int32x2_t) __b, (int32x2_t) __a); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vclt_u64 (uint64x1_t __a, uint64x1_t __b) { ! return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __b, (int64x1_t) __a); } *************** vcltq_s64 (int64x2_t __a, int64x2_t __b) *** 19971,19998 **** __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcltq_u8 (uint8x16_t __a, uint8x16_t __b) { ! return (uint8x16_t) __builtin_aarch64_cmhiv16qi ((int8x16_t) __b, (int8x16_t) __a); } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) vcltq_u16 (uint16x8_t __a, uint16x8_t __b) { ! return (uint16x8_t) __builtin_aarch64_cmhiv8hi ((int16x8_t) __b, (int16x8_t) __a); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcltq_u32 (uint32x4_t __a, uint32x4_t __b) { ! return (uint32x4_t) __builtin_aarch64_cmhiv4si ((int32x4_t) __b, (int32x4_t) __a); } __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcltq_u64 (uint64x2_t __a, uint64x2_t __b) { ! return (uint64x2_t) __builtin_aarch64_cmhiv2di ((int64x2_t) __b, (int64x2_t) __a); } --- 19971,19998 ---- __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcltq_u8 (uint8x16_t __a, uint8x16_t __b) { ! return (uint8x16_t) __builtin_aarch64_cmgtuv16qi ((int8x16_t) __b, (int8x16_t) __a); } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) vcltq_u16 (uint16x8_t __a, uint16x8_t __b) { ! return (uint16x8_t) __builtin_aarch64_cmgtuv8hi ((int16x8_t) __b, (int16x8_t) __a); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcltq_u32 (uint32x4_t __a, uint32x4_t __b) { ! return (uint32x4_t) __builtin_aarch64_cmgtuv4si ((int32x4_t) __b, (int32x4_t) __a); } __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcltq_u64 (uint64x2_t __a, uint64x2_t __b) { ! return (uint64x2_t) __builtin_aarch64_cmgtuv2di ((int64x2_t) __b, (int64x2_t) __a); } diff -Nrcpad gcc-4.8.2/gcc/config/aarch64/iterators.md gcc-4.8.3/gcc/config/aarch64/iterators.md *** gcc-4.8.2/gcc/config/aarch64/iterators.md Fri Jan 25 11:35:03 2013 --- gcc-4.8.3/gcc/config/aarch64/iterators.md Thu Dec 19 20:01:26 2013 *************** *** 83,88 **** --- 83,91 ---- ;; Vector Float modes. (define_mode_iterator VDQF [V2SF V4SF V2DF]) + ;; All Float modes. + (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) + ;; Vector Float modes with 2 elements. (define_mode_iterator V2F [V2SF V2DF]) *************** *** 213,225 **** UNSPEC_URSHL ; Used in aarch64-simd.md. UNSPEC_SQRSHL ; Used in aarch64-simd.md. UNSPEC_UQRSHL ; Used in aarch64-simd.md. - UNSPEC_CMEQ ; Used in aarch64-simd.md. - UNSPEC_CMLE ; Used in aarch64-simd.md. - UNSPEC_CMLT ; Used in aarch64-simd.md. - UNSPEC_CMGE ; Used in aarch64-simd.md. - UNSPEC_CMGT ; Used in aarch64-simd.md. - UNSPEC_CMHS ; Used in aarch64-simd.md. - UNSPEC_CMHI ; Used in aarch64-simd.md. UNSPEC_SSLI ; Used in aarch64-simd.md. UNSPEC_USLI ; Used in aarch64-simd.md. UNSPEC_SSRI ; Used in aarch64-simd.md. --- 216,221 ---- *************** *** 227,233 **** UNSPEC_SSHLL ; Used in aarch64-simd.md. UNSPEC_USHLL ; Used in aarch64-simd.md. UNSPEC_ADDP ; Used in aarch64-simd.md. - UNSPEC_CMTST ; Used in aarch64-simd.md. UNSPEC_FMAX ; Used in aarch64-simd.md. UNSPEC_FMIN ; Used in aarch64-simd.md. UNSPEC_BSL ; Used in aarch64-simd.md. --- 223,228 ---- *************** *** 251,256 **** --- 246,252 ---- ;; For scalar usage of vector/FP registers (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") + (SF "s") (DF "d") (V8QI "") (V16QI "") (V4HI "") (V8HI "") (V2SI "") (V4SI "") *************** *** 305,311 **** (V4SF ".4s") (V2DF ".2d") (DI "") (SI "") (HI "") (QI "") ! (TI "")]) ;; Register suffix narrowed modes for VQN. (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") --- 301,308 ---- (V4SF ".4s") (V2DF ".2d") (DI "") (SI "") (HI "") (QI "") ! (TI "") (SF "") ! (DF "")]) ;; Register suffix narrowed modes for VQN. (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") *************** *** 444,450 **** (V2SI "V2SI") (V4SI "V4SI") (DI "DI") (V2DI "V2DI") (V2SF "V2SI") (V4SF "V4SI") ! (V2DF "V2DI")]) ;; Lower case mode of results of comparison operations. (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") --- 441,448 ---- (V2SI "V2SI") (V4SI "V4SI") (DI "DI") (V2DI "V2DI") (V2SF "V2SI") (V4SF "V4SI") ! (V2DF "V2DI") (DF "DI") ! (SF "SI")]) ;; Lower case mode of results of comparison operations. (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") *************** *** 452,458 **** (V2SI "v2si") (V4SI "v4si") (DI "di") (V2DI "v2di") (V2SF "v2si") (V4SF "v4si") ! (V2DF "v2di")]) ;; Vm for lane instructions is restricted to FP_LO_REGS. (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") --- 450,457 ---- (V2SI "v2si") (V4SI "v4si") (DI "di") (V2DI "v2di") (V2SF "v2si") (V4SF "v4si") ! (V2DF "v2di") (DF "di") ! (SF "si")]) ;; Vm for lane instructions is restricted to FP_LO_REGS. (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") *************** *** 543,548 **** --- 542,553 ---- ;; Code iterator for signed variants of vector saturating binary ops. (define_code_iterator SBINQOPS [ss_plus ss_minus]) + ;; Comparison operators for CM. + (define_code_iterator COMPARISONS [lt le eq ge gt]) + + ;; Unsigned comparison operators. + (define_code_iterator UCOMPARISONS [ltu leu geu gtu]) + ;; ------------------------------------------------------------------- ;; Code Attributes ;; ------------------------------------------------------------------- *************** *** 571,577 **** (eq "eq") (ne "ne") (lt "lt") ! (ge "ge")]) ;; Optab prefix for sign/zero-extending operations (define_code_attr su_optab [(sign_extend "") (zero_extend "u") --- 576,603 ---- (eq "eq") (ne "ne") (lt "lt") ! (ge "ge") ! (le "le") ! (gt "gt") ! (ltu "ltu") ! (leu "leu") ! (geu "geu") ! (gtu "gtu")]) ! ! ;; For comparison operators we use the FCM* and CM* instructions. ! ;; As there are no CMLE or CMLT instructions which act on 3 vector ! ;; operands, we must use CMGE or CMGT and swap the order of the ! ;; source operands. ! ! (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt") ! (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")]) ! (define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1") ! (ltu "2") (leu "2") (geu "1") (gtu "1")]) ! (define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2") ! (ltu "1") (leu "1") (geu "2") (gtu "2")]) ! ! (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT") ! (ltu "LTU") (leu "LEU") (geu "GEU") (gtu "GTU")]) ;; Optab prefix for sign/zero-extending operations (define_code_attr su_optab [(sign_extend "") (zero_extend "u") *************** *** 680,690 **** UNSPEC_SQSHRN UNSPEC_UQSHRN UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) - (define_int_iterator VCMP_S [UNSPEC_CMEQ UNSPEC_CMGE UNSPEC_CMGT - UNSPEC_CMLE UNSPEC_CMLT]) - - (define_int_iterator VCMP_U [UNSPEC_CMHS UNSPEC_CMHI UNSPEC_CMTST]) - (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 UNSPEC_TRN1 UNSPEC_TRN2 UNSPEC_UZP1 UNSPEC_UZP2]) --- 706,711 ---- *************** *** 768,779 **** (UNSPEC_RADDHN2 "add") (UNSPEC_RSUBHN2 "sub")]) - (define_int_attr cmp [(UNSPEC_CMGE "ge") (UNSPEC_CMGT "gt") - (UNSPEC_CMLE "le") (UNSPEC_CMLT "lt") - (UNSPEC_CMEQ "eq") - (UNSPEC_CMHS "hs") (UNSPEC_CMHI "hi") - (UNSPEC_CMTST "tst")]) - (define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1") (UNSPEC_SSRI "0") (UNSPEC_USRI "0")]) --- 789,794 ---- diff -Nrcpad gcc-4.8.2/gcc/config/aarch64/predicates.md gcc-4.8.3/gcc/config/aarch64/predicates.md *** gcc-4.8.2/gcc/config/aarch64/predicates.md Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/aarch64/predicates.md Thu Dec 19 20:01:26 2013 *************** *** 31,36 **** --- 31,41 ---- (ior (match_operand 0 "register_operand") (match_test "op == const0_rtx")))) + (define_predicate "aarch64_reg_or_fp_zero" + (and (match_code "reg,subreg,const_double") + (ior (match_operand 0 "register_operand") + (match_test "aarch64_float_const_zero_rtx_p (op)")))) + (define_predicate "aarch64_reg_zero_or_m1_or_1" (and (match_code "reg,subreg,const_int") (ior (match_operand 0 "register_operand") diff -Nrcpad gcc-4.8.2/gcc/config/arm/arm-ldmstm.ml gcc-4.8.3/gcc/config/arm/arm-ldmstm.ml *** gcc-4.8.2/gcc/config/arm/arm-ldmstm.ml Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/arm/arm-ldmstm.ml Fri Jan 17 11:48:06 2014 *************** let destreg nregs first op_type thumb = *** 67,76 **** Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")") (nregs + 1) (inout_constr op_type) (constr thumb) let write_ldm_set thumb nregs offset opnr first = let indent = " " in Printf.printf "%s" (if first then " [" else indent); ! Printf.printf "(set (match_operand:SI %d \"arm_hard_register_operand\" \"\")\n" opnr; Printf.printf "%s (mem:SI " indent; begin if offset != 0 then Printf.printf "(plus:SI " end; Printf.printf "%s" (destreg nregs first IN thumb); --- 67,79 ---- Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")") (nregs + 1) (inout_constr op_type) (constr thumb) + let reg_predicate thumb = + if thumb then "low_register_operand" else "arm_hard_general_register_operand" + let write_ldm_set thumb nregs offset opnr first = let indent = " " in Printf.printf "%s" (if first then " [" else indent); ! Printf.printf "(set (match_operand:SI %d \"%s\" \"\")\n" opnr (reg_predicate thumb); Printf.printf "%s (mem:SI " indent; begin if offset != 0 then Printf.printf "(plus:SI " end; Printf.printf "%s" (destreg nregs first IN thumb); *************** let write_stm_set thumb nregs offset opn *** 84,90 **** begin if offset != 0 then Printf.printf "(plus:SI " end; Printf.printf "%s" (destreg nregs first IN thumb); begin if offset != 0 then Printf.printf " (const_int %d))" offset end; ! Printf.printf ")\n%s (match_operand:SI %d \"arm_hard_register_operand\" \"\"))" indent opnr let write_ldm_peep_set extra_indent nregs opnr first = let indent = " " ^ extra_indent in --- 87,93 ---- begin if offset != 0 then Printf.printf "(plus:SI " end; Printf.printf "%s" (destreg nregs first IN thumb); begin if offset != 0 then Printf.printf " (const_int %d))" offset end; ! Printf.printf ")\n%s (match_operand:SI %d \"%s\" \"\"))" indent opnr (reg_predicate thumb) let write_ldm_peep_set extra_indent nregs opnr first = let indent = " " ^ extra_indent in diff -Nrcpad gcc-4.8.2/gcc/config/arm/arm.c gcc-4.8.3/gcc/config/arm/arm.c *** gcc-4.8.2/gcc/config/arm/arm.c Wed Sep 18 16:37:35 2013 --- gcc-4.8.3/gcc/config/arm/arm.c Thu Apr 10 07:45:21 2014 *************** static tree arm_gimplify_va_arg_expr (tr *** 230,236 **** static void arm_option_override (void); static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode); static bool arm_cannot_copy_insn_p (rtx); - static bool arm_tls_symbol_p (rtx x); static int arm_issue_rate (void); static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; static bool arm_output_addr_const_extra (FILE *, rtx); --- 230,235 ---- *************** require_pic_register (void) *** 5425,5431 **** if (!crtl->uses_pic_offset_table) { gcc_assert (can_create_pseudo_p ()); ! if (arm_pic_register != INVALID_REGNUM) { if (!cfun->machine->pic_reg) cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register); --- 5424,5431 ---- if (!crtl->uses_pic_offset_table) { gcc_assert (can_create_pseudo_p ()); ! if (arm_pic_register != INVALID_REGNUM ! && !(TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM)) { if (!cfun->machine->pic_reg) cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register); *************** require_pic_register (void) *** 5451,5457 **** crtl->uses_pic_offset_table = 1; start_sequence (); ! arm_load_pic_register (0UL); seq = get_insns (); end_sequence (); --- 5451,5462 ---- crtl->uses_pic_offset_table = 1; start_sequence (); ! if (TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM ! && arm_pic_register > LAST_LO_REGNUM) ! emit_move_insn (cfun->machine->pic_reg, ! gen_rtx_REG (Pmode, arm_pic_register)); ! else ! arm_load_pic_register (0UL); seq = get_insns (); end_sequence (); *************** arm_load_pic_register (unsigned long sav *** 5709,5714 **** --- 5714,5727 ---- emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp)); emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno)); } + else if (arm_pic_register != INVALID_REGNUM + && arm_pic_register > LAST_LO_REGNUM + && REGNO (pic_reg) <= LAST_LO_REGNUM) + { + emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno)); + emit_move_insn (gen_rtx_REG (Pmode, arm_pic_register), pic_reg); + emit_use (gen_rtx_REG (Pmode, arm_pic_register)); + } else emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno)); } *************** legitimize_tls_address (rtx x, rtx reg) *** 6573,6578 **** --- 6586,6617 ---- rtx arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) { + if (arm_tls_referenced_p (x)) + { + rtx addend = NULL; + + if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS) + { + addend = XEXP (XEXP (x, 0), 1); + x = XEXP (XEXP (x, 0), 0); + } + + if (GET_CODE (x) != SYMBOL_REF) + return x; + + gcc_assert (SYMBOL_REF_TLS_MODEL (x) != 0); + + x = legitimize_tls_address (x, NULL_RTX); + + if (addend) + { + x = gen_rtx_PLUS (SImode, x, addend); + orig_x = x; + } + else + return x; + } + if (!TARGET_ARM) { /* TODO: legitimize_address for Thumb2. */ *************** arm_legitimize_address (rtx x, rtx orig_ *** 6581,6589 **** return thumb_legitimize_address (x, orig_x, mode); } - if (arm_tls_symbol_p (x)) - return legitimize_tls_address (x, NULL_RTX); - if (GET_CODE (x) == PLUS) { rtx xop0 = XEXP (x, 0); --- 6620,6625 ---- *************** arm_legitimize_address (rtx x, rtx orig_ *** 6695,6703 **** rtx thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) { - if (arm_tls_symbol_p (x)) - return legitimize_tls_address (x, NULL_RTX); - if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)) && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode) --- 6731,6736 ---- *************** thumb_legitimize_reload_address (rtx *x_ *** 6988,7007 **** /* Test for various thread-local symbols. */ - /* Return TRUE if X is a thread-local symbol. */ - - static bool - arm_tls_symbol_p (rtx x) - { - if (! TARGET_HAVE_TLS) - return false; - - if (GET_CODE (x) != SYMBOL_REF) - return false; - - return SYMBOL_REF_TLS_MODEL (x) != 0; - } - /* Helper for arm_tls_referenced_p. */ static int --- 7021,7026 ---- *************** arm_expand_neon_args (rtx target, int ic *** 21279,21285 **** type_mode); } ! op[argc] = expand_normal (arg[argc]); switch (thisarg) { --- 21298,21308 ---- type_mode); } ! /* Use EXPAND_MEMORY for NEON_ARG_MEMORY to ensure a MEM_P ! be returned. */ ! op[argc] = expand_expr (arg[argc], NULL_RTX, VOIDmode, ! (thisarg == NEON_ARG_MEMORY ! ? EXPAND_MEMORY : EXPAND_NORMAL)); switch (thisarg) { *************** arm_expand_neon_args (rtx target, int ic *** 21298,21303 **** --- 21321,21329 ---- break; case NEON_ARG_MEMORY: + /* Check if expand failed. */ + if (op[argc] == const0_rtx) + return 0; gcc_assert (MEM_P (op[argc])); PUT_MODE (op[argc], mode[argc]); /* ??? arm_neon.h uses the same built-in functions for signed *************** arm_expand_epilogue_apcs_frame (bool rea *** 23555,23560 **** --- 23581,23587 ---- num_regs = bit_count (saved_regs_mask); if ((offsets->outgoing_args != (1 + num_regs)) || cfun->calls_alloca) { + emit_insn (gen_blockage ()); /* Unwind the stack to just below the saved registers. */ emit_insn (gen_addsi3 (stack_pointer_rtx, hard_frame_pointer_rtx, *************** arm_expand_epilogue_apcs_frame (bool rea *** 23583,23590 **** if (crtl->calls_eh_return) emit_insn (gen_addsi3 (stack_pointer_rtx, ! stack_pointer_rtx, ! GEN_INT (ARM_EH_STACKADJ_REGNUM))); if (IS_STACKALIGN (func_type)) /* Restore the original stack pointer. Before prologue, the stack was --- 23610,23617 ---- if (crtl->calls_eh_return) emit_insn (gen_addsi3 (stack_pointer_rtx, ! stack_pointer_rtx, ! gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM))); if (IS_STACKALIGN (func_type)) /* Restore the original stack pointer. Before prologue, the stack was diff -Nrcpad gcc-4.8.2/gcc/config/arm/arm.h gcc-4.8.3/gcc/config/arm/arm.h *** gcc-4.8.2/gcc/config/arm/arm.h Sun Mar 17 16:28:55 2013 --- gcc-4.8.3/gcc/config/arm/arm.h Thu May 8 17:06:01 2014 *************** enum reg_class *** 1213,1223 **** VFPv2. In big-endian mode, modes greater than word size (i.e. DFmode) are stored in VFP registers in little-endian order. We can't describe that accurately to ! GCC, so avoid taking subregs of such values. */ ! #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ ! (TARGET_VFP && TARGET_BIG_END \ ! && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ ! || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ && reg_classes_intersect_p (VFP_REGS, (CLASS))) /* The class value for index registers, and the one for base regs. */ --- 1213,1227 ---- VFPv2. In big-endian mode, modes greater than word size (i.e. DFmode) are stored in VFP registers in little-endian order. We can't describe that accurately to ! GCC, so avoid taking subregs of such values. ! The only exception is going from a 128-bit to a 64-bit type. In that case ! the data layout happens to be consistent for big-endian, so we explicitly allow ! that case. */ ! #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ ! (TARGET_VFP && TARGET_BIG_END \ ! && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \ ! && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ ! || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ && reg_classes_intersect_p (VFP_REGS, (CLASS))) /* The class value for index registers, and the one for base regs. */ *************** extern int making_const_table; *** 2139,2152 **** #undef ASM_OUTPUT_BEFORE_CASE_LABEL #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ ! /* Make sure subsequent insns are aligned after a TBB. */ ! #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ ! do \ ! { \ ! if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \ ! ASM_OUTPUT_ALIGN (FILE, 1); \ ! } \ ! while (0) #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ do \ --- 2143,2151 ---- #undef ASM_OUTPUT_BEFORE_CASE_LABEL #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ ! #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ ! (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ ! ? 1 : 0) #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ do \ diff -Nrcpad gcc-4.8.2/gcc/config/arm/arm.md gcc-4.8.3/gcc/config/arm/arm.md *** gcc-4.8.2/gcc/config/arm/arm.md Fri Feb 22 14:23:12 2013 --- gcc-4.8.3/gcc/config/arm/arm.md Fri Jan 17 11:48:06 2014 *************** *** 11036,11042 **** [(set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) (match_operand:SI 2 "const_int_operand" "I"))) ! (set (match_operand:DF 3 "arm_hard_register_operand" "") (mem:DF (match_dup 1)))])] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "* --- 11036,11042 ---- [(set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) (match_operand:SI 2 "const_int_operand" "I"))) ! (set (match_operand:DF 3 "vfp_hard_register_operand" "") (mem:DF (match_dup 1)))])] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "* *************** *** 11270,11276 **** (match_operand:SI 1 "" "") (match_operand:SI 2 "" ""))] "TARGET_32BIT && arm_arch5e" ! "pld\\t%a0") ;; General predication pattern --- 11270,11278 ---- (match_operand:SI 1 "" "") (match_operand:SI 2 "" ""))] "TARGET_32BIT && arm_arch5e" ! "pld\\t%a0" ! [(set_attr "type" "load1")] ! ) ;; General predication pattern diff -Nrcpad gcc-4.8.2/gcc/config/arm/iterators.md gcc-4.8.3/gcc/config/arm/iterators.md *** gcc-4.8.2/gcc/config/arm/iterators.md Thu Apr 4 14:34:01 2013 --- gcc-4.8.3/gcc/config/arm/iterators.md Thu Nov 28 17:30:53 2013 *************** *** 493,498 **** --- 493,502 ---- (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no") (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")]) + (define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional") + (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional") + (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")]) + (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) diff -Nrcpad gcc-4.8.2/gcc/config/arm/ldmstm.md gcc-4.8.3/gcc/config/arm/ldmstm.md *** gcc-4.8.2/gcc/config/arm/ldmstm.md Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/arm/ldmstm.md Fri Jan 17 11:48:06 2014 *************** *** 23,37 **** (define_insn "*ldm4_ia" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) ! (set (match_operand:SI 4 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" --- 23,37 ---- (define_insn "*ldm4_ia" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) ! (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" *************** *** 41,55 **** (define_insn "*thumb_ldm4_ia" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (match_operand:SI 5 "s_register_operand" "l"))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) ! (set (match_operand:SI 4 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" --- 41,55 ---- (define_insn "*thumb_ldm4_ia" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_operand:SI 5 "s_register_operand" "l"))) ! (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) ! (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) ! (set (match_operand:SI 4 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" *************** *** 60,74 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (match_dup 5))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) ! (set (match_operand:SI 4 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" --- 60,74 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) ! (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_dup 5))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) ! (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" *************** *** 80,94 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&l") (plus:SI (match_dup 5) (const_int 16))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (match_dup 5))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) ! (set (match_operand:SI 4 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" --- 80,94 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&l") (plus:SI (match_dup 5) (const_int 16))) ! (set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_dup 5))) ! (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) ! (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) ! (set (match_operand:SI 4 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" *************** *** 98,110 **** (define_insn "*stm4_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk")) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) ! (match_operand:SI 3 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) ! (match_operand:SI 4 "arm_hard_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") --- 98,110 ---- (define_insn "*stm4_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk")) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) ! (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) ! (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") *************** *** 115,127 **** [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (match_dup 5)) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) ! (match_operand:SI 3 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) ! (match_operand:SI 4 "arm_hard_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "stm%(ia%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") --- 115,127 ---- [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (match_dup 5)) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) ! (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) ! (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "stm%(ia%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") *************** *** 132,160 **** [(set (match_operand:SI 5 "s_register_operand" "+&l") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (match_dup 5)) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) ! (match_operand:SI 3 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) ! (match_operand:SI 4 "arm_hard_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" "stm%(ia%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4")]) (define_insn "*ldm4_ib" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12)))) ! (set (match_operand:SI 4 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 16))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" --- 132,160 ---- [(set (match_operand:SI 5 "s_register_operand" "+&l") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (match_dup 5)) ! (match_operand:SI 1 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) ! (match_operand:SI 2 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) ! (match_operand:SI 3 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) ! (match_operand:SI 4 "low_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" "stm%(ia%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4")]) (define_insn "*ldm4_ib" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12)))) ! (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 16))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" *************** *** 166,181 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12)))) ! (set (match_operand:SI 4 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 16))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" --- 166,181 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) ! (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12)))) ! (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 16))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" *************** *** 186,198 **** (define_insn "*stm4_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) ! (match_operand:SI 3 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) ! (match_operand:SI 4 "arm_hard_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(ib%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") --- 186,198 ---- (define_insn "*stm4_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) ! (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) ! (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(ib%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") *************** *** 203,215 **** [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) ! (match_operand:SI 3 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) ! (match_operand:SI 4 "arm_hard_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "stm%(ib%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") --- 203,215 ---- [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) ! (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) ! (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "stm%(ib%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") *************** *** 217,232 **** (define_insn "*ldm4_da" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4)))) ! (set (match_operand:SI 4 "arm_hard_register_operand" "") (mem:SI (match_dup 5)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "ldm%(da%)\t%5, {%1, %2, %3, %4}" --- 217,232 ---- (define_insn "*ldm4_da" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4)))) ! (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (match_dup 5)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "ldm%(da%)\t%5, {%1, %2, %3, %4}" *************** *** 237,252 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4)))) ! (set (match_operand:SI 4 "arm_hard_register_operand" "") (mem:SI (match_dup 5)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "ldm%(da%)\t%5!, {%1, %2, %3, %4}" --- 237,252 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) ! (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4)))) ! (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (match_dup 5)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "ldm%(da%)\t%5!, {%1, %2, %3, %4}" *************** *** 256,268 **** (define_insn "*stm4_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) ! (match_operand:SI 3 "arm_hard_register_operand" "")) (set (mem:SI (match_dup 5)) ! (match_operand:SI 4 "arm_hard_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(da%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") --- 256,268 ---- (define_insn "*stm4_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) ! (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 5)) ! (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(da%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") *************** *** 273,285 **** [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) ! (match_operand:SI 3 "arm_hard_register_operand" "")) (set (mem:SI (match_dup 5)) ! (match_operand:SI 4 "arm_hard_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "stm%(da%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") --- 273,285 ---- [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) ! (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 5)) ! (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "stm%(da%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") *************** *** 287,302 **** (define_insn "*ldm4_db" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) ! (set (match_operand:SI 4 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" --- 287,302 ---- (define_insn "*ldm4_db" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) ! (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" *************** *** 308,323 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -16)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) ! (set (match_operand:SI 4 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" --- 308,323 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) ! (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -16)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) ! (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" *************** *** 328,340 **** (define_insn "*stm4_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) ! (match_operand:SI 3 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) ! (match_operand:SI 4 "arm_hard_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(db%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") --- 328,340 ---- (define_insn "*stm4_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) ! (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) ! (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(db%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") *************** *** 345,357 **** [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) (set (mem:SI (plus:SI (match_dup 5) (const_int -16))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) ! (match_operand:SI 3 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) ! (match_operand:SI 4 "arm_hard_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "stm%(db%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") --- 345,357 ---- [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) (set (mem:SI (plus:SI (match_dup 5) (const_int -16))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) ! (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) ! (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "stm%(db%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") *************** *** 466,477 **** (define_insn "*ldm3_ia" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" --- 466,477 ---- (define_insn "*ldm3_ia" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" *************** *** 481,492 **** (define_insn "*thumb_ldm3_ia" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (match_operand:SI 4 "s_register_operand" "l"))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" --- 481,492 ---- (define_insn "*thumb_ldm3_ia" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_operand:SI 4 "s_register_operand" "l"))) ! (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) ! (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" *************** *** 497,508 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (match_dup 4))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" --- 497,508 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) ! (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_dup 4))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" *************** *** 514,525 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&l") (plus:SI (match_dup 4) (const_int 12))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (match_dup 4))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" --- 514,525 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&l") (plus:SI (match_dup 4) (const_int 12))) ! (set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_dup 4))) ! (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) ! (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" *************** *** 529,539 **** (define_insn "*stm3_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk")) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) ! (match_operand:SI 3 "arm_hard_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") --- 529,539 ---- (define_insn "*stm3_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk")) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) ! (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") *************** *** 544,554 **** [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (match_dup 4)) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) ! (match_operand:SI 3 "arm_hard_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") --- 544,554 ---- [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (match_dup 4)) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) ! (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") *************** *** 559,582 **** [(set (match_operand:SI 4 "s_register_operand" "+&l") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (match_dup 4)) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) ! (match_operand:SI 3 "arm_hard_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3")]) (define_insn "*ldm3_ib" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 12))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" --- 559,582 ---- [(set (match_operand:SI 4 "s_register_operand" "+&l") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (match_dup 4)) ! (match_operand:SI 1 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) ! (match_operand:SI 2 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) ! (match_operand:SI 3 "low_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3")]) (define_insn "*ldm3_ib" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 12))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" *************** *** 588,600 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 12))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" --- 588,600 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) ! (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 12))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" *************** *** 605,615 **** (define_insn "*stm3_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) ! (match_operand:SI 3 "arm_hard_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(ib%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") --- 605,615 ---- (define_insn "*stm3_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) ! (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(ib%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") *************** *** 620,630 **** [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) ! (match_operand:SI 3 "arm_hard_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(ib%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") --- 620,630 ---- [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) ! (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(ib%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") *************** *** 632,644 **** (define_insn "*ldm3_da" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (match_dup 4)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "ldm%(da%)\t%4, {%1, %2, %3}" --- 632,644 ---- (define_insn "*ldm3_da" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (match_dup 4)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "ldm%(da%)\t%4, {%1, %2, %3}" *************** *** 649,661 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (match_dup 4)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "ldm%(da%)\t%4!, {%1, %2, %3}" --- 649,661 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) ! (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (match_dup 4)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "ldm%(da%)\t%4!, {%1, %2, %3}" *************** *** 665,675 **** (define_insn "*stm3_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (match_dup 4)) ! (match_operand:SI 3 "arm_hard_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(da%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") --- 665,675 ---- (define_insn "*stm3_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 4)) ! (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(da%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") *************** *** 680,690 **** [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (match_dup 4)) ! (match_operand:SI 3 "arm_hard_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(da%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") --- 680,690 ---- [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 4)) ! (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(da%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") *************** *** 692,704 **** (define_insn "*ldm3_db" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" --- 692,704 ---- (define_insn "*ldm3_db" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" *************** *** 710,722 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -12)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) ! (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" --- 710,722 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) ! (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -12)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) ! (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" *************** *** 727,737 **** (define_insn "*stm3_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) ! (match_operand:SI 3 "arm_hard_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(db%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") --- 727,737 ---- (define_insn "*stm3_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) ! (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(db%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") *************** *** 742,752 **** [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) (set (mem:SI (plus:SI (match_dup 4) (const_int -12))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) ! (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) ! (match_operand:SI 3 "arm_hard_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(db%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") --- 742,752 ---- [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) (set (mem:SI (plus:SI (match_dup 4) (const_int -12))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) ! (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) ! (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(db%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") *************** *** 847,855 **** (define_insn "*ldm2_ia" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" --- 847,855 ---- (define_insn "*ldm2_ia" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" *************** *** 859,867 **** (define_insn "*thumb_ldm2_ia" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (match_operand:SI 3 "s_register_operand" "l"))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2" --- 859,867 ---- (define_insn "*thumb_ldm2_ia" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_operand:SI 3 "s_register_operand" "l"))) ! (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2" *************** *** 872,880 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (match_dup 3))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" --- 872,880 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) ! (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_dup 3))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" *************** *** 886,894 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&l") (plus:SI (match_dup 3) (const_int 8))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (match_dup 3))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" --- 886,894 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&l") (plus:SI (match_dup 3) (const_int 8))) ! (set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_dup 3))) ! (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" *************** *** 898,906 **** (define_insn "*stm2_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk")) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) ! (match_operand:SI 2 "arm_hard_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "stm%(ia%)\t%3, {%1, %2}" [(set_attr "type" "store2") --- 898,906 ---- (define_insn "*stm2_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk")) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) ! (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "stm%(ia%)\t%3, {%1, %2}" [(set_attr "type" "store2") *************** *** 911,919 **** [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (match_dup 3)) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) ! (match_operand:SI 2 "arm_hard_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%3!, {%1, %2}" [(set_attr "type" "store2") --- 911,919 ---- [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (match_dup 3)) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) ! (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%3!, {%1, %2}" [(set_attr "type" "store2") *************** *** 924,942 **** [(set (match_operand:SI 3 "s_register_operand" "+&l") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (match_dup 3)) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) ! (match_operand:SI 2 "arm_hard_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%3!, {%1, %2}" [(set_attr "type" "store2")]) (define_insn "*ldm2_ib" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 8))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" --- 924,942 ---- [(set (match_operand:SI 3 "s_register_operand" "+&l") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (match_dup 3)) ! (match_operand:SI 1 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) ! (match_operand:SI 2 "low_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%3!, {%1, %2}" [(set_attr "type" "store2")]) (define_insn "*ldm2_ib" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 8))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" *************** *** 948,957 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 8))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" --- 948,957 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) ! (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 8))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" *************** *** 962,970 **** (define_insn "*stm2_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) ! (match_operand:SI 2 "arm_hard_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "stm%(ib%)\t%3, {%1, %2}" [(set_attr "type" "store2") --- 962,970 ---- (define_insn "*stm2_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) ! (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "stm%(ib%)\t%3, {%1, %2}" [(set_attr "type" "store2") *************** *** 975,983 **** [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) ! (match_operand:SI 2 "arm_hard_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(ib%)\t%3!, {%1, %2}" [(set_attr "type" "store2") --- 975,983 ---- [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) ! (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(ib%)\t%3!, {%1, %2}" [(set_attr "type" "store2") *************** *** 985,994 **** (define_insn "*ldm2_da" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (match_dup 3)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "ldm%(da%)\t%3, {%1, %2}" --- 985,994 ---- (define_insn "*ldm2_da" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (match_dup 3)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "ldm%(da%)\t%3, {%1, %2}" *************** *** 999,1008 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (match_dup 3)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "ldm%(da%)\t%3!, {%1, %2}" --- 999,1008 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) ! (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (match_dup 3)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "ldm%(da%)\t%3!, {%1, %2}" *************** *** 1012,1020 **** (define_insn "*stm2_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (match_dup 3)) ! (match_operand:SI 2 "arm_hard_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "stm%(da%)\t%3, {%1, %2}" [(set_attr "type" "store2") --- 1012,1020 ---- (define_insn "*stm2_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 3)) ! (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "stm%(da%)\t%3, {%1, %2}" [(set_attr "type" "store2") *************** *** 1025,1033 **** [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (match_dup 3)) ! (match_operand:SI 2 "arm_hard_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(da%)\t%3!, {%1, %2}" [(set_attr "type" "store2") --- 1025,1033 ---- [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 3)) ! (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(da%)\t%3!, {%1, %2}" [(set_attr "type" "store2") *************** *** 1035,1044 **** (define_insn "*ldm2_db" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" --- 1035,1044 ---- (define_insn "*ldm2_db" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" *************** *** 1050,1059 **** [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) ! (set (match_operand:SI 1 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -8)))) ! (set (match_operand:SI 2 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" --- 1050,1059 ---- [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) ! (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -8)))) ! (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" *************** *** 1064,1072 **** (define_insn "*stm2_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) ! (match_operand:SI 2 "arm_hard_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "stm%(db%)\t%3, {%1, %2}" [(set_attr "type" "store2") --- 1064,1072 ---- (define_insn "*stm2_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) ! (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "stm%(db%)\t%3, {%1, %2}" [(set_attr "type" "store2") *************** *** 1077,1085 **** [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) (set (mem:SI (plus:SI (match_dup 3) (const_int -8))) ! (match_operand:SI 1 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) ! (match_operand:SI 2 "arm_hard_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(db%)\t%3!, {%1, %2}" [(set_attr "type" "store2") --- 1077,1085 ---- [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) (set (mem:SI (plus:SI (match_dup 3) (const_int -8))) ! (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) ! (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(db%)\t%3!, {%1, %2}" [(set_attr "type" "store2") diff -Nrcpad gcc-4.8.2/gcc/config/arm/predicates.md gcc-4.8.3/gcc/config/arm/predicates.md *** gcc-4.8.2/gcc/config/arm/predicates.md Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/arm/predicates.md Fri Jan 17 11:48:06 2014 *************** *** 31,41 **** || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); }) ! ;; Any hard register. ! (define_predicate "arm_hard_register_operand" (match_code "reg") { ! return REGNO (op) < FIRST_PSEUDO_REGISTER; }) ;; A low register. --- 31,41 ---- || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); }) ! ;; Any general register. ! (define_predicate "arm_hard_general_register_operand" (match_code "reg") { ! return REGNO (op) <= LAST_ARM_REGNUM; }) ;; A low register. *************** *** 76,81 **** --- 76,87 ---- && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); }) + (define_predicate "vfp_hard_register_operand" + (match_code "reg") + { + return (IS_VFP_REGNUM (REGNO (op))); + }) + (define_predicate "zero_operand" (and (match_code "const_int,const_double,const_vector") (match_test "op == CONST0_RTX (mode)"))) diff -Nrcpad gcc-4.8.2/gcc/config/arm/vfp.md gcc-4.8.3/gcc/config/arm/vfp.md *** gcc-4.8.2/gcc/config/arm/vfp.md Tue Sep 10 16:53:15 2013 --- gcc-4.8.3/gcc/config/arm/vfp.md Thu Nov 28 17:30:53 2013 *************** *** 1264,1269 **** --- 1264,1270 ---- "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " "vrint%?.\\t%0, %1" [(set_attr "predicable" "") + (set_attr "conds" "") (set_attr "type" "f_rint")] ) *************** *** 1280,1286 **** (match_operand:SDF 2 "register_operand" "")))] "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " "vmaxnm.\\t%0, %1, %2" ! [(set_attr "type" "f_minmax")] ) (define_insn "smin3" --- 1281,1288 ---- (match_operand:SDF 2 "register_operand" "")))] "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " "vmaxnm.\\t%0, %1, %2" ! [(set_attr "type" "f_minmax") ! (set_attr "conds" "unconditional")] ) (define_insn "smin3" *************** *** 1289,1295 **** (match_operand:SDF 2 "register_operand" "")))] "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " "vminnm.\\t%0, %1, %2" ! [(set_attr "type" "f_minmax")] ) ;; Unimplemented insns: --- 1291,1298 ---- (match_operand:SDF 2 "register_operand" "")))] "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " "vminnm.\\t%0, %1, %2" ! [(set_attr "type" "f_minmax") ! (set_attr "conds" "unconditional")] ) ;; Unimplemented insns: diff -Nrcpad gcc-4.8.2/gcc/config/avr/avr.c gcc-4.8.3/gcc/config/avr/avr.c *** gcc-4.8.2/gcc/config/avr/avr.c Fri Jul 19 11:15:26 2013 --- gcc-4.8.3/gcc/config/avr/avr.c Mon May 12 16:07:44 2014 *************** avr_set_current_function (tree decl) *** 587,596 **** const char *name; name = DECL_ASSEMBLER_NAME_SET_P (decl) ! /* Remove the leading '*' added in set_user_assembler_name. */ ! ? 1 + IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)) : IDENTIFIER_POINTER (DECL_NAME (decl)); /* Silently ignore 'signal' if 'interrupt' is present. AVR-LibC startet using this when it switched from SIGNAL and INTERRUPT to ISR. */ --- 587,600 ---- const char *name; name = DECL_ASSEMBLER_NAME_SET_P (decl) ! ? IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)) : IDENTIFIER_POINTER (DECL_NAME (decl)); + /* Skip a leading '*' that might still prefix the assembler name, + e.g. in non-LTO runs. */ + + name = default_strip_name_encoding (name); + /* Silently ignore 'signal' if 'interrupt' is present. AVR-LibC startet using this when it switched from SIGNAL and INTERRUPT to ISR. */ *************** avr_notice_update_cc (rtx body ATTRIBUTE *** 2339,2344 **** --- 2343,2354 ---- } break; + case CC_SET_VZN: + /* Insn like INC, DEC, NEG that set Z,N,V. We currently don't make use + of this combination, cf. also PR61055. */ + CC_STATUS_INIT; + break; + case CC_SET_CZN: /* Insn sets the Z,N,C flags of CC to recog_operand[0]. The V flag may or may not be known but that's ok because *************** avr_out_store_psi (rtx insn, rtx *op, in *** 3977,3983 **** "std Y+61,%A1" CR_TAB "std Y+62,%B1" CR_TAB "std Y+63,%C1" CR_TAB ! "sbiw r28,%o0-60", op, plen, -5); return avr_asm_len ("subi r28,lo8(-%o0)" CR_TAB "sbci r29,hi8(-%o0)" CR_TAB --- 3987,3993 ---- "std Y+61,%A1" CR_TAB "std Y+62,%B1" CR_TAB "std Y+63,%C1" CR_TAB ! "sbiw r28,%o0-61", op, plen, -5); return avr_asm_len ("subi r28,lo8(-%o0)" CR_TAB "sbci r29,hi8(-%o0)" CR_TAB *************** avr_out_plus_1 (rtx *xop, int *plen, enu *** 6274,6280 **** if (REG_P (xop[2])) { ! *pcc = MINUS == code ? (int) CC_SET_CZN : (int) CC_SET_N; for (i = 0; i < n_bytes; i++) { --- 6284,6290 ---- if (REG_P (xop[2])) { ! *pcc = MINUS == code ? (int) CC_SET_CZN : (int) CC_CLOBBER; for (i = 0; i < n_bytes; i++) { *************** avr_out_plus_1 (rtx *xop, int *plen, enu *** 6383,6389 **** op, plen, 1); if (n_bytes == 2 && PLUS == code) ! *pcc = CC_SET_ZN; } i++; --- 6393,6399 ---- op, plen, 1); if (n_bytes == 2 && PLUS == code) ! *pcc = CC_SET_CZN; } i++; *************** avr_out_plus_1 (rtx *xop, int *plen, enu *** 6406,6411 **** --- 6416,6422 ---- { avr_asm_len ((code == PLUS) ^ (val8 == 1) ? "dec %0" : "inc %0", op, plen, 1); + *pcc = CC_CLOBBER; break; } *************** avr_out_plus (rtx insn, rtx *xop, int *p *** 6806,6813 **** /* Work out the shortest sequence. */ ! avr_out_plus_1 (op, &len_minus, MINUS, &cc_plus, code_sat, sign, out_label); ! avr_out_plus_1 (op, &len_plus, PLUS, &cc_minus, code_sat, sign, out_label); if (plen) { --- 6817,6824 ---- /* Work out the shortest sequence. */ ! avr_out_plus_1 (op, &len_minus, MINUS, &cc_minus, code_sat, sign, out_label); ! avr_out_plus_1 (op, &len_plus, PLUS, &cc_plus, code_sat, sign, out_label); if (plen) { diff -Nrcpad gcc-4.8.2/gcc/config/avr/avr.md gcc-4.8.3/gcc/config/avr/avr.md *** gcc-4.8.2/gcc/config/avr/avr.md Fri Jul 19 11:15:26 2013 --- gcc-4.8.3/gcc/config/avr/avr.md Fri May 9 11:29:58 2014 *************** *** 89,95 **** (include "constraints.md") ;; Condition code settings. ! (define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber, plus,ldi" (const_string "none")) --- 89,95 ---- (include "constraints.md") ;; Condition code settings. ! (define_attr "cc" "none,set_czn,set_zn,set_vzn,set_n,compare,clobber, plus,ldi" (const_string "none")) *************** *** 1097,1103 **** inc %0\;inc %0 dec %0\;dec %0" [(set_attr "length" "1,1,1,1,2,2") ! (set_attr "cc" "set_czn,set_czn,set_zn,set_zn,set_zn,set_zn")]) ;; "addhi3" ;; "addhq3" "adduhq3" --- 1097,1103 ---- inc %0\;inc %0 dec %0\;dec %0" [(set_attr "length" "1,1,1,1,2,2") ! (set_attr "cc" "set_czn,set_czn,set_vzn,set_vzn,set_vzn,set_vzn")]) ;; "addhi3" ;; "addhq3" "adduhq3" *************** *** 1368,1374 **** dec %0\;dec %0 inc %0\;inc %0" [(set_attr "length" "1,1,1,1,2,2") ! (set_attr "cc" "set_czn,set_czn,set_zn,set_zn,set_zn,set_zn")]) ;; "subhi3" ;; "subhq3" "subuhq3" --- 1368,1374 ---- dec %0\;dec %0 inc %0\;inc %0" [(set_attr "length" "1,1,1,1,2,2") ! (set_attr "cc" "set_czn,set_czn,set_vzn,set_vzn,set_vzn,set_vzn")]) ;; "subhi3" ;; "subhq3" "subuhq3" *************** *** 3991,3997 **** "" "neg %0" [(set_attr "length" "1") ! (set_attr "cc" "set_zn")]) (define_insn "*negqihi2" [(set (match_operand:HI 0 "register_operand" "=r") --- 3991,3997 ---- "" "neg %0" [(set_attr "length" "1") ! (set_attr "cc" "set_vzn")]) (define_insn "*negqihi2" [(set (match_operand:HI 0 "register_operand" "=r") diff -Nrcpad gcc-4.8.2/gcc/config/cris/cris.md gcc-4.8.3/gcc/config/cris/cris.md *** gcc-4.8.2/gcc/config/cris/cris.md Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/cris/cris.md Thu Jan 9 00:23:22 2014 *************** *** 758,764 **** (match_operand:SI 1 "const_int_operand" "")) (match_operand:SI 2 "register_operand" ""))]) (match_operand 3 "register_operand" "")) ! (set (match_operand:SI 4 "register_operand" "") (plus:SI (mult:SI (match_dup 0) (match_dup 1)) (match_dup 2)))])] --- 758,764 ---- (match_operand:SI 1 "const_int_operand" "")) (match_operand:SI 2 "register_operand" ""))]) (match_operand 3 "register_operand" "")) ! (set (match_operand:SI 4 "cris_nonsp_register_operand" "") (plus:SI (mult:SI (match_dup 0) (match_dup 1)) (match_dup 2)))])] *************** *** 859,865 **** (match_operand:SI 0 "cris_bdap_operand" "") (match_operand:SI 1 "cris_bdap_operand" ""))]) (match_operand 2 "register_operand" "")) ! (set (match_operand:SI 3 "register_operand" "") (plus:SI (match_dup 0) (match_dup 1)))])] "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])" [(set (match_dup 4) (match_dup 2)) --- 859,865 ---- (match_operand:SI 0 "cris_bdap_operand" "") (match_operand:SI 1 "cris_bdap_operand" ""))]) (match_operand 2 "register_operand" "")) ! (set (match_operand:SI 3 "cris_nonsp_register_operand" "") (plus:SI (match_dup 0) (match_dup 1)))])] "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])" [(set (match_dup 4) (match_dup 2)) *************** *** 3960,3966 **** ;; up. (define_split ! [(set (match_operand 0 "register_operand" "") (match_operator 4 "cris_operand_extend_operator" [(match_operand 1 "register_operand" "") --- 3960,3966 ---- ;; up. (define_split ! [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_operand_extend_operator" [(match_operand 1 "register_operand" "") *************** *** 3990,3996 **** ;; Call this op-extend-split-rx=rz (define_split ! [(set (match_operand 0 "register_operand" "") (match_operator 4 "cris_plus_or_bound_operator" [(match_operand 1 "register_operand" "") --- 3990,3996 ---- ;; Call this op-extend-split-rx=rz (define_split ! [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_plus_or_bound_operator" [(match_operand 1 "register_operand" "") *************** *** 4018,4024 **** ;; Call this op-extend-split-swapped (define_split ! [(set (match_operand 0 "register_operand" "") (match_operator 4 "cris_plus_or_bound_operator" [(match_operator --- 4018,4024 ---- ;; Call this op-extend-split-swapped (define_split ! [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_plus_or_bound_operator" [(match_operator *************** *** 4044,4050 **** ;; bound. Call this op-extend-split-swapped-rx=rz. (define_split ! [(set (match_operand 0 "register_operand" "") (match_operator 4 "cris_plus_or_bound_operator" [(match_operator --- 4044,4050 ---- ;; bound. Call this op-extend-split-swapped-rx=rz. (define_split ! [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_plus_or_bound_operator" [(match_operator *************** *** 4075,4081 **** ;; Call this op-extend. (define_split ! [(set (match_operand 0 "register_operand" "") (match_operator 3 "cris_orthogonal_operator" [(match_operand 1 "register_operand" "") --- 4075,4081 ---- ;; Call this op-extend. (define_split ! [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 3 "cris_orthogonal_operator" [(match_operand 1 "register_operand" "") *************** *** 4099,4105 **** ;; Call this op-split-rx=rz (define_split ! [(set (match_operand 0 "register_operand" "") (match_operator 3 "cris_commutative_orth_op" [(match_operand 2 "memory_operand" "") --- 4099,4105 ---- ;; Call this op-split-rx=rz (define_split ! [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 3 "cris_commutative_orth_op" [(match_operand 2 "memory_operand" "") *************** *** 4123,4129 **** ;; Call this op-split-swapped. (define_split ! [(set (match_operand 0 "register_operand" "") (match_operator 3 "cris_commutative_orth_op" [(match_operand 1 "register_operand" "") --- 4123,4129 ---- ;; Call this op-split-swapped. (define_split ! [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 3 "cris_commutative_orth_op" [(match_operand 1 "register_operand" "") *************** *** 4146,4152 **** ;; Call this op-split-swapped-rx=rz. (define_split ! [(set (match_operand 0 "register_operand" "") (match_operator 3 "cris_orthogonal_operator" [(match_operand 2 "memory_operand" "") --- 4146,4152 ---- ;; Call this op-split-swapped-rx=rz. (define_split ! [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 3 "cris_orthogonal_operator" [(match_operand 2 "memory_operand" "") *************** *** 4555,4564 **** ;; We're not allowed to generate copies of registers with different mode ;; until after reload; copying pseudos upsets reload. CVS as of ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in ! ;; cselib_invalidate_regno. (define_split ; indir_to_reg_split ! [(set (match_operand 0 "register_operand" "") (match_operand 1 "indirect_operand" ""))] "reload_completed && REG_P (operands[0]) --- 4555,4565 ---- ;; We're not allowed to generate copies of registers with different mode ;; until after reload; copying pseudos upsets reload. CVS as of ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in ! ;; cselib_invalidate_regno. Also, don't do this for the stack-pointer, ! ;; as we don't want it set temporarily to an invalid value. (define_split ; indir_to_reg_split ! [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operand 1 "indirect_operand" ""))] "reload_completed && REG_P (operands[0]) *************** *** 4574,4580 **** ;; As the above, but MOVS and MOVU. (define_split ! [(set (match_operand 0 "register_operand" "") (match_operator 4 "cris_extend_operator" [(match_operand 1 "indirect_operand" "")]))] --- 4575,4581 ---- ;; As the above, but MOVS and MOVU. (define_split ! [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_extend_operator" [(match_operand 1 "indirect_operand" "")]))] diff -Nrcpad gcc-4.8.2/gcc/config/cris/predicates.md gcc-4.8.3/gcc/config/cris/predicates.md *** gcc-4.8.2/gcc/config/cris/predicates.md Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/cris/predicates.md Thu Jan 9 00:23:22 2014 *************** *** 76,81 **** --- 76,85 ---- (match_test "cris_simple_address_operand (XEXP (op, 0), Pmode)")))) + (define_predicate "cris_nonsp_register_operand" + (and (match_operand 0 "register_operand") + (match_test "op != stack_pointer_rtx"))) + ;; The caller needs to use :SI. (define_predicate "cris_bdap_sign_extend_operand" ; Disabled until diff -Nrcpad gcc-4.8.2/gcc/config/darwin.c gcc-4.8.3/gcc/config/darwin.c *** gcc-4.8.2/gcc/config/darwin.c Mon Jul 22 08:57:41 2013 --- gcc-4.8.3/gcc/config/darwin.c Mon Apr 7 06:40:18 2014 *************** is_objc_metadata (tree decl) *** 1329,1334 **** --- 1329,1337 ---- return NULL_TREE; } + static int classes_seen; + static int objc_metadata_seen; + /* Return the section required for Objective C ABI 2 metadata. */ static section * darwin_objc2_section (tree decl ATTRIBUTE_UNUSED, tree meta, section * base) *************** darwin_objc2_section (tree decl ATTRIBUT *** 1338,1349 **** gcc_assert (TREE_CODE (ident) == IDENTIFIER_NODE); p = IDENTIFIER_POINTER (ident); ! /* If we are in LTO, then we don't know the state of flag_next_runtime ! or flag_objc_abi when the code was generated. We set these from the ! meta-data - which is needed to deal with const string constructors. */ ! flag_next_runtime = 1; ! flag_objc_abi = 2; if (base == data_section) base = darwin_sections[objc2_metadata_section]; --- 1341,1349 ---- gcc_assert (TREE_CODE (ident) == IDENTIFIER_NODE); p = IDENTIFIER_POINTER (ident); ! gcc_checking_assert (flag_next_runtime == 1 && flag_objc_abi == 2); ! objc_metadata_seen = 1; if (base == data_section) base = darwin_sections[objc2_metadata_section]; *************** darwin_objc2_section (tree decl ATTRIBUT *** 1366,1372 **** else if (!strncmp (p, "V2_NLCL", 7)) return darwin_sections[objc2_nonlazy_class_section]; else if (!strncmp (p, "V2_CLAB", 7)) ! return darwin_sections[objc2_classlist_section]; else if (!strncmp (p, "V2_SRFS", 7)) return darwin_sections[objc2_selector_refs_section]; else if (!strncmp (p, "V2_NLCA", 7)) --- 1366,1375 ---- else if (!strncmp (p, "V2_NLCL", 7)) return darwin_sections[objc2_nonlazy_class_section]; else if (!strncmp (p, "V2_CLAB", 7)) ! { ! classes_seen = 1; ! return darwin_sections[objc2_classlist_section]; ! } else if (!strncmp (p, "V2_SRFS", 7)) return darwin_sections[objc2_selector_refs_section]; else if (!strncmp (p, "V2_NLCA", 7)) *************** darwin_objc1_section (tree decl ATTRIBUT *** 1401,1412 **** gcc_assert (TREE_CODE (ident) == IDENTIFIER_NODE); p = IDENTIFIER_POINTER (ident); ! /* If we are in LTO, then we don't know the state of flag_next_runtime ! or flag_objc_abi when the code was generated. We set these from the ! meta-data - which is needed to deal with const string constructors. */ ! flag_next_runtime = 1; ! if (!global_options_set.x_flag_objc_abi) ! flag_objc_abi = 1; /* String sections first, cos there are lots of strings. */ if (!strncmp (p, "V1_STRG", 7)) --- 1404,1412 ---- gcc_assert (TREE_CODE (ident) == IDENTIFIER_NODE); p = IDENTIFIER_POINTER (ident); ! gcc_checking_assert (flag_next_runtime == 1 && flag_objc_abi < 2); ! ! objc_metadata_seen = 1; /* String sections first, cos there are lots of strings. */ if (!strncmp (p, "V1_STRG", 7)) *************** darwin_objc1_section (tree decl ATTRIBUT *** 1419,1425 **** return darwin_sections[objc_meth_var_types_section]; else if (!strncmp (p, "V1_CLAS", 7)) ! return darwin_sections[objc_class_section]; else if (!strncmp (p, "V1_META", 7)) return darwin_sections[objc_meta_class_section]; else if (!strncmp (p, "V1_CATG", 7)) --- 1419,1428 ---- return darwin_sections[objc_meth_var_types_section]; else if (!strncmp (p, "V1_CLAS", 7)) ! { ! classes_seen = 1; ! return darwin_sections[objc_class_section]; ! } else if (!strncmp (p, "V1_META", 7)) return darwin_sections[objc_meta_class_section]; else if (!strncmp (p, "V1_CATG", 7)) *************** machopic_select_section (tree decl, *** 1603,1610 **** if (TREE_CODE (name) == TYPE_DECL) name = DECL_NAME (name); - /* FIXME: This is unsatisfactory for LTO, since it relies on other - metadata determining the source FE. */ if (!strcmp (IDENTIFIER_POINTER (name), "__builtin_ObjCString")) { if (flag_next_runtime) --- 1606,1611 ---- *************** darwin_file_end (void) *** 2845,2850 **** --- 2846,2878 ---- finalize_ctors (); if (!vec_safe_is_empty (dtors)) finalize_dtors (); + + /* If we are expecting to output NeXT ObjC meta-data, (and we actually see + some) then we output the fix-and-continue marker (Image Info). + This applies to Objective C, Objective C++ and LTO with either language + as part of the input. */ + if (flag_next_runtime && objc_metadata_seen) + { + unsigned int flags = 0; + if (flag_objc_abi >= 2) + { + flags = 16; + output_section_asm_op + (darwin_sections[objc2_image_info_section]->unnamed.data); + } + else + output_section_asm_op + (darwin_sections[objc_image_info_section]->unnamed.data); + + ASM_OUTPUT_ALIGN (asm_out_file, 2); + fputs ("L_OBJC_ImageInfo:\n", asm_out_file); + + flags |= (flag_replace_objc_classes && classes_seen) ? 1 : 0; + flags |= flag_objc_gc ? 2 : 0; + + fprintf (asm_out_file, "\t.long\t0\n\t.long\t%u\n", flags); + } + machopic_finish (asm_out_file); if (strcmp (lang_hooks.name, "GNU C++") == 0) { diff -Nrcpad gcc-4.8.2/gcc/config/i386/driver-i386.c gcc-4.8.3/gcc/config/i386/driver-i386.c *** gcc-4.8.2/gcc/config/i386/driver-i386.c Wed Aug 28 08:25:13 2013 --- gcc-4.8.3/gcc/config/i386/driver-i386.c Tue Feb 18 07:23:51 2014 *************** decode_caches_intel (unsigned reg, bool *** 126,131 **** --- 126,143 ---- case 0x0c: level1->sizekb = 16; level1->assoc = 4; level1->line = 32; break; + case 0x0d: + level1->sizekb = 16; level1->assoc = 4; level1->line = 64; + break; + case 0x0e: + level1->sizekb = 24; level1->assoc = 6; level1->line = 64; + break; + case 0x21: + level2->sizekb = 256; level2->assoc = 8; level2->line = 64; + break; + case 0x24: + level2->sizekb = 1024; level2->assoc = 16; level2->line = 64; + break; case 0x2c: level1->sizekb = 32; level1->assoc = 8; level1->line = 64; break; *************** decode_caches_intel (unsigned reg, bool *** 162,167 **** --- 174,182 ---- case 0x45: level2->sizekb = 2048; level2->assoc = 4; level2->line = 32; break; + case 0x48: + level2->sizekb = 3072; level2->assoc = 12; level2->line = 64; + break; case 0x49: if (xeon_mp) break; *************** decode_caches_intel (unsigned reg, bool *** 203,208 **** --- 218,226 ---- case 0x7f: level2->sizekb = 512; level2->assoc = 2; level2->line = 64; break; + case 0x80: + level2->sizekb = 512; level2->assoc = 8; level2->line = 64; + break; case 0x82: level2->sizekb = 256; level2->assoc = 8; level2->line = 32; break; *************** const char *host_detect_local_cpu (int a *** 470,475 **** --- 488,515 ---- has_xsaveopt = eax & bit_XSAVEOPT; } + /* Check cpuid level of extended features. */ + __cpuid (0x80000000, ext_level, ebx, ecx, edx); + + if (ext_level > 0x80000000) + { + __cpuid (0x80000001, eax, ebx, ecx, edx); + + has_lahf_lm = ecx & bit_LAHF_LM; + has_sse4a = ecx & bit_SSE4a; + has_abm = ecx & bit_ABM; + has_lwp = ecx & bit_LWP; + has_fma4 = ecx & bit_FMA4; + has_xop = ecx & bit_XOP; + has_tbm = ecx & bit_TBM; + has_lzcnt = ecx & bit_LZCNT; + has_prfchw = ecx & bit_PRFCHW; + + has_longmode = edx & bit_LM; + has_3dnowp = edx & bit_3DNOWP; + has_3dnow = edx & bit_3DNOW; + } + /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */ #define XCR_XFEATURE_ENABLED_MASK 0x0 #define XSTATE_FP 0x1 *************** const char *host_detect_local_cpu (int a *** 488,520 **** has_avx2 = 0; has_fma = 0; has_fma4 = 0; has_xop = 0; has_xsave = 0; has_xsaveopt = 0; } - /* Check cpuid level of extended features. */ - __cpuid (0x80000000, ext_level, ebx, ecx, edx); - - if (ext_level > 0x80000000) - { - __cpuid (0x80000001, eax, ebx, ecx, edx); - - has_lahf_lm = ecx & bit_LAHF_LM; - has_sse4a = ecx & bit_SSE4a; - has_abm = ecx & bit_ABM; - has_lwp = ecx & bit_LWP; - has_fma4 = ecx & bit_FMA4; - has_xop = ecx & bit_XOP; - has_tbm = ecx & bit_TBM; - has_lzcnt = ecx & bit_LZCNT; - has_prfchw = ecx & bit_PRFCHW; - - has_longmode = edx & bit_LM; - has_3dnowp = edx & bit_3DNOWP; - has_3dnow = edx & bit_3DNOW; - } - if (!arch) { if (vendor == signature_AMD_ebx --- 528,539 ---- has_avx2 = 0; has_fma = 0; has_fma4 = 0; + has_f16c = 0; has_xop = 0; has_xsave = 0; has_xsaveopt = 0; } if (!arch) { if (vendor == signature_AMD_ebx diff -Nrcpad gcc-4.8.2/gcc/config/i386/f16cintrin.h gcc-4.8.3/gcc/config/i386/f16cintrin.h *** gcc-4.8.2/gcc/config/i386/f16cintrin.h Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/i386/f16cintrin.h Sun Feb 2 10:21:44 2014 *************** *** 35,41 **** extern __inline float __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _cvtsh_ss (unsigned short __S) { ! __v8hi __H = __extension__ (__v8hi){ __S, 0, 0, 0, 0, 0, 0, 0 }; __v4sf __A = __builtin_ia32_vcvtph2ps (__H); return __builtin_ia32_vec_ext_v4sf (__A, 0); } --- 35,41 ---- extern __inline float __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _cvtsh_ss (unsigned short __S) { ! __v8hi __H = __extension__ (__v8hi){ (short) __S, 0, 0, 0, 0, 0, 0, 0 }; __v4sf __A = __builtin_ia32_vcvtph2ps (__H); return __builtin_ia32_vec_ext_v4sf (__A, 0); } diff -Nrcpad gcc-4.8.2/gcc/config/i386/i386.c gcc-4.8.3/gcc/config/i386/i386.c *** gcc-4.8.2/gcc/config/i386/i386.c Fri Aug 23 10:01:34 2013 --- gcc-4.8.3/gcc/config/i386/i386.c Thu May 8 19:32:34 2014 *************** struct processor_costs nocona_cost = { *** 1378,1384 **** 8, /* MMX or SSE register to integer */ 8, /* size of l1 cache. */ 1024, /* size of l2 cache. */ ! 128, /* size of prefetch block */ 8, /* number of parallel prefetches */ 1, /* Branch cost */ COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */ --- 1378,1384 ---- 8, /* MMX or SSE register to integer */ 8, /* size of l1 cache. */ 1024, /* size of l2 cache. */ ! 64, /* size of prefetch block */ 8, /* number of parallel prefetches */ 1, /* Branch cost */ COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */ *************** static unsigned int initial_ix86_tune_fe *** 1894,1903 **** m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_AMDFAM10 | m_BDVER | m_GENERIC, /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */ ! m_COREI7 | m_AMDFAM10 | m_BDVER | m_BTVER, /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */ ! m_COREI7 | m_BDVER, /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */ m_BDVER , --- 1894,1903 ---- m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_AMDFAM10 | m_BDVER | m_GENERIC, /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */ ! m_COREI7 | m_HASWELL | m_AMDFAM10 | m_BDVER | m_BTVER, /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */ ! m_COREI7 | m_HASWELL| m_BDVER, /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */ m_BDVER , *************** static tree ix86_veclibabi_acml (enum bu *** 2409,2414 **** --- 2409,2415 ---- /* Processor target table, indexed by processor number */ struct ptt { + const char *const name; /* processor name */ const struct processor_costs *cost; /* Processor costs */ const int align_loop; /* Default alignments. */ const int align_loop_max_skip; *************** struct ptt *** 2417,2482 **** const int align_func; }; static const struct ptt processor_target_table[PROCESSOR_max] = { ! {&i386_cost, 4, 3, 4, 3, 4}, ! {&i486_cost, 16, 15, 16, 15, 16}, ! {&pentium_cost, 16, 7, 16, 7, 16}, ! {&pentiumpro_cost, 16, 15, 16, 10, 16}, ! {&geode_cost, 0, 0, 0, 0, 0}, ! {&k6_cost, 32, 7, 32, 7, 32}, ! {&athlon_cost, 16, 7, 16, 7, 16}, ! {&pentium4_cost, 0, 0, 0, 0, 0}, ! {&k8_cost, 16, 7, 16, 7, 16}, ! {&nocona_cost, 0, 0, 0, 0, 0}, ! /* Core 2 */ ! {&core_cost, 16, 10, 16, 10, 16}, ! /* Core i7 */ ! {&core_cost, 16, 10, 16, 10, 16}, ! /* Core avx2 */ ! {&core_cost, 16, 10, 16, 10, 16}, ! {&generic32_cost, 16, 7, 16, 7, 16}, ! {&generic64_cost, 16, 10, 16, 10, 16}, ! {&amdfam10_cost, 32, 24, 32, 7, 32}, ! {&bdver1_cost, 16, 10, 16, 7, 11}, ! {&bdver2_cost, 16, 10, 16, 7, 11}, ! {&bdver3_cost, 16, 10, 16, 7, 11}, ! {&btver1_cost, 16, 10, 16, 7, 11}, ! {&btver2_cost, 16, 10, 16, 7, 11}, ! {&atom_cost, 16, 15, 16, 7, 16} ! }; ! ! static const char *const cpu_names[TARGET_CPU_DEFAULT_max] = ! { ! "generic", ! "i386", ! "i486", ! "pentium", ! "pentium-mmx", ! "pentiumpro", ! "pentium2", ! "pentium3", ! "pentium4", ! "pentium-m", ! "prescott", ! "nocona", ! "core2", ! "corei7", ! "core-avx2", ! "atom", ! "geode", ! "k6", ! "k6-2", ! "k6-3", ! "athlon", ! "athlon-4", ! "k8", ! "amdfam10", ! "bdver1", ! "bdver2", ! "bdver3", ! "btver1", ! "btver2" }; static bool --- 2418,2448 ---- const int align_func; }; + /* This table must be in sync with enum processor_type in i386.h. */ static const struct ptt processor_target_table[PROCESSOR_max] = { ! {"generic", &generic32_cost, 16, 7, 16, 7, 16}, ! {"generic", &generic64_cost, 16, 10, 16, 10, 16}, ! {"i386", &i386_cost, 4, 3, 4, 3, 4}, ! {"i486", &i486_cost, 16, 15, 16, 15, 16}, ! {"pentium", &pentium_cost, 16, 7, 16, 7, 16}, ! {"pentiumpro", &pentiumpro_cost, 16, 15, 16, 10, 16}, ! {"pentium4", &pentium4_cost, 0, 0, 0, 0, 0}, ! {"nocona", &nocona_cost, 0, 0, 0, 0, 0}, ! {"core2", &core_cost, 16, 10, 16, 10, 16}, ! {"corei7", &core_cost, 16, 10, 16, 10, 16}, ! {"core-avx2", &core_cost, 16, 10, 16, 10, 16}, ! {"atom", &atom_cost, 16, 15, 16, 7, 16}, ! {"geode", &geode_cost, 0, 0, 0, 0, 0}, ! {"k6", &k6_cost, 32, 7, 32, 7, 32}, ! {"athlon", &athlon_cost, 16, 7, 16, 7, 16}, ! {"k8", &k8_cost, 16, 7, 16, 7, 16}, ! {"amdfam10", &amdfam10_cost, 32, 24, 32, 7, 32}, ! {"bdver1", &bdver1_cost, 16, 10, 16, 7, 11}, ! {"bdver2", &bdver2_cost, 16, 10, 16, 7, 11}, ! {"bdver3", &bdver3_cost, 16, 10, 16, 7, 11}, ! {"btver1", &btver1_cost, 16, 10, 16, 7, 11}, ! {"btver2", &btver2_cost, 16, 10, 16, 7, 11} }; static bool *************** ix86_option_override_internal (bool main *** 2920,2926 **** | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2 | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT ! | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT}, {"atom", PROCESSOR_ATOM, CPU_ATOM, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 --- 2886,2892 ---- | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2 | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT ! | PTA_FMA | PTA_MOVBE | PTA_HLE | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT}, {"atom", PROCESSOR_ATOM, CPU_ATOM, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 *************** ix86_option_override_internal (bool main *** 2983,2989 **** {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 ! | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT}, --- 2949,2955 ---- {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 ! | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT}, *************** ix86_option_override_internal (bool main *** 3125,3131 **** ix86_tune_string = ix86_arch_string; if (!ix86_tune_string) { ! ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT]; ix86_tune_defaulted = 1; } --- 3091,3098 ---- ix86_tune_string = ix86_arch_string; if (!ix86_tune_string) { ! ix86_tune_string ! = processor_target_table[TARGET_CPU_DEFAULT].name; ix86_tune_defaulted = 1; } *************** ix86_function_specific_print (FILE *file *** 4078,4096 **** = ix86_target_string (ptr->x_ix86_isa_flags, ptr->x_target_flags, NULL, NULL, ptr->x_ix86_fpmath, false); fprintf (file, "%*sarch = %d (%s)\n", indent, "", ! ptr->arch, ! ((ptr->arch < TARGET_CPU_DEFAULT_max) ! ? cpu_names[ptr->arch] ! : "")); fprintf (file, "%*stune = %d (%s)\n", indent, "", ! ptr->tune, ! ((ptr->tune < TARGET_CPU_DEFAULT_max) ! ? cpu_names[ptr->tune] ! : "")); fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost); --- 4045,4059 ---- = ix86_target_string (ptr->x_ix86_isa_flags, ptr->x_target_flags, NULL, NULL, ptr->x_ix86_fpmath, false); + gcc_assert (ptr->arch < PROCESSOR_max); fprintf (file, "%*sarch = %d (%s)\n", indent, "", ! ptr->arch, processor_target_table[ptr->arch].name); + gcc_assert (ptr->tune < PROCESSOR_max); fprintf (file, "%*stune = %d (%s)\n", indent, "", ! ptr->tune, processor_target_table[ptr->tune].name); fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost); *************** ix86_function_regparm (const_tree type, *** 5213,5219 **** /* Use register calling convention for local functions when possible. */ if (decl && TREE_CODE (decl) == FUNCTION_DECL ! && optimize && !(profile_flag && !flag_fentry)) { /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */ --- 5176,5187 ---- /* Use register calling convention for local functions when possible. */ if (decl && TREE_CODE (decl) == FUNCTION_DECL ! /* Caller and callee must agree on the calling convention, so ! checking here just optimize means that with ! __attribute__((optimize (...))) caller could use regparm convention ! and callee not, or vice versa. Instead look at whether the callee ! is optimized or not. */ ! && opt_for_fn (decl, optimize) && !(profile_flag && !flag_fentry)) { /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */ *************** ix86_legitimate_combined_insn (rtx insn) *** 5409,5414 **** --- 5377,5393 ---- bool win; int j; + /* For pre-AVX disallow unaligned loads/stores where the + instructions don't support it. */ + if (!TARGET_AVX + && VECTOR_MODE_P (GET_MODE (op)) + && misaligned_operand (op, GET_MODE (op))) + { + int min_align = get_attr_ssememalign (insn); + if (min_align == 0) + return false; + } + /* A unary operator may be accepted by the predicate, but it is irrelevant for matching constraints. */ if (UNARY_P (op)) *************** init_cumulative_args (CUMULATIVE_ARGS *c *** 5747,5755 **** cum->nregs = 0; cum->sse_nregs = 0; cum->mmx_nregs = 0; ! cum->warn_avx = 0; ! cum->warn_sse = 0; ! cum->warn_mmx = 0; return; } --- 5726,5734 ---- cum->nregs = 0; cum->sse_nregs = 0; cum->mmx_nregs = 0; ! cum->warn_avx = false; ! cum->warn_sse = false; ! cum->warn_mmx = false; return; } *************** init_cumulative_args (CUMULATIVE_ARGS *c *** 5790,5799 **** The midde-end can't deal with the vector types > 16 bytes. In this case, we return the original mode and warn ABI change if CUM isn't ! NULL. */ static enum machine_mode ! type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum) { enum machine_mode mode = TYPE_MODE (type); --- 5769,5782 ---- The midde-end can't deal with the vector types > 16 bytes. In this case, we return the original mode and warn ABI change if CUM isn't ! NULL. ! ! If INT_RETURN is true, warn ABI change if the vector mode isn't ! available for function return value. */ static enum machine_mode ! type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum, ! bool in_return) { enum machine_mode mode = TYPE_MODE (type); *************** type_natural_mode (const_tree type, cons *** 5819,5851 **** if (size == 32 && !TARGET_AVX) { static bool warnedavx; ! if (cum ! && !warnedavx ! && cum->warn_avx) { ! warnedavx = true; ! warning (0, "AVX vector argument without AVX " ! "enabled changes the ABI"); } return TYPE_MODE (type); } ! else if ((size == 8 || size == 16) && !TARGET_SSE) { static bool warnedsse; ! if (cum ! && !warnedsse ! && cum->warn_sse) { ! warnedsse = true; ! warning (0, "SSE vector argument without SSE " ! "enabled changes the ABI"); } - return mode; } ! else ! return mode; } gcc_unreachable (); --- 5802,5862 ---- if (size == 32 && !TARGET_AVX) { static bool warnedavx; + static bool warnedavx_ret; ! if (cum && cum->warn_avx && !warnedavx) { ! if (warning (OPT_Wpsabi, "AVX vector argument " ! "without AVX enabled changes the ABI")) ! warnedavx = true; } + else if (in_return && !warnedavx_ret) + { + if (warning (OPT_Wpsabi, "AVX vector return " + "without AVX enabled changes the ABI")) + warnedavx_ret = true; + } + return TYPE_MODE (type); } ! else if (((size == 8 && TARGET_64BIT) || size == 16) ! && !TARGET_SSE) { static bool warnedsse; + static bool warnedsse_ret; ! if (cum && cum->warn_sse && !warnedsse) { ! if (warning (OPT_Wpsabi, "SSE vector argument " ! "without SSE enabled changes the ABI")) ! warnedsse = true; ! } ! else if (!TARGET_64BIT && in_return && !warnedsse_ret) ! { ! if (warning (OPT_Wpsabi, "SSE vector return " ! "without SSE enabled changes the ABI")) ! warnedsse_ret = true; } } ! else if ((size == 8 && !TARGET_64BIT) && !TARGET_MMX) ! { ! static bool warnedmmx; ! static bool warnedmmx_ret; ! ! if (cum && cum->warn_mmx && !warnedmmx) ! { ! if (warning (OPT_Wpsabi, "MMX vector argument " ! "without MMX enabled changes the ABI")) ! warnedmmx = true; ! } ! else if (in_return && !warnedmmx_ret) ! { ! if (warning (OPT_Wpsabi, "MMX vector return " ! "without MMX enabled changes the ABI")) ! warnedmmx_ret = true; ! } ! } ! return mode; } gcc_unreachable (); *************** classify_argument (enum machine_mode mod *** 6190,6214 **** case CHImode: case CQImode: { ! int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode); ! if (size <= 32) { classes[0] = X86_64_INTEGERSI_CLASS; return 1; } ! else if (size <= 64) { classes[0] = X86_64_INTEGER_CLASS; return 1; } ! else if (size <= 64+32) { classes[0] = X86_64_INTEGER_CLASS; classes[1] = X86_64_INTEGERSI_CLASS; return 2; } ! else if (size <= 64+64) { classes[0] = classes[1] = X86_64_INTEGER_CLASS; return 2; --- 6201,6228 ---- case CHImode: case CQImode: { ! int size = bit_offset + (int) GET_MODE_BITSIZE (mode); ! /* Analyze last 128 bits only. */ ! size = (size - 1) & 0x7f; ! ! if (size < 32) { classes[0] = X86_64_INTEGERSI_CLASS; return 1; } ! else if (size < 64) { classes[0] = X86_64_INTEGER_CLASS; return 1; } ! else if (size < 64+32) { classes[0] = X86_64_INTEGER_CLASS; classes[1] = X86_64_INTEGERSI_CLASS; return 2; } ! else if (size < 64+64) { classes[0] = classes[1] = X86_64_INTEGER_CLASS; return 2; *************** construct_container (enum machine_mode m *** 6475,6481 **** if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS && regclass[1] == X86_64_INTEGER_CLASS ! && (mode == CDImode || mode == TImode || mode == TFmode) && intreg[0] + 1 == intreg[1]) return gen_rtx_REG (mode, intreg[0]); --- 6489,6495 ---- if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS && regclass[1] == X86_64_INTEGER_CLASS ! && (mode == CDImode || mode == TImode) && intreg[0] + 1 == intreg[1]) return gen_rtx_REG (mode, intreg[0]); *************** ix86_function_arg_advance (cumulative_ar *** 6725,6731 **** words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; if (type) ! mode = type_natural_mode (type, NULL); if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) function_arg_advance_ms_64 (cum, bytes, words); --- 6739,6745 ---- words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; if (type) ! mode = type_natural_mode (type, NULL, false); if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) function_arg_advance_ms_64 (cum, bytes, words); *************** function_arg_32 (const CUMULATIVE_ARGS * *** 6753,6760 **** enum machine_mode orig_mode, const_tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words) { - static bool warnedsse, warnedmmx; - /* Avoid the AL settings for the Unix64 ABI. */ if (mode == VOIDmode) return constm1_rtx; --- 6767,6772 ---- *************** function_arg_32 (const CUMULATIVE_ARGS * *** 6811,6822 **** case V2DFmode: if (!type || !AGGREGATE_TYPE_P (type)) { - if (!TARGET_SSE && !warnedsse && cum->warn_sse) - { - warnedsse = true; - warning (0, "SSE vector argument without SSE enabled " - "changes the ABI"); - } if (cum->sse_nregs) return gen_reg_or_parallel (mode, orig_mode, cum->sse_regno + FIRST_SSE_REG); --- 6823,6828 ---- *************** function_arg_32 (const CUMULATIVE_ARGS * *** 6849,6860 **** case V1DImode: if (!type || !AGGREGATE_TYPE_P (type)) { - if (!TARGET_MMX && !warnedmmx && cum->warn_mmx) - { - warnedmmx = true; - warning (0, "MMX vector argument without MMX enabled " - "changes the ABI"); - } if (cum->mmx_nregs) return gen_reg_or_parallel (mode, orig_mode, cum->mmx_regno + FIRST_MMX_REG); --- 6855,6860 ---- *************** ix86_function_arg (cumulative_args_t cum *** 6977,6983 **** /* To simplify the code below, represent vector types with a vector mode even if MMX/SSE are not active. */ if (type && TREE_CODE (type) == VECTOR_TYPE) ! mode = type_natural_mode (type, cum); if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) arg = function_arg_ms_64 (cum, mode, omode, named, bytes); --- 6977,6983 ---- /* To simplify the code below, represent vector types with a vector mode even if MMX/SSE are not active. */ if (type && TREE_CODE (type) == VECTOR_TYPE) ! mode = type_natural_mode (type, cum, false); if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) arg = function_arg_ms_64 (cum, mode, omode, named, bytes); *************** ix86_function_value_regno_p (const unsig *** 7235,7243 **** switch (regno) { case AX_REG: return true; ! case FIRST_FLOAT_REG: /* TODO: The function should depend on current function ABI but builtins.c would need updating then. Therefore we use the default ABI. */ --- 7235,7249 ---- switch (regno) { case AX_REG: + case DX_REG: return true; + case DI_REG: + case SI_REG: + return TARGET_64BIT && ix86_abi != MS_ABI; ! /* Complex values are returned in %st(0)/%st(1) pair. */ ! case ST0_REG: ! case ST1_REG: /* TODO: The function should depend on current function ABI but builtins.c would need updating then. Therefore we use the default ABI. */ *************** ix86_function_value_regno_p (const unsig *** 7245,7254 **** return false; return TARGET_FLOAT_RETURNS_IN_80387; ! case FIRST_SSE_REG: return TARGET_SSE; ! case FIRST_MMX_REG: if (TARGET_MACHO || TARGET_64BIT) return false; return TARGET_MMX; --- 7251,7262 ---- return false; return TARGET_FLOAT_RETURNS_IN_80387; ! /* Complex values are returned in %xmm0/%xmm1 pair. */ ! case XMM0_REG: ! case XMM1_REG: return TARGET_SSE; ! case MM0_REG: if (TARGET_MACHO || TARGET_64BIT) return false; return TARGET_MMX; *************** ix86_function_value (const_tree valtype, *** 7420,7426 **** enum machine_mode mode, orig_mode; orig_mode = TYPE_MODE (valtype); ! mode = type_natural_mode (valtype, NULL); return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode); } --- 7428,7434 ---- enum machine_mode mode, orig_mode; orig_mode = TYPE_MODE (valtype); ! mode = type_natural_mode (valtype, NULL, true); return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode); } *************** ix86_return_in_memory (const_tree type, *** 7535,7541 **** #ifdef SUBTARGET_RETURN_IN_MEMORY return SUBTARGET_RETURN_IN_MEMORY (type, fntype); #else ! const enum machine_mode mode = type_natural_mode (type, NULL); if (TARGET_64BIT) { --- 7543,7549 ---- #ifdef SUBTARGET_RETURN_IN_MEMORY return SUBTARGET_RETURN_IN_MEMORY (type, fntype); #else ! const enum machine_mode mode = type_natural_mode (type, NULL, true); if (TARGET_64BIT) { *************** ix86_return_in_memory (const_tree type, *** 7549,7600 **** #endif } - /* When returning SSE vector types, we have a choice of either - (1) being abi incompatible with a -march switch, or - (2) generating an error. - Given no good solution, I think the safest thing is one warning. - The user won't be able to use -Werror, but.... - - Choose the STRUCT_VALUE_RTX hook because that's (at present) only - called in response to actually generating a caller or callee that - uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called - via aggregate_value_p for general type probing from tree-ssa. */ - - static rtx - ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED) - { - static bool warnedsse, warnedmmx; - - if (!TARGET_64BIT && type) - { - /* Look at the return type of the function, not the function type. */ - enum machine_mode mode = TYPE_MODE (TREE_TYPE (type)); - - if (!TARGET_SSE && !warnedsse) - { - if (mode == TImode - || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16)) - { - warnedsse = true; - warning (0, "SSE vector return without SSE enabled " - "changes the ABI"); - } - } - - if (!TARGET_MMX && !warnedmmx) - { - if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8) - { - warnedmmx = true; - warning (0, "MMX vector return without MMX enabled " - "changes the ABI"); - } - } - } - - return NULL; - } - /* Create the va_list data type. */ --- 7557,7562 ---- *************** ix86_gimplify_va_arg (tree valist, tree *** 8019,8025 **** size = int_size_in_bytes (type); rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; ! nat_mode = type_natural_mode (type, NULL); switch (nat_mode) { case V8SFmode: --- 7981,7987 ---- size = int_size_in_bytes (type); rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; ! nat_mode = type_natural_mode (type, NULL, false); switch (nat_mode) { case V8SFmode: *************** ix86_expand_prologue (void) *** 10560,10577 **** } m->fs.sp_offset += allocate; if (r10_live && eax_live) { ! t = choose_baseaddr (m->fs.sp_offset - allocate); emit_move_insn (gen_rtx_REG (word_mode, R10_REG), gen_frame_mem (word_mode, t)); ! t = choose_baseaddr (m->fs.sp_offset - allocate - UNITS_PER_WORD); emit_move_insn (gen_rtx_REG (word_mode, AX_REG), gen_frame_mem (word_mode, t)); } else if (eax_live || r10_live) { ! t = choose_baseaddr (m->fs.sp_offset - allocate); emit_move_insn (gen_rtx_REG (word_mode, (eax_live ? AX_REG : R10_REG)), gen_frame_mem (word_mode, t)); --- 10522,10541 ---- } m->fs.sp_offset += allocate; + /* Use stack_pointer_rtx for relative addressing so that code + works for realigned stack, too. */ if (r10_live && eax_live) { ! t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, eax); emit_move_insn (gen_rtx_REG (word_mode, R10_REG), gen_frame_mem (word_mode, t)); ! t = plus_constant (Pmode, t, UNITS_PER_WORD); emit_move_insn (gen_rtx_REG (word_mode, AX_REG), gen_frame_mem (word_mode, t)); } else if (eax_live || r10_live) { ! t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, eax); emit_move_insn (gen_rtx_REG (word_mode, (eax_live ? AX_REG : R10_REG)), gen_frame_mem (word_mode, t)); *************** ix86_expand_epilogue (int style) *** 11164,11171 **** m->fs.cfa_offset -= UNITS_PER_WORD; m->fs.sp_offset -= UNITS_PER_WORD; ! add_reg_note (insn, REG_CFA_ADJUST_CFA, ! copy_rtx (XVECEXP (PATTERN (insn), 0, 1))); add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (VOIDmode, ecx, pc_rtx)); RTX_FRAME_RELATED_P (insn) = 1; --- 11128,11136 ---- m->fs.cfa_offset -= UNITS_PER_WORD; m->fs.sp_offset -= UNITS_PER_WORD; ! rtx x = plus_constant (Pmode, stack_pointer_rtx, UNITS_PER_WORD); ! x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x); ! add_reg_note (insn, REG_CFA_ADJUST_CFA, x); add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (VOIDmode, ecx, pc_rtx)); RTX_FRAME_RELATED_P (insn) = 1; *************** ix86_live_on_entry (bitmap regs) *** 11561,11590 **** } } - /* Determine if op is suitable SUBREG RTX for address. */ - - static bool - ix86_address_subreg_operand (rtx op) - { - enum machine_mode mode; - - if (!REG_P (op)) - return false; - - mode = GET_MODE (op); - - if (GET_MODE_CLASS (mode) != MODE_INT) - return false; - - /* Don't allow SUBREGs that span more than a word. It can lead to spill - failures when the register is one word out of a two word structure. */ - if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) - return false; - - /* Allow only SUBREGs of non-eliminable hard registers. */ - return register_no_elim_operand (op, mode); - } - /* Extract the parts of an RTL expression that is a valid memory address for an instruction. Return 0 if the structure of the address is grossly off. Return -1 if the address contains ASHIFT, so it is not --- 11526,11531 ---- *************** ix86_decompose_address (rtx addr, struct *** 11641,11647 **** base = addr; else if (GET_CODE (addr) == SUBREG) { ! if (ix86_address_subreg_operand (SUBREG_REG (addr))) base = addr; else return 0; --- 11582,11588 ---- base = addr; else if (GET_CODE (addr) == SUBREG) { ! if (REG_P (SUBREG_REG (addr))) base = addr; else return 0; *************** ix86_decompose_address (rtx addr, struct *** 11705,11711 **** break; case SUBREG: ! if (!ix86_address_subreg_operand (SUBREG_REG (op))) return 0; /* FALLTHRU */ --- 11646,11652 ---- break; case SUBREG: ! if (!REG_P (SUBREG_REG (op))) return 0; /* FALLTHRU */ *************** ix86_decompose_address (rtx addr, struct *** 11750,11768 **** scale = 1 << scale; retval = -1; } - else if (CONST_INT_P (addr)) - { - if (!x86_64_immediate_operand (addr, VOIDmode)) - return 0; - - /* Constant addresses are sign extended to 64bit, we have to - prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */ - if (TARGET_X32 - && val_signbit_known_set_p (SImode, INTVAL (addr))) - return 0; - - disp = addr; - } else disp = addr; /* displacement */ --- 11691,11696 ---- *************** ix86_decompose_address (rtx addr, struct *** 11771,11788 **** if (REG_P (index)) ; else if (GET_CODE (index) == SUBREG ! && ix86_address_subreg_operand (SUBREG_REG (index))) ; else return 0; } - /* Address override works only on the (%reg) part of %fs:(%reg). */ - if (seg != SEG_DEFAULT - && ((base && GET_MODE (base) != word_mode) - || (index && GET_MODE (index) != word_mode))) - return 0; - /* Extract the integral value of scale. */ if (scale_rtx) { --- 11699,11710 ---- if (REG_P (index)) ; else if (GET_CODE (index) == SUBREG ! && REG_P (SUBREG_REG (index))) ; else return 0; } /* Extract the integral value of scale. */ if (scale_rtx) { *************** ix86_legitimize_reload_address (rtx x, *** 12258,12263 **** --- 12180,12224 ---- return false; } + /* Determine if op is suitable RTX for an address register. + Return naked register if a register or a register subreg is + found, otherwise return NULL_RTX. */ + + static rtx + ix86_validate_address_register (rtx op) + { + enum machine_mode mode = GET_MODE (op); + + /* Only SImode or DImode registers can form the address. */ + if (mode != SImode && mode != DImode) + return NULL_RTX; + + if (REG_P (op)) + return op; + else if (GET_CODE (op) == SUBREG) + { + rtx reg = SUBREG_REG (op); + + if (!REG_P (reg)) + return NULL_RTX; + + mode = GET_MODE (reg); + + /* Don't allow SUBREGs that span more than a word. It can + lead to spill failures when the register is one word out + of a two word structure. */ + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) + return NULL_RTX; + + /* Allow only SUBREGs of non-eliminable hard registers. */ + if (register_no_elim_operand (reg, mode)) + return reg; + } + + /* Op is not a register. */ + return NULL_RTX; + } + /* Recognizes RTL expressions that are valid memory addresses for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. *************** ix86_legitimate_address_p (enum machine_ *** 12273,12278 **** --- 12234,12240 ---- struct ix86_address parts; rtx base, index, disp; HOST_WIDE_INT scale; + enum ix86_address_seg seg; if (ix86_decompose_address (addr, &parts) <= 0) /* Decomposition failed. */ *************** ix86_legitimate_address_p (enum machine_ *** 12282,12302 **** index = parts.index; disp = parts.disp; scale = parts.scale; /* Validate base register. */ if (base) { ! rtx reg; ! ! if (REG_P (base)) ! reg = base; ! else if (GET_CODE (base) == SUBREG && REG_P (SUBREG_REG (base))) ! reg = SUBREG_REG (base); ! else ! /* Base is not a register. */ ! return false; ! if (GET_MODE (base) != SImode && GET_MODE (base) != DImode) return false; if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg)) --- 12244,12257 ---- index = parts.index; disp = parts.disp; scale = parts.scale; + seg = parts.seg; /* Validate base register. */ if (base) { ! rtx reg = ix86_validate_address_register (base); ! if (reg == NULL_RTX) return false; if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg)) *************** ix86_legitimate_address_p (enum machine_ *** 12308,12324 **** /* Validate index register. */ if (index) { ! rtx reg; ! ! if (REG_P (index)) ! reg = index; ! else if (GET_CODE (index) == SUBREG && REG_P (SUBREG_REG (index))) ! reg = SUBREG_REG (index); ! else ! /* Index is not a register. */ ! return false; ! if (GET_MODE (index) != SImode && GET_MODE (index) != DImode) return false; if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg)) --- 12263,12271 ---- /* Validate index register. */ if (index) { ! rtx reg = ix86_validate_address_register (index); ! if (reg == NULL_RTX) return false; if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg)) *************** ix86_legitimate_address_p (enum machine_ *** 12332,12337 **** --- 12279,12290 ---- && GET_MODE (base) != GET_MODE (index)) return false; + /* Address override works only on the (%reg) part of %fs:(%reg). */ + if (seg != SEG_DEFAULT + && ((base && GET_MODE (base) != word_mode) + || (index && GET_MODE (index) != word_mode))) + return false; + /* Validate scale factor. */ if (scale != 1) { *************** ix86_legitimate_address_p (enum machine_ *** 12453,12458 **** --- 12406,12417 ---- && !x86_64_immediate_operand (disp, VOIDmode)) /* Displacement is out of range. */ return false; + /* In x32 mode, constant addresses are sign extended to 64bit, so + we have to prevent addresses from 0x80000000 to 0xffffffff. */ + else if (TARGET_X32 && !(index || base) + && CONST_INT_P (disp) + && val_signbit_known_set_p (SImode, INTVAL (disp))) + return false; } /* Everything looks valid. */ *************** put_condition_code (enum rtx_code code, *** 13817,13824 **** Those same assemblers have the same but opposite lossage on cmov. */ if (mode == CCmode) suffix = fp ? "nbe" : "a"; - else if (mode == CCCmode) - suffix = "b"; else gcc_unreachable (); break; --- 13776,13781 ---- *************** put_condition_code (enum rtx_code code, *** 13840,13847 **** } break; case LTU: ! gcc_assert (mode == CCmode || mode == CCCmode); ! suffix = "b"; break; case GE: switch (mode) --- 13797,13808 ---- } break; case LTU: ! if (mode == CCmode) ! suffix = "b"; ! else if (mode == CCCmode) ! suffix = "c"; ! else ! gcc_unreachable (); break; case GE: switch (mode) *************** put_condition_code (enum rtx_code code, *** 13861,13880 **** } break; case GEU: ! /* ??? As above. */ ! gcc_assert (mode == CCmode || mode == CCCmode); ! suffix = fp ? "nb" : "ae"; break; case LE: gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode); suffix = "le"; break; case LEU: - /* ??? As above. */ if (mode == CCmode) suffix = "be"; - else if (mode == CCCmode) - suffix = fp ? "nb" : "ae"; else gcc_unreachable (); break; --- 13822,13841 ---- } break; case GEU: ! if (mode == CCmode) ! suffix = fp ? "nb" : "ae"; ! else if (mode == CCCmode) ! suffix = "nc"; ! else ! gcc_unreachable (); break; case LE: gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode); suffix = "le"; break; case LEU: if (mode == CCmode) suffix = "be"; else gcc_unreachable (); break; *************** ix86_avx_u128_mode_needed (rtx insn) *** 15340,15346 **** rtx arg = XEXP (XEXP (link, 0), 0); if (ix86_check_avx256_register (&arg, NULL)) ! return AVX_U128_ANY; } } --- 15301,15307 ---- rtx arg = XEXP (XEXP (link, 0), 0); if (ix86_check_avx256_register (&arg, NULL)) ! return AVX_U128_DIRTY; } } *************** ix86_avx_u128_mode_after (int mode, rtx *** 15460,15467 **** { bool avx_reg256_found = false; note_stores (pat, ix86_check_avx256_stores, &avx_reg256_found); ! if (!avx_reg256_found) ! return AVX_U128_CLEAN; } /* Otherwise, return current mode. Remember that if insn --- 15421,15428 ---- { bool avx_reg256_found = false; note_stores (pat, ix86_check_avx256_stores, &avx_reg256_found); ! ! return avx_reg256_found ? AVX_U128_DIRTY : AVX_U128_CLEAN; } /* Otherwise, return current mode. Remember that if insn *************** ix86_avoid_lea_for_addr (rtx insn, rtx o *** 17350,17357 **** if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun)) return false; ! /* Check it is correct to split here. */ ! if (!ix86_ok_to_clobber_flags(insn)) return false; ok = ix86_decompose_address (operands[1], &parts); --- 17311,17328 ---- if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun)) return false; ! /* The "at least two components" test below might not catch simple ! move or zero extension insns if parts.base is non-NULL and parts.disp ! is const0_rtx as the only components in the address, e.g. if the ! register is %rbp or %r13. As this test is much cheaper and moves or ! zero extensions are the common case, do this check first. */ ! if (REG_P (operands[1]) ! || (SImode_address_operand (operands[1], VOIDmode) ! && REG_P (XEXP (operands[1], 0)))) ! return false; ! ! /* Check if it is OK to split here. */ ! if (!ix86_ok_to_clobber_flags (insn)) return false; ok = ix86_decompose_address (operands[1], &parts); *************** ix86_cc_mode (enum rtx_code code, rtx op *** 18486,18497 **** return CCmode; case GTU: /* CF=0 & ZF=0 */ case LEU: /* CF=1 | ZF=1 */ ! /* Detect overflow checks. They need just the carry flag. */ ! if (GET_CODE (op0) == MINUS ! && rtx_equal_p (op1, XEXP (op0, 0))) ! return CCCmode; ! else ! return CCmode; /* Codes possibly doable only with sign flag when comparing against zero. */ case GE: /* SF=OF or SF=0 */ --- 18457,18463 ---- return CCmode; case GTU: /* CF=0 & ZF=0 */ case LEU: /* CF=1 | ZF=1 */ ! return CCmode; /* Codes possibly doable only with sign flag when comparing against zero. */ case GE: /* SF=OF or SF=0 */ *************** ix86_expand_vec_perm (rtx operands[]) *** 20500,20506 **** return; case V8SFmode: ! mask = gen_lowpart (V8SFmode, mask); if (one_operand_shuffle) emit_insn (gen_avx2_permvarv8sf (target, op0, mask)); else --- 20466,20472 ---- return; case V8SFmode: ! mask = gen_lowpart (V8SImode, mask); if (one_operand_shuffle) emit_insn (gen_avx2_permvarv8sf (target, op0, mask)); else *************** counter_mode (rtx count_exp) *** 21740,21745 **** --- 21706,21726 ---- return SImode; } + /* Copy the address to a Pmode register. This is used for x32 to + truncate DImode TLS address to a SImode register. */ + + static rtx + ix86_copy_addr_to_reg (rtx addr) + { + if (GET_MODE (addr) == Pmode || GET_MODE (addr) == VOIDmode) + return copy_addr_to_reg (addr); + else + { + gcc_assert (GET_MODE (addr) == DImode && Pmode == SImode); + return gen_rtx_SUBREG (SImode, copy_to_mode_reg (DImode, addr), 0); + } + } + /* When SRCPTR is non-NULL, output simple loop to move memory pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT specified in bytes. When SRCPTR is NULL, output the *************** ix86_expand_movmem (rtx dst, rtx src, rt *** 22728,22735 **** gcc_assert (alg != no_stringop); if (!count) count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp); ! destreg = copy_addr_to_reg (XEXP (dst, 0)); ! srcreg = copy_addr_to_reg (XEXP (src, 0)); switch (alg) { case libcall: --- 22709,22716 ---- gcc_assert (alg != no_stringop); if (!count) count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp); ! destreg = ix86_copy_addr_to_reg (XEXP (dst, 0)); ! srcreg = ix86_copy_addr_to_reg (XEXP (src, 0)); switch (alg) { case libcall: *************** ix86_expand_setmem (rtx dst, rtx count_e *** 23119,23125 **** gcc_assert (alg != no_stringop); if (!count) count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp); ! destreg = copy_addr_to_reg (XEXP (dst, 0)); switch (alg) { case libcall: --- 23100,23106 ---- gcc_assert (alg != no_stringop); if (!count) count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp); ! destreg = ix86_copy_addr_to_reg (XEXP (dst, 0)); switch (alg) { case libcall: *************** ix86_constant_alignment (tree exp, int a *** 24988,24994 **** int ix86_data_alignment (tree type, int align) { ! int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT); if (AGGREGATE_TYPE_P (type) && TYPE_SIZE (type) --- 24969,24976 ---- int ix86_data_alignment (tree type, int align) { ! int max_align ! = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT); if (AGGREGATE_TYPE_P (type) && TYPE_SIZE (type) *************** static const struct builtin_description *** 27984,27991 **** { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI }, ! { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF }, ! { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 }, --- 27966,27973 ---- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI }, ! { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF }, ! { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 }, *************** ix86_expand_args_builtin (const struct b *** 31245,31255 **** static rtx ix86_expand_special_args_builtin (const struct builtin_description *d, ! tree exp, rtx target) { tree arg; rtx pat, op; unsigned int i, nargs, arg_adjust, memory; struct { rtx op; --- 31227,31238 ---- static rtx ix86_expand_special_args_builtin (const struct builtin_description *d, ! tree exp, rtx target) { tree arg; rtx pat, op; unsigned int i, nargs, arg_adjust, memory; + bool aligned_mem = false; struct { rtx op; *************** ix86_expand_special_args_builtin (const *** 31295,31300 **** --- 31278,31292 ---- nargs = 1; klass = load; memory = 0; + switch (icode) + { + case CODE_FOR_sse4_1_movntdqa: + case CODE_FOR_avx2_movntdqa: + aligned_mem = true; + break; + default: + break; + } break; case VOID_FTYPE_PV2SF_V4SF: case VOID_FTYPE_PV4DI_V4DI: *************** ix86_expand_special_args_builtin (const *** 31312,31317 **** --- 31304,31329 ---- klass = store; /* Reserve memory operand for target. */ memory = ARRAY_SIZE (args); + switch (icode) + { + /* These builtins and instructions require the memory + to be properly aligned. */ + case CODE_FOR_avx_movntv4di: + case CODE_FOR_sse2_movntv2di: + case CODE_FOR_avx_movntv8sf: + case CODE_FOR_sse_movntv4sf: + case CODE_FOR_sse4a_vmmovntv4sf: + case CODE_FOR_avx_movntv4df: + case CODE_FOR_sse2_movntv2df: + case CODE_FOR_sse4a_vmmovntv2df: + case CODE_FOR_sse2_movntidi: + case CODE_FOR_sse_movntq: + case CODE_FOR_sse2_movntisi: + aligned_mem = true; + break; + default: + break; + } break; case V4SF_FTYPE_V4SF_PCV2SF: case V2DF_FTYPE_V2DF_PCDOUBLE: *************** ix86_expand_special_args_builtin (const *** 31368,31373 **** --- 31380,31396 ---- { op = force_reg (Pmode, convert_to_mode (Pmode, op, 1)); target = gen_rtx_MEM (tmode, op); + /* target at this point has just BITS_PER_UNIT MEM_ALIGN + on it. Try to improve it using get_pointer_alignment, + and if the special builtin is one that requires strict + mode alignment, also from it's GET_MODE_ALIGNMENT. + Failure to do so could lead to ix86_legitimate_combined_insn + rejecting all changes to such insns. */ + unsigned int align = get_pointer_alignment (arg); + if (aligned_mem && align < GET_MODE_ALIGNMENT (tmode)) + align = GET_MODE_ALIGNMENT (tmode); + if (MEM_ALIGN (target) < align) + set_mem_align (target, align); } else target = force_reg (tmode, op); *************** ix86_expand_special_args_builtin (const *** 31413,31420 **** /* This must be the memory operand. */ op = force_reg (Pmode, convert_to_mode (Pmode, op, 1)); op = gen_rtx_MEM (mode, op); ! gcc_assert (GET_MODE (op) == mode ! || GET_MODE (op) == VOIDmode); } else { --- 31436,31452 ---- /* This must be the memory operand. */ op = force_reg (Pmode, convert_to_mode (Pmode, op, 1)); op = gen_rtx_MEM (mode, op); ! /* op at this point has just BITS_PER_UNIT MEM_ALIGN ! on it. Try to improve it using get_pointer_alignment, ! and if the special builtin is one that requires strict ! mode alignment, also from it's GET_MODE_ALIGNMENT. ! Failure to do so could lead to ix86_legitimate_combined_insn ! rejecting all changes to such insns. */ ! unsigned int align = get_pointer_alignment (arg); ! if (aligned_mem && align < GET_MODE_ALIGNMENT (mode)) ! align = GET_MODE_ALIGNMENT (mode); ! if (MEM_ALIGN (op) < align) ! set_mem_align (op, align); } else { *************** rdrand_step: *** 32027,32033 **** else op2 = gen_rtx_SUBREG (SImode, op0, 0); ! if (target == 0) target = gen_reg_rtx (SImode); pat = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG), --- 32059,32066 ---- else op2 = gen_rtx_SUBREG (SImode, op0, 0); ! if (target == 0 ! || !register_operand (target, SImode)) target = gen_reg_rtx (SImode); pat = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG), *************** rdseed_step: *** 32069,32075 **** const0_rtx); emit_insn (gen_rtx_SET (VOIDmode, op2, pat)); ! if (target == 0) target = gen_reg_rtx (SImode); emit_insn (gen_zero_extendqisi2 (target, op2)); --- 32102,32109 ---- const0_rtx); emit_insn (gen_rtx_SET (VOIDmode, op2, pat)); ! if (target == 0 ! || !register_operand (target, SImode)) target = gen_reg_rtx (SImode); emit_insn (gen_zero_extendqisi2 (target, op2)); *************** addcarryx: *** 32208,32214 **** mode4 = insn_data[icode].operand[5].mode; if (target == NULL_RTX ! || GET_MODE (target) != insn_data[icode].operand[0].mode) subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); else subtarget = target; --- 32242,32250 ---- mode4 = insn_data[icode].operand[5].mode; if (target == NULL_RTX ! || GET_MODE (target) != insn_data[icode].operand[0].mode ! || !insn_data[icode].operand[0].predicate (target, ! GET_MODE (target))) subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); else subtarget = target; *************** ix86_hard_regno_mode_ok (int regno, enum *** 33879,33888 **** { /* We implement the move patterns for all vector modes into and out of SSE registers, even when no operation instructions ! are available. OImode move is available only when AVX is ! enabled. */ ! return ((TARGET_AVX && mode == OImode) ! || VALID_AVX256_REG_MODE (mode) || VALID_SSE_REG_MODE (mode) || VALID_SSE2_REG_MODE (mode) || VALID_MMX_REG_MODE (mode) --- 33915,33924 ---- { /* We implement the move patterns for all vector modes into and out of SSE registers, even when no operation instructions ! are available. OImode and AVX modes are available only when ! AVX is enabled. */ ! return ((TARGET_AVX ! && VALID_AVX256_REG_OR_OI_MODE (mode)) || VALID_SSE_REG_MODE (mode) || VALID_SSE2_REG_MODE (mode) || VALID_MMX_REG_MODE (mode) *************** x86_output_mi_thunk (FILE *file, *** 35020,35026 **** { tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOTPCREL); tmp = gen_rtx_CONST (Pmode, tmp); ! fnaddr = gen_rtx_MEM (Pmode, tmp); } } else --- 35056,35062 ---- { tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOTPCREL); tmp = gen_rtx_CONST (Pmode, tmp); ! fnaddr = gen_const_mem (Pmode, tmp); } } else *************** x86_output_mi_thunk (FILE *file, *** 35040,35047 **** output_set_got (tmp, NULL_RTX); fnaddr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOT); ! fnaddr = gen_rtx_PLUS (Pmode, fnaddr, tmp); ! fnaddr = gen_rtx_MEM (Pmode, fnaddr); } } --- 35076,35084 ---- output_set_got (tmp, NULL_RTX); fnaddr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOT); ! fnaddr = gen_rtx_CONST (Pmode, fnaddr); ! fnaddr = gen_rtx_PLUS (Pmode, tmp, fnaddr); ! fnaddr = gen_const_mem (Pmode, fnaddr); } } *************** ix86_avoid_jump_mispredicts (void) *** 35232,35238 **** The smallest offset in the page INSN can start is the case where START ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN). We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN). ! */ for (insn = start; insn; insn = NEXT_INSN (insn)) { int min_size; --- 35269,35278 ---- The smallest offset in the page INSN can start is the case where START ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN). We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN). ! ! Don't consider asm goto as jump, while it can contain a jump, it doesn't ! have to, control transfer to label(s) can be performed through other ! means, and also we estimate minimum length of all asm stmts as 0. */ for (insn = start; insn; insn = NEXT_INSN (insn)) { int min_size; *************** ix86_avoid_jump_mispredicts (void) *** 35260,35265 **** --- 35300,35306 ---- { start = NEXT_INSN (start); if ((JUMP_P (start) + && asm_noperands (PATTERN (start)) < 0 && GET_CODE (PATTERN (start)) != ADDR_VEC && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC) || CALL_P (start)) *************** ix86_avoid_jump_mispredicts (void) *** 35278,35283 **** --- 35319,35325 ---- fprintf (dump_file, "Insn %i estimated to %i bytes\n", INSN_UID (insn), min_size); if ((JUMP_P (insn) + && asm_noperands (PATTERN (insn)) < 0 && GET_CODE (PATTERN (insn)) != ADDR_VEC && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) || CALL_P (insn)) *************** ix86_avoid_jump_mispredicts (void) *** 35289,35294 **** --- 35331,35337 ---- { start = NEXT_INSN (start); if ((JUMP_P (start) + && asm_noperands (PATTERN (start)) < 0 && GET_CODE (PATTERN (start)) != ADDR_VEC && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC) || CALL_P (start)) *************** expand_vec_perm_interleave2 (struct expa *** 39371,39377 **** else dfinal.perm[i] = e; } ! dfinal.op0 = gen_reg_rtx (dfinal.vmode); dfinal.op1 = dfinal.op0; dfinal.one_operand_p = true; dremap.target = dfinal.op0; --- 39414,39422 ---- else dfinal.perm[i] = e; } ! ! if (!d->testing_p) ! dfinal.op0 = gen_reg_rtx (dfinal.vmode); dfinal.op1 = dfinal.op0; dfinal.one_operand_p = true; dremap.target = dfinal.op0; *************** expand_vec_perm_pshufb2 (struct expand_v *** 39806,39811 **** --- 39851,39859 ---- return false; gcc_assert (!d->one_operand_p); + if (d->testing_p) + return true; + nelt = d->nelt; eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode)); *************** expand_vec_perm_even_odd_1 (struct expan *** 40005,40010 **** --- 40053,40060 ---- switch (d->vmode) { case V4DFmode: + if (d->testing_p) + break; t1 = gen_reg_rtx (V4DFmode); t2 = gen_reg_rtx (V4DFmode); *************** expand_vec_perm_even_odd_1 (struct expan *** 40024,40029 **** --- 40074,40081 ---- { int mask = odd ? 0xdd : 0x88; + if (d->testing_p) + break; t1 = gen_reg_rtx (V8SFmode); t2 = gen_reg_rtx (V8SFmode); t3 = gen_reg_rtx (V8SFmode); *************** expand_vec_perm_even_odd_1 (struct expan *** 40065,40070 **** --- 40117,40124 ---- return expand_vec_perm_pshufb2 (d); else { + if (d->testing_p) + break; /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */ t1 = gen_reg_rtx (V8HImode); *************** expand_vec_perm_even_odd_1 (struct expan *** 40086,40091 **** --- 40140,40147 ---- return expand_vec_perm_pshufb2 (d); else { + if (d->testing_p) + break; t1 = gen_reg_rtx (V16QImode); t2 = gen_reg_rtx (V16QImode); t3 = gen_reg_rtx (V16QImode); *************** expand_vec_perm_even_odd_1 (struct expan *** 40118,40123 **** --- 40174,40182 ---- return expand_vec_perm_even_odd_1 (&d_copy, odd); } + if (d->testing_p) + break; + t1 = gen_reg_rtx (V4DImode); t2 = gen_reg_rtx (V4DImode); *************** expand_vec_perm_even_odd_1 (struct expan *** 40144,40149 **** --- 40203,40211 ---- return expand_vec_perm_even_odd_1 (&d_copy, odd); } + if (d->testing_p) + break; + t1 = gen_reg_rtx (V8SImode); t2 = gen_reg_rtx (V8SImode); *************** expand_vec_perm_broadcast_1 (struct expa *** 40236,40241 **** --- 40298,40305 ---- case V16QImode: /* These can be implemented via interleave. We save one insn by stopping once we have promoted to V4SImode and then use pshufd. */ + if (d->testing_p) + return true; do { rtx dest; *************** ix86_memmodel_check (unsigned HOST_WIDE_ *** 42473,42480 **** #undef TARGET_PROMOTE_PROTOTYPES #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true - #undef TARGET_STRUCT_VALUE_RTX - #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx #undef TARGET_SETUP_INCOMING_VARARGS #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs #undef TARGET_MUST_PASS_IN_STACK --- 42537,42542 ---- diff -Nrcpad gcc-4.8.2/gcc/config/i386/i386.h gcc-4.8.3/gcc/config/i386/i386.h *** gcc-4.8.2/gcc/config/i386/i386.h Mon Jan 28 20:42:55 2013 --- gcc-4.8.3/gcc/config/i386/i386.h Wed Jan 8 19:54:29 2014 *************** extern const struct processor_costs ix86 *** 197,206 **** /* Macros used in the machine description to test the flags. */ ! /* configure can arrange to make this 2, to force a 486. */ #ifndef TARGET_CPU_DEFAULT ! #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic #endif #ifndef TARGET_FPMATH_DEFAULT --- 197,206 ---- /* Macros used in the machine description to test the flags. */ ! /* configure can arrange to change it. */ #ifndef TARGET_CPU_DEFAULT ! #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC32 #endif #ifndef TARGET_FPMATH_DEFAULT *************** extern const char *host_detect_local_cpu *** 591,633 **** /* Target Pragmas. */ #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () - enum target_cpu_default - { - TARGET_CPU_DEFAULT_generic = 0, - - TARGET_CPU_DEFAULT_i386, - TARGET_CPU_DEFAULT_i486, - TARGET_CPU_DEFAULT_pentium, - TARGET_CPU_DEFAULT_pentium_mmx, - TARGET_CPU_DEFAULT_pentiumpro, - TARGET_CPU_DEFAULT_pentium2, - TARGET_CPU_DEFAULT_pentium3, - TARGET_CPU_DEFAULT_pentium4, - TARGET_CPU_DEFAULT_pentium_m, - TARGET_CPU_DEFAULT_prescott, - TARGET_CPU_DEFAULT_nocona, - TARGET_CPU_DEFAULT_core2, - TARGET_CPU_DEFAULT_corei7, - TARGET_CPU_DEFAULT_haswell, - TARGET_CPU_DEFAULT_atom, - - TARGET_CPU_DEFAULT_geode, - TARGET_CPU_DEFAULT_k6, - TARGET_CPU_DEFAULT_k6_2, - TARGET_CPU_DEFAULT_k6_3, - TARGET_CPU_DEFAULT_athlon, - TARGET_CPU_DEFAULT_athlon_sse, - TARGET_CPU_DEFAULT_k8, - TARGET_CPU_DEFAULT_amdfam10, - TARGET_CPU_DEFAULT_bdver1, - TARGET_CPU_DEFAULT_bdver2, - TARGET_CPU_DEFAULT_bdver3, - TARGET_CPU_DEFAULT_btver1, - TARGET_CPU_DEFAULT_btver2, - - TARGET_CPU_DEFAULT_max - }; - #ifndef CC1_SPEC #define CC1_SPEC "%(cc1_cpu) " #endif --- 591,596 ---- *************** do { \ *** 2089,2120 **** with x86-64 medium memory model */ #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 ! /* Which processor to tune code generation for. */ enum processor_type { ! PROCESSOR_I386 = 0, /* 80386 */ PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO, - PROCESSOR_GEODE, - PROCESSOR_K6, - PROCESSOR_ATHLON, PROCESSOR_PENTIUM4, - PROCESSOR_K8, PROCESSOR_NOCONA, PROCESSOR_CORE2, PROCESSOR_COREI7, PROCESSOR_HASWELL, ! PROCESSOR_GENERIC32, ! PROCESSOR_GENERIC64, PROCESSOR_AMDFAM10, PROCESSOR_BDVER1, PROCESSOR_BDVER2, PROCESSOR_BDVER3, PROCESSOR_BTVER1, PROCESSOR_BTVER2, - PROCESSOR_ATOM, PROCESSOR_max }; --- 2052,2084 ---- with x86-64 medium memory model */ #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 ! /* Which processor to tune code generation for. These must be in sync ! with processor_target_table in i386.c. */ enum processor_type { ! PROCESSOR_GENERIC32 = 0, ! PROCESSOR_GENERIC64, ! PROCESSOR_I386, /* 80386 */ PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, PROCESSOR_CORE2, PROCESSOR_COREI7, PROCESSOR_HASWELL, ! PROCESSOR_ATOM, ! PROCESSOR_GEODE, ! PROCESSOR_K6, ! PROCESSOR_ATHLON, ! PROCESSOR_K8, PROCESSOR_AMDFAM10, PROCESSOR_BDVER1, PROCESSOR_BDVER2, PROCESSOR_BDVER3, PROCESSOR_BTVER1, PROCESSOR_BTVER2, PROCESSOR_max }; diff -Nrcpad gcc-4.8.2/gcc/config/i386/i386.md gcc-4.8.3/gcc/config/i386/i386.md *** gcc-4.8.2/gcc/config/i386/i386.md Tue Aug 13 12:45:06 2013 --- gcc-4.8.3/gcc/config/i386/i386.md Fri Feb 14 17:37:50 2014 *************** *** 363,368 **** --- 363,375 ---- (const_string "unknown")] (const_string "integer"))) + ;; The minimum required alignment of vector mode memory operands of the SSE + ;; (non-VEX/EVEX) instruction in bits, if it is different from + ;; GET_MODE_ALIGNMENT of the operand, otherwise 0. If an instruction has + ;; multiple alternatives, this should be conservative maximum of those minimum + ;; required alignments. + (define_attr "ssememalign" "" (const_int 0)) + ;; The (bounding maximum) length of an instruction immediate. (define_attr "length_immediate" "" (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave, *************** *** 1570,1576 **** split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]); operands[1] = gen_lowpart (DImode, operands[2]); ! operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx, GEN_INT (4))); }) --- 1577,1583 ---- split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]); operands[1] = gen_lowpart (DImode, operands[2]); ! operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (4))); }) *************** *** 1587,1593 **** split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]); operands[1] = gen_lowpart (DImode, operands[2]); ! operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx, GEN_INT (4))); }) --- 1594,1600 ---- split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]); operands[1] = gen_lowpart (DImode, operands[2]); ! operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (4))); }) *************** *** 2715,2721 **** "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2))) (set (mem:SF (reg:P SP_REG)) (match_dup 1))] ! "operands[2] = GEN_INT (-GET_MODE_SIZE (mode));") (define_split [(set (match_operand:SF 0 "push_operand") --- 2722,2741 ---- "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2))) (set (mem:SF (reg:P SP_REG)) (match_dup 1))] ! { ! rtx op = XEXP (operands[0], 0); ! if (GET_CODE (op) == PRE_DEC) ! { ! gcc_assert (!TARGET_64BIT); ! op = GEN_INT (-4); ! } ! else ! { ! op = XEXP (XEXP (op, 1), 1); ! gcc_assert (CONST_INT_P (op)); ! } ! operands[2] = op; ! }) (define_split [(set (match_operand:SF 0 "push_operand") *************** *** 5443,5448 **** --- 5463,5474 ---- mode = SImode; ix86_split_lea_for_addr (curr_insn, operands, mode); + + /* Zero-extend return register to DImode for zero-extended addresses. */ + if (mode != mode) + emit_insn (gen_zero_extendsidi2 + (operands[0], gen_lowpart (mode, operands[0]))); + DONE; } [(set_attr "type" "lea") *************** *** 6589,6595 **** (set_attr "use_carry" "1") (set_attr "mode" "")]) ! ;; Overflow setting add and subtract instructions (define_insn "*add3_cconly_overflow" [(set (reg:CCC FLAGS_REG) --- 6615,6621 ---- (set_attr "use_carry" "1") (set_attr "mode" "")]) ! ;; Overflow setting add instructions (define_insn "*add3_cconly_overflow" [(set (reg:CCC FLAGS_REG) *************** *** 6604,6646 **** [(set_attr "type" "alu") (set_attr "mode" "")]) ! (define_insn "*sub3_cconly_overflow" ! [(set (reg:CCC FLAGS_REG) ! (compare:CCC ! (minus:SWI ! (match_operand:SWI 0 "nonimmediate_operand" "m,") ! (match_operand:SWI 1 "" ",m")) ! (match_dup 0)))] ! "" ! "cmp{}\t{%1, %0|%0, %1}" ! [(set_attr "type" "icmp") ! (set_attr "mode" "")]) ! ! (define_insn "*3_cc_overflow" [(set (reg:CCC FLAGS_REG) (compare:CCC ! (plusminus:SWI ! (match_operand:SWI 1 "nonimmediate_operand" "0,0") (match_operand:SWI 2 "" ",m")) (match_dup 1))) (set (match_operand:SWI 0 "nonimmediate_operand" "=m,") ! (plusminus:SWI (match_dup 1) (match_dup 2)))] ! "ix86_binary_operator_ok (, mode, operands)" ! "{}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "")]) ! (define_insn "*si3_zext_cc_overflow" [(set (reg:CCC FLAGS_REG) (compare:CCC ! (plusminus:SI ! (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:SI 2 "x86_64_general_operand" "rme")) (match_dup 1))) (set (match_operand:DI 0 "register_operand" "=r") ! (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))] ! "TARGET_64BIT && ix86_binary_operator_ok (, SImode, operands)" ! "{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") (set_attr "mode" "SI")]) --- 6630,6660 ---- [(set_attr "type" "alu") (set_attr "mode" "")]) ! (define_insn "*add3_cc_overflow" [(set (reg:CCC FLAGS_REG) (compare:CCC ! (plus:SWI ! (match_operand:SWI 1 "nonimmediate_operand" "%0,0") (match_operand:SWI 2 "" ",m")) (match_dup 1))) (set (match_operand:SWI 0 "nonimmediate_operand" "=m,") ! (plus:SWI (match_dup 1) (match_dup 2)))] ! "ix86_binary_operator_ok (PLUS, mode, operands)" ! "add{}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "")]) ! (define_insn "*addsi3_zext_cc_overflow" [(set (reg:CCC FLAGS_REG) (compare:CCC ! (plus:SI ! (match_operand:SI 1 "nonimmediate_operand" "%0") (match_operand:SI 2 "x86_64_general_operand" "rme")) (match_dup 1))) (set (match_operand:DI 0 "register_operand" "=r") ! (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] ! "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" ! "add{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") (set_attr "mode" "SI")]) *************** *** 8012,8018 **** (const_int 0))) (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm") (and:DI (match_dup 1) (match_dup 2)))] ! "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) && ix86_binary_operator_ok (AND, DImode, operands)" "@ and{l}\t{%k2, %k0|%k0, %k2} --- 8026,8043 ---- (const_int 0))) (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm") (and:DI (match_dup 1) (match_dup 2)))] ! "TARGET_64BIT ! && ix86_match_ccmode ! (insn, ! /* If we are going to emit andl instead of andq, and the operands[2] ! constant might have the SImode sign bit set, make sure the sign ! flag isn't tested, because the instruction will set the sign flag ! based on bit 31 rather than bit 63. If it isn't CONST_INT, ! conservatively assume it might have bit 31 set. */ ! (satisfies_constraint_Z (operands[2]) ! && (!CONST_INT_P (operands[2]) ! || val_signbit_known_set_p (SImode, INTVAL (operands[2])))) ! ? CCZmode : CCNOmode) && ix86_binary_operator_ok (AND, DImode, operands)" "@ and{l}\t{%k2, %k0|%k0, %k2} *************** *** 17569,17575 **** (define_insn "trap" [(trap_if (const_int 1) (const_int 6))] "" ! { return ASM_SHORT "0x0b0f"; } [(set_attr "length" "2")]) (define_expand "prefetch" --- 17594,17606 ---- (define_insn "trap" [(trap_if (const_int 1) (const_int 6))] "" ! { ! #ifdef HAVE_AS_IX86_UD2 ! return "ud2"; ! #else ! return ASM_SHORT "0x0b0f"; ! #endif ! } [(set_attr "length" "2")]) (define_expand "prefetch" diff -Nrcpad gcc-4.8.2/gcc/config/i386/sse.md gcc-4.8.3/gcc/config/i386/sse.md *** gcc-4.8.2/gcc/config/i386/sse.md Wed Aug 14 14:09:59 2013 --- gcc-4.8.3/gcc/config/i386/sse.md Thu Feb 13 22:30:26 2014 *************** *** 605,610 **** --- 605,611 ---- } [(set_attr "type" "ssemov") (set_attr "movu" "1") + (set_attr "ssememalign" "8") (set_attr "prefix" "maybe_vex") (set (attr "mode") (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") *************** *** 634,639 **** --- 635,641 ---- } [(set_attr "type" "ssemov") (set_attr "movu" "1") + (set_attr "ssememalign" "8") (set_attr "prefix" "maybe_vex") (set (attr "mode") (cond [(ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") *************** *** 663,668 **** --- 665,671 ---- } [(set_attr "type" "ssemov") (set_attr "movu" "1") + (set_attr "ssememalign" "8") (set (attr "prefix_data16") (if_then_else (match_test "TARGET_AVX") *************** *** 696,701 **** --- 699,705 ---- } [(set_attr "type" "ssemov") (set_attr "movu" "1") + (set_attr "ssememalign" "8") (set (attr "prefix_data16") (if_then_else (match_test "TARGET_AVX") *************** *** 721,726 **** --- 725,731 ---- "%vlddqu\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "movu" "1") + (set_attr "ssememalign" "8") (set (attr "prefix_data16") (if_then_else (match_test "TARGET_AVX") *************** *** 1001,1006 **** --- 1006,1012 ---- vrcpss\t{%1, %2, %0|%0, %2, %1}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sse") + (set_attr "ssememalign" "32") (set_attr "atom_sse_attr" "rcp") (set_attr "btver2_sse_attr" "rcp") (set_attr "prefix" "orig,vex") *************** *** 1089,1094 **** --- 1095,1101 ---- vrsqrtss\t{%1, %2, %0|%0, %2, %1}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sse") + (set_attr "ssememalign" "32") (set_attr "prefix" "orig,vex") (set_attr "mode" "SF")]) *************** *** 2844,2849 **** --- 2851,2857 ---- "%vcvtdq2pd\t{%1, %0|%0, %q1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "maybe_vex") + (set_attr "ssememalign" "64") (set_attr "mode" "V2DF")]) (define_insn "avx_cvtpd2dq256" *************** *** 3572,3577 **** --- 3580,3586 ---- %vmovhps\t{%2, %0|%0, %2}" [(set_attr "isa" "noavx,avx,noavx,avx,*") (set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix" "orig,vex,orig,vex,maybe_vex") (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")]) *************** *** 3617,3622 **** --- 3626,3632 ---- %vmovlps\t{%2, %H0|%H0, %2}" [(set_attr "isa" "noavx,avx,noavx,avx,*") (set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix" "orig,vex,orig,vex,maybe_vex") (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")]) *************** *** 3941,3946 **** --- 3951,3957 ---- %vmovhlps\t{%1, %d0|%d0, %1} %vmovlps\t{%H1, %d0|%d0, %H1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix" "maybe_vex") (set_attr "mode" "V2SF,V4SF,V2SF")]) *************** *** 3980,3985 **** --- 3991,3997 ---- %vmovlps\t{%2, %H0|%H0, %2}" [(set_attr "isa" "noavx,avx,noavx,avx,*") (set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix" "orig,vex,orig,vex,maybe_vex") (set_attr "mode" "V2SF,V2SF,V4SF,V4SF,V2SF")]) *************** *** 4033,4038 **** --- 4045,4051 ---- %vmovlps\t{%2, %0|%0, %2}" [(set_attr "isa" "noavx,avx,noavx,avx,*") (set_attr "type" "sseshuf,sseshuf,ssemov,ssemov,ssemov") + (set_attr "ssememalign" "64") (set_attr "length_immediate" "1,1,*,*,*") (set_attr "prefix" "orig,vex,orig,vex,maybe_vex") (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")]) *************** *** 4642,4648 **** vmovlpd\t{%H1, %2, %0|%0, %2, %H1} %vmovhpd\t{%1, %0|%0, %1}" [(set_attr "isa" "noavx,avx,sse3,noavx,avx,*") ! (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov") (set_attr "prefix_data16" "*,*,*,1,*,1") (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex") (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")]) --- 4655,4662 ---- vmovlpd\t{%H1, %2, %0|%0, %2, %H1} %vmovhpd\t{%1, %0|%0, %1}" [(set_attr "isa" "noavx,avx,sse3,noavx,avx,*") ! (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov") ! (set_attr "ssememalign" "64") (set_attr "prefix_data16" "*,*,*,1,*,1") (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex") (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")]) *************** *** 4744,4749 **** --- 4758,4764 ---- %vmovlpd\t{%2, %H0|%H0, %2}" [(set_attr "isa" "noavx,avx,sse3,noavx,avx,*") (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix_data16" "*,*,*,1,*,1") (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex") (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")]) *************** *** 4982,4987 **** --- 4997,5003 ---- movhlps\t{%1, %0|%0, %1} movlps\t{%H1, %0|%0, %H1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "mode" "V2SF,V4SF,V2SF")]) ;; Avoid combining registers from different units in a single alternative, *************** *** 5077,5082 **** --- 5093,5099 ---- #" [(set_attr "isa" "noavx,avx,noavx,avx,*,*,*") (set_attr "type" "ssemov,ssemov,sselog,sselog,ssemov,fmov,imov") + (set_attr "ssememalign" "64") (set_attr "prefix_data16" "1,*,*,*,*,*,*") (set_attr "prefix" "orig,vex,orig,vex,*,*,*") (set_attr "mode" "V1DF,V1DF,V2DF,V2DF,DF,DF,DF")]) *************** *** 5145,5150 **** --- 5162,5168 ---- (const_string "imov") ] (const_string "ssemov"))) + (set_attr "ssememalign" "64") (set_attr "prefix_data16" "*,1,*,*,*,*,1,*,*,*,*") (set_attr "length_immediate" "*,*,*,*,*,1,*,*,*,*,*") (set_attr "prefix" "maybe_vex,orig,vex,orig,vex,orig,orig,vex,*,*,*") *************** *** 5189,5194 **** --- 5207,5213 ---- (const_string "1") (const_string "*"))) (set_attr "length_immediate" "*,*,*,*,*,1,*,*,*") + (set_attr "ssememalign" "64") (set_attr "prefix" "orig,vex,orig,vex,maybe_vex,orig,orig,vex,maybe_vex") (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")]) *************** *** 8736,8741 **** --- 8755,8761 ---- "TARGET_SSE4_1" "%vpmovbw\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) *************** *** 8766,8771 **** --- 8786,8792 ---- "TARGET_SSE4_1" "%vpmovbd\t{%1, %0|%0, %k1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "32") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) *************** *** 8791,8796 **** --- 8812,8818 ---- "TARGET_SSE4_1" "%vpmovwd\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) *************** *** 8818,8823 **** --- 8840,8846 ---- "TARGET_SSE4_1" "%vpmovbq\t{%1, %0|%0, %w1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "16") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) *************** *** 8845,8850 **** --- 8868,8874 ---- "TARGET_SSE4_1" "%vpmovwq\t{%1, %0|%0, %k1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "32") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) *************** *** 8868,8873 **** --- 8892,8898 ---- "TARGET_SSE4_1" "%vpmovdq\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) *************** *** 9151,9156 **** --- 9176,9182 ---- [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "memory" "none,load") (set_attr "mode" "TI")]) *************** *** 9213,9218 **** --- 9239,9245 ---- [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "memory" "load") (set_attr "mode" "TI")]) *************** *** 9240,9245 **** --- 9267,9273 ---- (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "btver2_decode" "vector") (set_attr "memory" "none,load") *************** *** 9267,9272 **** --- 9295,9301 ---- [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") (set_attr "btver2_decode" "vector") *************** *** 9293,9298 **** --- 9322,9328 ---- [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "memory" "none,load,none,load") (set_attr "btver2_decode" "vector,vector,vector,vector") *************** *** 9346,9351 **** --- 9376,9382 ---- [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "memory" "none,load") (set_attr "mode" "TI")]) *************** *** 9399,9404 **** --- 9430,9436 ---- [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "memory" "load") (set_attr "mode" "TI")]) *************** *** 9421,9426 **** --- 9453,9459 ---- [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") (set_attr "memory" "none,load") *************** *** 9445,9450 **** --- 9478,9484 ---- [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") (set_attr "memory" "none,load") *************** *** 9469,9474 **** --- 9503,9509 ---- [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "memory" "none,load,none,load") (set_attr "prefix" "maybe_vex") *************** *** 10213,10233 **** [(set_attr "type" "ssecvt1") (set_attr "mode" "")]) - ;; scalar insns (define_expand "xop_vmfrcz2" [(set (match_operand:VF_128 0 "register_operand") (vec_merge:VF_128 (unspec:VF_128 [(match_operand:VF_128 1 "nonimmediate_operand")] UNSPEC_FRCZ) ! (match_dup 3) (const_int 1)))] "TARGET_XOP" ! { ! operands[3] = CONST0_RTX (mode); ! }) ! (define_insn "*xop_vmfrcz_" [(set (match_operand:VF_128 0 "register_operand" "=x") (vec_merge:VF_128 (unspec:VF_128 --- 10248,10265 ---- [(set_attr "type" "ssecvt1") (set_attr "mode" "")]) (define_expand "xop_vmfrcz2" [(set (match_operand:VF_128 0 "register_operand") (vec_merge:VF_128 (unspec:VF_128 [(match_operand:VF_128 1 "nonimmediate_operand")] UNSPEC_FRCZ) ! (match_dup 2) (const_int 1)))] "TARGET_XOP" ! "operands[2] = CONST0_RTX (mode);") ! (define_insn "*xop_vmfrcz2" [(set (match_operand:VF_128 0 "register_operand" "=x") (vec_merge:VF_128 (unspec:VF_128 diff -Nrcpad gcc-4.8.2/gcc/config/i386/t-rtems gcc-4.8.3/gcc/config/i386/t-rtems *** gcc-4.8.2/gcc/config/i386/t-rtems Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/i386/t-rtems Tue Nov 5 18:50:44 2013 *************** *** 17,27 **** # . # ! MULTILIB_OPTIONS = mtune=i486/mtune=pentium/mtune=pentiumpro \ ! msoft-float MULTILIB_DIRNAMES= m486 mpentium mpentiumpro soft-float ! MULTILIB_MATCHES = msoft-float=mno-m80387 ! MULTILIB_MATCHES += mtune?pentium=mtune?k6 mtune?pentiumpro=mtune?mathlon MULTILIB_EXCEPTIONS = \ mtune=pentium/*msoft-float* \ mtune=pentiumpro/*msoft-float* --- 17,26 ---- # . # ! MULTILIB_OPTIONS = mtune=i486/mtune=pentium/mtune=pentiumpro msoft-float MULTILIB_DIRNAMES= m486 mpentium mpentiumpro soft-float ! MULTILIB_MATCHES = msoft-float=mno-80387 ! MULTILIB_MATCHES += mtune?pentium=mtune?k6 mtune?pentiumpro=mtune?athlon MULTILIB_EXCEPTIONS = \ mtune=pentium/*msoft-float* \ mtune=pentiumpro/*msoft-float* diff -Nrcpad gcc-4.8.2/gcc/config/i386/winnt.c gcc-4.8.3/gcc/config/i386/winnt.c *** gcc-4.8.2/gcc/config/i386/winnt.c Fri May 10 01:54:06 2013 --- gcc-4.8.3/gcc/config/i386/winnt.c Sun Dec 1 12:21:51 2013 *************** i386_pe_asm_named_section (const char *n *** 547,554 **** sets 'discard' characteristic, rather than telling linker to warn of size or content mismatch, so do the same. */ bool discard = (flags & SECTION_CODE) ! || lookup_attribute ("selectany", ! DECL_ATTRIBUTES (decl)); fprintf (asm_out_file, "\t.linkonce %s\n", (discard ? "discard" : "same_size")); } --- 547,555 ---- sets 'discard' characteristic, rather than telling linker to warn of size or content mismatch, so do the same. */ bool discard = (flags & SECTION_CODE) ! || (TREE_CODE (decl) != IDENTIFIER_NODE ! && lookup_attribute ("selectany", ! DECL_ATTRIBUTES (decl))); fprintf (asm_out_file, "\t.linkonce %s\n", (discard ? "discard" : "same_size")); } diff -Nrcpad gcc-4.8.2/gcc/config/i386/xopintrin.h gcc-4.8.3/gcc/config/i386/xopintrin.h *** gcc-4.8.2/gcc/config/i386/xopintrin.h Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/i386/xopintrin.h Thu Nov 28 16:48:44 2013 *************** _mm_frcz_pd (__m128d __A) *** 745,757 **** extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_frcz_ss (__m128 __A, __m128 __B) { ! return (__m128) __builtin_ia32_vfrczss ((__v4sf)__A, (__v4sf)__B); } extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_frcz_sd (__m128d __A, __m128d __B) { ! return (__m128d) __builtin_ia32_vfrczsd ((__v2df)__A, (__v2df)__B); } extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) --- 745,761 ---- extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_frcz_ss (__m128 __A, __m128 __B) { ! return (__m128) __builtin_ia32_movss ((__v4sf)__A, ! (__v4sf) ! __builtin_ia32_vfrczss ((__v4sf)__B)); } extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_frcz_sd (__m128d __A, __m128d __B) { ! return (__m128d) __builtin_ia32_movsd ((__v2df)__A, ! (__v2df) ! __builtin_ia32_vfrczsd ((__v2df)__B)); } extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) diff -Nrcpad gcc-4.8.2/gcc/config/m68k/m68k.c gcc-4.8.3/gcc/config/m68k/m68k.c *** gcc-4.8.2/gcc/config/m68k/m68k.c Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/m68k/m68k.c Fri Jan 3 14:06:22 2014 *************** handle_move_double (rtx operands[2], *** 3325,3336 **** latehalf[1] = adjust_address (operands[1], SImode, 0); } ! /* If insn is effectively movd N(sp),-(sp) then we will do the ! high word first. We should use the adjusted operand 1 (which is N+4(sp)) ! for the low word as well, to compensate for the first decrement of sp. */ if (optype0 == PUSHOP ! && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM ! && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) operands[1] = middlehalf[1] = latehalf[1]; /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), --- 3325,3336 ---- latehalf[1] = adjust_address (operands[1], SImode, 0); } ! /* If insn is effectively movd N(REG),-(REG) then we will do the high ! word first. We should use the adjusted operand 1 (which is N+4(REG)) ! for the low word as well, to compensate for the first decrement of ! REG. */ if (optype0 == PUSHOP ! && reg_overlap_mentioned_p (XEXP (XEXP (operands[0], 0), 0), operands[1])) operands[1] = middlehalf[1] = latehalf[1]; /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), diff -Nrcpad gcc-4.8.2/gcc/config/microblaze/microblaze.c gcc-4.8.3/gcc/config/microblaze/microblaze.c *** gcc-4.8.2/gcc/config/microblaze/microblaze.c Thu Mar 14 15:43:23 2013 --- gcc-4.8.3/gcc/config/microblaze/microblaze.c Sun Feb 23 18:45:12 2014 *************** static int *** 1609,1629 **** microblaze_version_to_int (const char *version) { const char *p, *v; ! const char *tmpl = "vX.YY.Z"; int iver = 0; p = version; v = tmpl; ! while (*v) { if (*v == 'X') { /* Looking for major */ ! if (!(*p >= '0' && *p <= '9')) ! return -1; ! iver += (int) (*p - '0'); ! iver *= 10; ! } else if (*v == 'Y') { /* Looking for minor */ if (!(*p >= '0' && *p <= '9')) --- 1609,1636 ---- microblaze_version_to_int (const char *version) { const char *p, *v; ! const char *tmpl = "vXX.YY.Z"; int iver = 0; p = version; v = tmpl; ! while (*p) { if (*v == 'X') { /* Looking for major */ ! if (*p == '.') ! { ! *v++; ! } ! else ! { ! if (!(*p >= '0' && *p <= '9')) ! return -1; ! iver += (int) (*p - '0'); ! iver *= 10; ! } ! } else if (*v == 'Y') { /* Looking for minor */ if (!(*p >= '0' && *p <= '9')) *************** expand_pic_symbol_ref (enum machine_mode *** 3064,3069 **** --- 3071,3143 ---- return result; } + static void + microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, + tree function) + { + rtx this_rtx, insn, funexp; + + reload_completed = 1; + epilogue_completed = 1; + + /* Mark the end of the (empty) prologue. */ + emit_note (NOTE_INSN_PROLOGUE_END); + + /* Find the "this" pointer. If the function returns a structure, + the structure return pointer is in MB_ABI_FIRST_ARG_REGNUM. */ + if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) + this_rtx = gen_rtx_REG (Pmode, (MB_ABI_FIRST_ARG_REGNUM + 1)); + else + this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM); + + /* Apply the constant offset, if required. */ + if (delta) + emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); + + /* Apply the offset from the vtable, if required. */ + if (vcall_offset) + { + rtx vcall_offset_rtx = GEN_INT (vcall_offset); + rtx temp1 = gen_rtx_REG (Pmode, MB_ABI_TEMP1_REGNUM); + + emit_move_insn (temp1, gen_rtx_MEM (Pmode, this_rtx)); + + rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx); + emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc)); + + emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); + } + + /* Generate a tail call to the target function. */ + if (!TREE_USED (function)) + { + assemble_external (function); + TREE_USED (function) = 1; + } + + funexp = XEXP (DECL_RTL (function), 0); + rtx temp2 = gen_rtx_REG (Pmode, MB_ABI_TEMP2_REGNUM); + + if (flag_pic) + emit_move_insn (temp2, expand_pic_symbol_ref (Pmode, funexp)); + else + emit_move_insn (temp2, funexp); + + emit_insn (gen_indirect_jump (temp2)); + + /* Run just enough of rest_of_compilation. This sequence was + "borrowed" from rs6000.c. */ + insn = get_insns (); + shorten_branches (insn); + final_start_function (insn, file, 1); + final (insn, file, 1); + final_end_function (); + + reload_completed = 0; + epilogue_completed = 0; + } + bool microblaze_expand_move (enum machine_mode mode, rtx operands[]) { *************** microblaze_trampoline_init (rtx m_tramp, *** 3234,3298 **** emit_move_insn (mem, fnaddr); } ! /* Emit instruction to perform compare. ! cmp is (compare_op op0 op1). */ ! static rtx ! microblaze_emit_compare (enum machine_mode mode, rtx cmp, enum rtx_code *cmp_code) { ! rtx cmp_op0 = XEXP (cmp, 0); ! rtx cmp_op1 = XEXP (cmp, 1); rtx comp_reg = gen_reg_rtx (SImode); ! enum rtx_code code = *cmp_code; ! gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG)); /* If comparing against zero, just test source reg. */ ! if (cmp_op1 == const0_rtx) ! return cmp_op0; ! if (code == EQ || code == NE) { /* Use xor for equal/not-equal comparison. */ emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); } ! else if (code == GT || code == GTU || code == LE || code == LEU) ! { ! /* MicroBlaze compare is not symmetrical. */ ! /* Swap argument order. */ ! cmp_op1 = force_reg (mode, cmp_op1); ! if (code == GT || code == LE) ! emit_insn (gen_signed_compare (comp_reg, cmp_op0, cmp_op1)); ! else ! emit_insn (gen_unsigned_compare (comp_reg, cmp_op0, cmp_op1)); ! /* Translate test condition. */ ! *cmp_code = swap_condition (code); ! } ! else /* if (code == GE || code == GEU || code == LT || code == LTU) */ { cmp_op1 = force_reg (mode, cmp_op1); ! if (code == GE || code == LT) ! emit_insn (gen_signed_compare (comp_reg, cmp_op1, cmp_op0)); ! else ! emit_insn (gen_unsigned_compare (comp_reg, cmp_op1, cmp_op0)); } - - return comp_reg; } - /* Generate conditional branch -- first, generate test condition, - second, generate correct branch instruction. */ - - void - microblaze_expand_conditional_branch (enum machine_mode mode, rtx operands[]) - { - enum rtx_code code = GET_CODE (operands[0]); - rtx comp; - rtx condition; - - comp = microblaze_emit_compare (mode, operands[0], &code); - condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp, const0_rtx); - emit_jump_insn (gen_condjump (condition, operands[3])); - } void microblaze_expand_conditional_branch_sf (rtx operands[]) --- 3308,3352 ---- emit_move_insn (mem, fnaddr); } ! /* Generate conditional branch -- first, generate test condition, ! second, generate correct branch instruction. */ ! ! void ! microblaze_expand_conditional_branch (enum machine_mode mode, rtx operands[]) { ! enum rtx_code code = GET_CODE (operands[0]); ! rtx cmp_op0 = operands[1]; ! rtx cmp_op1 = operands[2]; ! rtx label1 = operands[3]; rtx comp_reg = gen_reg_rtx (SImode); ! rtx condition; ! gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG)); /* If comparing against zero, just test source reg. */ ! if (cmp_op1 == const0_rtx) ! { ! comp_reg = cmp_op0; ! condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); ! emit_jump_insn (gen_condjump (condition, label1)); ! } ! else if (code == EQ || code == NE) { /* Use xor for equal/not-equal comparison. */ emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); + condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); + emit_jump_insn (gen_condjump (condition, label1)); } ! else { + /* Generate compare and branch in single instruction. */ cmp_op1 = force_reg (mode, cmp_op1); ! condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); ! emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); } } void microblaze_expand_conditional_branch_sf (rtx operands[]) *************** microblaze_legitimate_constant_p (enum m *** 3501,3506 **** --- 3555,3566 ---- #undef TARGET_SECONDARY_RELOAD #define TARGET_SECONDARY_RELOAD microblaze_secondary_reload + #undef TARGET_ASM_OUTPUT_MI_THUNK + #define TARGET_ASM_OUTPUT_MI_THUNK microblaze_asm_output_mi_thunk + + #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK + #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true + #undef TARGET_SCHED_ADJUST_COST #define TARGET_SCHED_ADJUST_COST microblaze_adjust_cost diff -Nrcpad gcc-4.8.2/gcc/config/microblaze/microblaze.h gcc-4.8.3/gcc/config/microblaze/microblaze.h *** gcc-4.8.2/gcc/config/microblaze/microblaze.h Thu Mar 14 15:43:23 2013 --- gcc-4.8.3/gcc/config/microblaze/microblaze.h Sun Feb 23 18:54:17 2014 *************** extern enum pipeline_type microblaze_pip *** 213,218 **** --- 213,224 ---- #define STRICT_ALIGNMENT 1 #define PCC_BITFIELD_TYPE_MATTERS 1 + #undef SIZE_TYPE + #define SIZE_TYPE "unsigned int" + + #undef PTRDIFF_TYPE + #define PTRDIFF_TYPE "int" + #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ && (ALIGN) < BITS_PER_WORD \ *************** extern enum reg_class microblaze_regno_t *** 407,415 **** || GET_MODE (X) == VOIDmode) \ ? (GR_REGS) : (CLASS)))) - #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ - (GET_MODE_CLASS (MODE) == MODE_INT) - /* Stack layout; function entry, exit and calling. */ #define STACK_GROWS_DOWNWARD --- 413,418 ---- diff -Nrcpad gcc-4.8.2/gcc/config/microblaze/microblaze.md gcc-4.8.3/gcc/config/microblaze/microblaze.md *** gcc-4.8.2/gcc/config/microblaze/microblaze.md Thu Mar 14 15:43:23 2013 --- gcc-4.8.3/gcc/config/microblaze/microblaze.md Sun Feb 23 18:59:26 2014 *************** *** 74,80 **** ;; bshift Shift operations (define_attr "type" ! "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt" (const_string "unknown")) ;; Main data type used by the insn --- 74,80 ---- ;; bshift Shift operations (define_attr "type" ! "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap" (const_string "unknown")) ;; Main data type used by the insn *************** *** 365,371 **** [(set (match_operand:HI 0 "register_operand" "=r") (bswap:HI (match_operand:HI 1 "register_operand" "r")))] "TARGET_REORDER" ! "swaph %0, %1" ) ;;---------------------------------------------------------------- --- 365,372 ---- [(set (match_operand:HI 0 "register_operand" "=r") (bswap:HI (match_operand:HI 1 "register_operand" "r")))] "TARGET_REORDER" ! "swapb %0, %1 ! swaph %0, %0" ) ;;---------------------------------------------------------------- *************** *** 1118,1123 **** --- 1119,1136 ---- } ) + ;;Load and store reverse + (define_insn "movsi4_rev" + [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Q") + (bswap:SI (match_operand:SF 1 "reg_or_mem_operand" "Q,r")))] + "TARGET_REORDER" + "@ + lwr\t%0,%y1,r0 + swr\t%1,%y0,r0" + [(set_attr "type" "load,store") + (set_attr "mode" "SI") + (set_attr "length" "4,4")]) + ;; 32-bit floating point moves (define_expand "movsf" *************** *** 1472,1478 **** (set_attr "length" "124")] ) ! (define_insn "*ashlri_reg" [(set (match_operand:SI 0 "register_operand" "=&d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")))] --- 1485,1491 ---- (set_attr "length" "124")] ) ! (define_insn "*ashrsi_reg" [(set (match_operand:SI 0 "register_operand" "=&d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")))] *************** *** 1561,1567 **** (set_attr "length" "124")] ) ! (define_insn "*lshlri_reg" [(set (match_operand:SI 0 "register_operand" "=&d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")))] --- 1574,1580 ---- (set_attr "length" "124")] ) ! (define_insn "*lshrsi_reg" [(set (match_operand:SI 0 "register_operand" "=&d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")))] *************** *** 1622,1655 **** (set_attr "length" "4")] ) - (define_insn "signed_compare" - [(set (match_operand:SI 0 "register_operand" "=d") - (unspec - [(match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMP))] - "" - "cmp\t%0,%1,%2" - [(set_attr "type" "arith") - (set_attr "mode" "SI") - (set_attr "length" "4")]) - - (define_insn "unsigned_compare" - [(set (match_operand:SI 0 "register_operand" "=d") - (unspec - [(match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMPU))] - "" - "cmpu\t%0,%1,%2" - [(set_attr "type" "arith") - (set_attr "mode" "SI") - (set_attr "length" "4")]) - ;;---------------------------------------------------------------- ;; Setting a register from an floating point comparison. ;;---------------------------------------------------------------- (define_insn "cstoresf4" [(set (match_operand:SI 0 "register_operand" "=r") ! (match_operator 1 "comparison_operator" [(match_operand:SF 2 "register_operand" "r") (match_operand:SF 3 "register_operand" "r")]))] "TARGET_HARD_FLOAT" --- 1635,1646 ---- (set_attr "length" "4")] ) ;;---------------------------------------------------------------- ;; Setting a register from an floating point comparison. ;;---------------------------------------------------------------- (define_insn "cstoresf4" [(set (match_operand:SI 0 "register_operand" "=r") ! (match_operator:SI 1 "ordered_comparison_operator" [(match_operand:SF 2 "register_operand" "r") (match_operand:SF 3 "register_operand" "r")]))] "TARGET_HARD_FLOAT" *************** *** 1678,1684 **** (define_expand "cbranchsf4" [(set (pc) ! (if_then_else (match_operator 0 "comparison_operator" [(match_operand:SF 1 "register_operand") (match_operand:SF 2 "register_operand")]) (label_ref (match_operand 3 "")) --- 1669,1675 ---- (define_expand "cbranchsf4" [(set (pc) ! (if_then_else (match_operator 0 "ordered_comparison_operator" [(match_operand:SF 1 "register_operand") (match_operand:SF 2 "register_operand")]) (label_ref (match_operand 3 "")) *************** *** 1717,1722 **** --- 1708,1754 ---- (set_attr "length" "4")] ) + (define_insn "branch_compare" + [(set (pc) + (if_then_else (match_operator:SI 0 "cmp_op" + [(match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d") + ]) + (label_ref (match_operand 3)) + (pc))) + (clobber(reg:SI R_TMP))] + "" + { + operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + enum rtx_code code = GET_CODE (operands[0]); + + if (code == GT || code == LE) + { + output_asm_insn ("cmp\tr18,%z1,%z2", operands); + code = swap_condition (code); + } + else if (code == GTU || code == LEU) + { + output_asm_insn ("cmpu\tr18,%z1,%z2", operands); + code = swap_condition (code); + } + else if (code == GE || code == LT) + { + output_asm_insn ("cmp\tr18,%z2,%z1", operands); + } + else if (code == GEU || code == LTU) + { + output_asm_insn ("cmpu\tr18,%z2,%z1", operands); + } + + operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx); + return "b%C0i%?\tr18,%3"; + } + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "12")] + ) + ;;---------------------------------------------------------------- ;; Unconditional branches ;;---------------------------------------------------------------- *************** *** 2201,2206 **** --- 2233,2246 ---- (set_attr "mode" "none") (set_attr "length" "4")]) + ;; Trap instruction pattern for __builtin_trap. Same as the glibc ABORT_INSTRUCTION + (define_insn "trap" + [(trap_if (const_int 1) (const_int 0))] + "" + "brki\tr0,-1" + [(set_attr "type" "trap")] + ) + ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference ;; between "mfs" and "addik" instructions. (define_insn "set_got" diff -Nrcpad gcc-4.8.2/gcc/config/microblaze/predicates.md gcc-4.8.3/gcc/config/microblaze/predicates.md *** gcc-4.8.2/gcc/config/microblaze/predicates.md Thu Mar 14 15:43:23 2013 --- gcc-4.8.3/gcc/config/microblaze/predicates.md Sun Feb 23 18:38:29 2014 *************** *** 85,90 **** --- 85,94 ---- (ior (match_operand 0 "const_0_operand") (match_operand 0 "register_operand"))) + (define_predicate "reg_or_mem_operand" + (ior (match_operand 0 "memory_operand") + (match_operand 0 "register_operand"))) + ;; Return if the operand is either the PC or a label_ref. (define_special_predicate "pc_or_label_operand" (ior (match_code "pc,label_ref") *************** *** 119,121 **** --- 123,129 ---- ;; Test for valid PIC call operand (define_predicate "call_insn_plt_operand" (match_test "PLT_ADDR_P (op)")) + + ;; Return if the code of this rtx pattern is a comparison. + (define_predicate "cmp_op" + (match_code "gt,ge,gtu,geu,lt,le,ltu,leu")) diff -Nrcpad gcc-4.8.2/gcc/config/mips/driver-native.c gcc-4.8.3/gcc/config/mips/driver-native.c *** gcc-4.8.2/gcc/config/mips/driver-native.c Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/mips/driver-native.c Fri Jan 10 08:52:42 2014 *************** host_detect_local_cpu (int argc, const c *** 58,68 **** if (strncmp (buf, "cpu model", sizeof ("cpu model") - 1) == 0) { if (strstr (buf, "Godson2 V0.2") != NULL ! || strstr (buf, "Loongson-2 V0.2") != NULL) cpu = "loongson2e"; else if (strstr (buf, "Godson2 V0.3") != NULL ! || strstr (buf, "Loongson-2 V0.3") != NULL) cpu = "loongson2f"; else if (strstr (buf, "SiByte SB1") != NULL) cpu = "sb1"; else if (strstr (buf, "R5000") != NULL) --- 58,74 ---- if (strncmp (buf, "cpu model", sizeof ("cpu model") - 1) == 0) { if (strstr (buf, "Godson2 V0.2") != NULL ! || strstr (buf, "Loongson-2 V0.2") != NULL ! || strstr (buf, "Loongson-2E") != NULL) cpu = "loongson2e"; else if (strstr (buf, "Godson2 V0.3") != NULL ! || strstr (buf, "Loongson-2 V0.3") != NULL ! || strstr (buf, "Loongson-2F") != NULL) cpu = "loongson2f"; + else if (strstr (buf, "Godson3 V0.5") != NULL + || strstr (buf, "Loongson-3 V0.5") != NULL + || strstr (buf, "Loongson-3A") != NULL) + cpu = "loongson3a"; else if (strstr (buf, "SiByte SB1") != NULL) cpu = "sb1"; else if (strstr (buf, "R5000") != NULL) diff -Nrcpad gcc-4.8.2/gcc/config/mips/mips.c gcc-4.8.3/gcc/config/mips/mips.c *** gcc-4.8.2/gcc/config/mips/mips.c Mon Feb 25 13:53:16 2013 --- gcc-4.8.3/gcc/config/mips/mips.c Tue Jan 21 18:49:27 2014 *************** mips_set_reg_reg_cost (enum machine_mode *** 3560,3576 **** } } - /* Return the cost of an operand X that can be trucated for free. - SPEED says whether we're optimizing for size or speed. */ - - static int - mips_truncated_op_cost (rtx x, bool speed) - { - if (GET_CODE (x) == TRUNCATE) - x = XEXP (x, 0); - return set_src_cost (x, speed); - } - /* Implement TARGET_RTX_COSTS. */ static bool --- 3560,3565 ---- *************** mips_rtx_costs (rtx x, int code, int out *** 3951,3963 **** case ZERO_EXTEND: if (outer_code == SET && ISA_HAS_BADDU && GET_MODE (XEXP (x, 0)) == QImode ! && GET_CODE (XEXP (x, 0)) == PLUS) { ! rtx plus = XEXP (x, 0); ! *total = (COSTS_N_INSNS (1) ! + mips_truncated_op_cost (XEXP (plus, 0), speed) ! + mips_truncated_op_cost (XEXP (plus, 1), speed)); return true; } *total = mips_zero_extend_cost (mode, XEXP (x, 0)); --- 3940,3951 ---- case ZERO_EXTEND: if (outer_code == SET && ISA_HAS_BADDU + && (GET_CODE (XEXP (x, 0)) == TRUNCATE + || GET_CODE (XEXP (x, 0)) == SUBREG) && GET_MODE (XEXP (x, 0)) == QImode ! && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS) { ! *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed); return true; } *total = mips_zero_extend_cost (mode, XEXP (x, 0)); *************** mips_print_operand (FILE *file, rtx op, *** 8057,8063 **** case 't': { int truth = (code == NE) == (letter == 'T'); ! fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file); } break; --- 8045,8051 ---- case 't': { int truth = (code == NE) == (letter == 'T'); ! fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file); } break; diff -Nrcpad gcc-4.8.2/gcc/config/mips/mips.h gcc-4.8.3/gcc/config/mips/mips.h *** gcc-4.8.2/gcc/config/mips/mips.h Mon Feb 25 13:53:16 2013 --- gcc-4.8.3/gcc/config/mips/mips.h Thu Jan 9 20:06:19 2014 *************** struct mips_cpu_info { *** 949,954 **** --- 949,959 ---- || TARGET_SMARTMIPS) \ && !TARGET_MIPS16) + /* ISA has the WSBH (word swap bytes within halfwords) instruction. + 64-bit targets also provide DSBH and DSHD. */ + #define ISA_HAS_WSBH ((ISA_MIPS32R2 || ISA_MIPS64R2) \ + && !TARGET_MIPS16) + /* ISA has data prefetch instructions. This controls use of 'pref'. */ #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ || TARGET_LOONGSON_2EF \ diff -Nrcpad gcc-4.8.2/gcc/config/mips/mips.md gcc-4.8.3/gcc/config/mips/mips.md *** gcc-4.8.2/gcc/config/mips/mips.md Mon Feb 25 13:53:16 2013 --- gcc-4.8.3/gcc/config/mips/mips.md Thu Jan 9 20:06:19 2014 *************** *** 73,78 **** --- 73,83 ---- UNSPEC_STORE_LEFT UNSPEC_STORE_RIGHT + ;; Integer operations that are too cumbersome to describe directly. + UNSPEC_WSBH + UNSPEC_DSBH + UNSPEC_DSHD + ;; Floating-point moves. UNSPEC_LOAD_LOW UNSPEC_LOAD_HIGH *************** *** 1294,1313 **** ;; Combiner patterns for unsigned byte-add. ! (define_insn "*baddu_si" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI ! (plus:QI (match_operand:QI 1 "register_operand" "d") ! (match_operand:QI 2 "register_operand" "d"))))] ! "ISA_HAS_BADDU" "baddu\\t%0,%1,%2" [(set_attr "alu_type" "add")]) (define_insn "*baddu_di" [(set (match_operand:GPR 0 "register_operand" "=d") (zero_extend:GPR ! (plus:QI (truncate:QI (match_operand:DI 1 "register_operand" "d")) ! (truncate:QI (match_operand:DI 2 "register_operand" "d")))))] "ISA_HAS_BADDU && TARGET_64BIT" "baddu\\t%0,%1,%2" [(set_attr "alu_type" "add")]) --- 1299,1330 ---- ;; Combiner patterns for unsigned byte-add. ! (define_insn "*baddu_si_eb" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI ! (subreg:QI ! (plus:SI (match_operand:SI 1 "register_operand" "d") ! (match_operand:SI 2 "register_operand" "d")) 3)))] ! "ISA_HAS_BADDU && BYTES_BIG_ENDIAN" ! "baddu\\t%0,%1,%2" ! [(set_attr "alu_type" "add")]) ! ! (define_insn "*baddu_si_el" ! [(set (match_operand:SI 0 "register_operand" "=d") ! (zero_extend:SI ! (subreg:QI ! (plus:SI (match_operand:SI 1 "register_operand" "d") ! (match_operand:SI 2 "register_operand" "d")) 0)))] ! "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN" "baddu\\t%0,%1,%2" [(set_attr "alu_type" "add")]) (define_insn "*baddu_di" [(set (match_operand:GPR 0 "register_operand" "=d") (zero_extend:GPR ! (truncate:QI ! (plus:DI (match_operand:DI 1 "register_operand" "d") ! (match_operand:DI 2 "register_operand" "d")))))] "ISA_HAS_BADDU && TARGET_64BIT" "baddu\\t%0,%1,%2" [(set_attr "alu_type" "add")]) *************** *** 5367,5372 **** --- 5384,5439 ---- } [(set_attr "type" "shift") (set_attr "mode" "")]) + + (define_insn "bswaphi2" + [(set (match_operand:HI 0 "register_operand" "=d") + (bswap:HI (match_operand:HI 1 "register_operand" "d")))] + "ISA_HAS_WSBH" + "wsbh\t%0,%1" + [(set_attr "type" "shift")]) + + (define_insn_and_split "bswapsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (bswap:SI (match_operand:SI 1 "register_operand" "d")))] + "ISA_HAS_WSBH && ISA_HAS_ROR" + "#" + "" + [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH)) + (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))] + "" + [(set_attr "length" "8")]) + + (define_insn_and_split "bswapdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (bswap:DI (match_operand:DI 1 "register_operand" "d")))] + "TARGET_64BIT && ISA_HAS_WSBH" + "#" + "" + [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH)) + (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))] + "" + [(set_attr "length" "8")]) + + (define_insn "wsbh" + [(set (match_operand:SI 0 "register_operand" "=d") + (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))] + "ISA_HAS_WSBH" + "wsbh\t%0,%1" + [(set_attr "type" "shift")]) + + (define_insn "dsbh" + [(set (match_operand:DI 0 "register_operand" "=d") + (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))] + "TARGET_64BIT && ISA_HAS_WSBH" + "dsbh\t%0,%1" + [(set_attr "type" "shift")]) + + (define_insn "dshd" + [(set (match_operand:DI 0 "register_operand" "=d") + (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))] + "TARGET_64BIT && ISA_HAS_WSBH" + "dshd\t%0,%1" + [(set_attr "type" "shift")]) ;; ;; .................... diff -Nrcpad gcc-4.8.2/gcc/config/pa/pa.c gcc-4.8.3/gcc/config/pa/pa.c *** gcc-4.8.2/gcc/config/pa/pa.c Sat Sep 21 00:00:38 2013 --- gcc-4.8.3/gcc/config/pa/pa.c Tue Feb 25 00:52:10 2014 *************** static rtx *** 912,920 **** legitimize_tls_address (rtx addr) { rtx ret, insn, tmp, t1, t2, tp; - enum tls_model model = SYMBOL_REF_TLS_MODEL (addr); ! switch (model) { case TLS_MODEL_GLOBAL_DYNAMIC: tmp = gen_reg_rtx (Pmode); --- 912,923 ---- legitimize_tls_address (rtx addr) { rtx ret, insn, tmp, t1, t2, tp; ! /* Currently, we can't handle anything but a SYMBOL_REF. */ ! if (GET_CODE (addr) != SYMBOL_REF) ! return addr; ! ! switch (SYMBOL_REF_TLS_MODEL (addr)) { case TLS_MODEL_GLOBAL_DYNAMIC: tmp = gen_reg_rtx (Pmode); *************** hppa_legitimize_address (rtx x, rtx oldx *** 1035,1041 **** && !REG_POINTER (XEXP (x, 1))) return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0)); ! if (PA_SYMBOL_REF_TLS_P (x)) return legitimize_tls_address (x); else if (flag_pic) return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode)); --- 1038,1044 ---- && !REG_POINTER (XEXP (x, 1))) return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0)); ! if (pa_tls_referenced_p (x)) return legitimize_tls_address (x); else if (flag_pic) return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode)); *************** pa_emit_move_sequence (rtx *operands, en *** 1916,1924 **** not consider them legitimate constants. Loop optimizations can call the emit_move_xxx with one as a source. */ if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) - || function_label_operand (operand1, VOIDmode) || (GET_CODE (operand1) == HIGH ! && symbolic_operand (XEXP (operand1, 0), mode))) { int ishighonly = 0; --- 1919,1928 ---- not consider them legitimate constants. Loop optimizations can call the emit_move_xxx with one as a source. */ if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) || (GET_CODE (operand1) == HIGH ! && symbolic_operand (XEXP (operand1, 0), mode)) ! || function_label_operand (operand1, VOIDmode) ! || pa_tls_referenced_p (operand1)) { int ishighonly = 0; *************** pa_output_move_double (rtx *operands) *** 2625,2638 **** if (optype0 == REGOP) latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); else if (optype0 == OFFSOP) ! latehalf[0] = adjust_address (operands[0], SImode, 4); else latehalf[0] = operands[0]; if (optype1 == REGOP) latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); else if (optype1 == OFFSOP) ! latehalf[1] = adjust_address (operands[1], SImode, 4); else if (optype1 == CNSTOP) split_double (operands[1], &operands[1], &latehalf[1]); else --- 2629,2642 ---- if (optype0 == REGOP) latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); else if (optype0 == OFFSOP) ! latehalf[0] = adjust_address_nv (operands[0], SImode, 4); else latehalf[0] = operands[0]; if (optype1 == REGOP) latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); else if (optype1 == OFFSOP) ! latehalf[1] = adjust_address_nv (operands[1], SImode, 4); else if (optype1 == CNSTOP) split_double (operands[1], &operands[1], &latehalf[1]); else *************** pa_attr_length_millicode_call (rtx insn) *** 7539,7545 **** if (!TARGET_LONG_CALLS && distance < MAX_PCREL17F_OFFSET) return 8; ! if (TARGET_LONG_ABS_CALL && !flag_pic) return 12; return 24; --- 7543,7549 ---- if (!TARGET_LONG_CALLS && distance < MAX_PCREL17F_OFFSET) return 8; ! if (!flag_pic) return 12; return 24; *************** pa_attr_length_indirect_call (rtx insn) *** 8104,8110 **** return 12; if (TARGET_FAST_INDIRECT_CALLS ! || (!TARGET_PORTABLE_RUNTIME && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000) || distance < MAX_PCREL17F_OFFSET))) return 8; --- 8108,8115 ---- return 12; if (TARGET_FAST_INDIRECT_CALLS ! || (!TARGET_LONG_CALLS ! && !TARGET_PORTABLE_RUNTIME && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000) || distance < MAX_PCREL17F_OFFSET))) return 8; *************** pa_legitimate_constant_p (enum machine_m *** 10397,10403 **** /* TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC are not legitimate constants. The other variants can't be handled by the move patterns after reload starts. */ ! if (PA_SYMBOL_REF_TLS_P (x)) return false; if (TARGET_64BIT && GET_CODE (x) == CONST_DOUBLE) --- 10402,10408 ---- /* TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC are not legitimate constants. The other variants can't be handled by the move patterns after reload starts. */ ! if (pa_tls_referenced_p (x)) return false; if (TARGET_64BIT && GET_CODE (x) == CONST_DOUBLE) *************** pa_legitimate_address_p (enum machine_mo *** 10522,10534 **** /* When INT14_OK_STRICT is false, a secondary reload is needed to adjust the displacement of SImode and DImode floating point ! instructions. So, we return false when STRICT is true. We also reject long displacements for float mode addresses since the majority of accesses will use floating point instructions that don't support 14-bit offsets. */ if (!INT14_OK_STRICT ! && reload_in_progress ! && strict && mode != QImode && mode != HImode) return false; --- 10527,10539 ---- /* When INT14_OK_STRICT is false, a secondary reload is needed to adjust the displacement of SImode and DImode floating point ! instructions but this may fail when the register also needs ! reloading. So, we return false when STRICT is true. We also reject long displacements for float mode addresses since the majority of accesses will use floating point instructions that don't support 14-bit offsets. */ if (!INT14_OK_STRICT ! && (strict || !(reload_in_progress || reload_completed)) && mode != QImode && mode != HImode) return false; *************** pa_legitimate_address_p (enum machine_mo *** 10588,10595 **** return true; if (!INT14_OK_STRICT ! && reload_in_progress ! && strict && mode != QImode && mode != HImode) return false; --- 10593,10599 ---- return true; if (!INT14_OK_STRICT ! && (strict || !(reload_in_progress || reload_completed)) && mode != QImode && mode != HImode) return false; diff -Nrcpad gcc-4.8.2/gcc/config/pa/pa.h gcc-4.8.3/gcc/config/pa/pa.h *** gcc-4.8.2/gcc/config/pa/pa.h Sun Feb 3 19:52:37 2013 --- gcc-4.8.3/gcc/config/pa/pa.h Wed Feb 5 00:47:25 2014 *************** extern int may_call_alloca; *** 784,792 **** #define MAX_REGS_PER_ADDRESS 2 ! /* Non-TLS symbolic references. */ ! #define PA_SYMBOL_REF_TLS_P(RTX) \ ! (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) /* Recognize any constant value that is a valid address except for symbolic addresses. We get better CSE by rejecting them --- 784,792 ---- #define MAX_REGS_PER_ADDRESS 2 ! /* TLS symbolic reference. */ ! #define PA_SYMBOL_REF_TLS_P(X) \ ! (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (X) != 0) /* Recognize any constant value that is a valid address except for symbolic addresses. We get better CSE by rejecting them *************** extern int may_call_alloca; *** 796,802 **** #define CONSTANT_ADDRESS_P(X) \ ((GET_CODE (X) == LABEL_REF \ || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \ ! || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ || GET_CODE (X) == HIGH) \ && (reload_in_progress || reload_completed \ || ! pa_symbolic_expression_p (X))) --- 796,803 ---- #define CONSTANT_ADDRESS_P(X) \ ((GET_CODE (X) == LABEL_REF \ || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \ ! || GET_CODE (X) == CONST_INT \ ! || (GET_CODE (X) == CONST && !pa_tls_referenced_p (X)) \ || GET_CODE (X) == HIGH) \ && (reload_in_progress || reload_completed \ || ! pa_symbolic_expression_p (X))) diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/altivec.h gcc-4.8.3/gcc/config/rs6000/altivec.h *** gcc-4.8.2/gcc/config/rs6000/altivec.h Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/rs6000/altivec.h Wed Apr 23 23:16:05 2014 *************** *** 319,324 **** --- 319,374 ---- #define vec_sqrt __builtin_vec_sqrt #define vec_vsx_ld __builtin_vec_vsx_ld #define vec_vsx_st __builtin_vec_vsx_st + + /* Note, xxsldi and xxpermdi were added as __builtin_vsx_ functions + instead of __builtin_vec_ */ + #define vec_xxsldwi __builtin_vsx_xxsldwi + #define vec_xxpermdi __builtin_vsx_xxpermdi + #endif + + #ifdef _ARCH_PWR8 + /* Vector additions added in ISA 2.07. */ + #define vec_eqv __builtin_vec_eqv + #define vec_nand __builtin_vec_nand + #define vec_orc __builtin_vec_orc + #define vec_vaddcuq __builtin_vec_vaddcuq + #define vec_vaddudm __builtin_vec_vaddudm + #define vec_vadduqm __builtin_vec_vadduqm + #define vec_vbpermq __builtin_vec_vbpermq + #define vec_vclz __builtin_vec_vclz + #define vec_vclzb __builtin_vec_vclzb + #define vec_vclzd __builtin_vec_vclzd + #define vec_vclzh __builtin_vec_vclzh + #define vec_vclzw __builtin_vec_vclzw + #define vec_vaddecuq __builtin_vec_vaddecuq + #define vec_vaddeuqm __builtin_vec_vaddeuqm + #define vec_vsubecuq __builtin_vec_vsubecuq + #define vec_vsubeuqm __builtin_vec_vsubeuqm + #define vec_vgbbd __builtin_vec_vgbbd + #define vec_vmaxsd __builtin_vec_vmaxsd + #define vec_vmaxud __builtin_vec_vmaxud + #define vec_vminsd __builtin_vec_vminsd + #define vec_vminud __builtin_vec_vminud + #define vec_vmrgew __builtin_vec_vmrgew + #define vec_vmrgow __builtin_vec_vmrgow + #define vec_vpksdss __builtin_vec_vpksdss + #define vec_vpksdus __builtin_vec_vpksdus + #define vec_vpkudum __builtin_vec_vpkudum + #define vec_vpkudus __builtin_vec_vpkudus + #define vec_vpopcnt __builtin_vec_vpopcnt + #define vec_vpopcntb __builtin_vec_vpopcntb + #define vec_vpopcntd __builtin_vec_vpopcntd + #define vec_vpopcnth __builtin_vec_vpopcnth + #define vec_vpopcntw __builtin_vec_vpopcntw + #define vec_vrld __builtin_vec_vrld + #define vec_vsld __builtin_vec_vsld + #define vec_vsrad __builtin_vec_vsrad + #define vec_vsrd __builtin_vec_vsrd + #define vec_vsubcuq __builtin_vec_vsubcuq + #define vec_vsubudm __builtin_vec_vsubudm + #define vec_vsubuqm __builtin_vec_vsubuqm + #define vec_vupkhsw __builtin_vec_vupkhsw + #define vec_vupklsw __builtin_vec_vupklsw #endif /* Predicates. diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/altivec.md gcc-4.8.3/gcc/config/rs6000/altivec.md *** gcc-4.8.2/gcc/config/rs6000/altivec.md Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/rs6000/altivec.md Wed Apr 30 20:04:12 2014 *************** *** 41,55 **** UNSPEC_VMULOSB UNSPEC_VMULOUH UNSPEC_VMULOSH - UNSPEC_VPKUHUM - UNSPEC_VPKUWUM UNSPEC_VPKPX ! UNSPEC_VPKSHSS ! UNSPEC_VPKSWSS ! UNSPEC_VPKUHUS ! UNSPEC_VPKSHUS ! UNSPEC_VPKUWUS ! UNSPEC_VPKSWUS UNSPEC_VSLV4SI UNSPEC_VSLO UNSPEC_VSR --- 41,52 ---- UNSPEC_VMULOSB UNSPEC_VMULOUH UNSPEC_VMULOSH UNSPEC_VPKPX ! UNSPEC_VPACK_SIGN_SIGN_SAT ! UNSPEC_VPACK_SIGN_UNS_SAT ! UNSPEC_VPACK_UNS_UNS_SAT ! UNSPEC_VPACK_UNS_UNS_MOD ! UNSPEC_VPACK_UNS_UNS_MOD_DIRECT UNSPEC_VSLV4SI UNSPEC_VSLO UNSPEC_VSR *************** *** 71,82 **** UNSPEC_VLOGEFP UNSPEC_VEXPTEFP UNSPEC_VLSDOI ! UNSPEC_VUPKHSB UNSPEC_VUPKHPX - UNSPEC_VUPKHSH - UNSPEC_VUPKLSB UNSPEC_VUPKLPX - UNSPEC_VUPKLSH UNSPEC_DST UNSPEC_DSTT UNSPEC_DSTST --- 68,79 ---- UNSPEC_VLOGEFP UNSPEC_VEXPTEFP UNSPEC_VLSDOI ! UNSPEC_VUNPACK_HI_SIGN ! UNSPEC_VUNPACK_LO_SIGN ! UNSPEC_VUNPACK_HI_SIGN_DIRECT ! UNSPEC_VUNPACK_LO_SIGN_DIRECT UNSPEC_VUPKHPX UNSPEC_VUPKLPX UNSPEC_DST UNSPEC_DSTT UNSPEC_DSTST *************** *** 134,139 **** --- 131,151 ---- UNSPEC_VUPKLS_V4SF UNSPEC_VUPKHU_V4SF UNSPEC_VUPKLU_V4SF + UNSPEC_VGBBD + UNSPEC_VMRGH_DIRECT + UNSPEC_VMRGL_DIRECT + UNSPEC_VSPLT_DIRECT + UNSPEC_VSUMSWS_DIRECT + UNSPEC_VADDCUQ + UNSPEC_VADDEUQM + UNSPEC_VADDECUQ + UNSPEC_VSUBCUQ + UNSPEC_VSUBEUQM + UNSPEC_VSUBECUQ + UNSPEC_VBPERMQ + UNSPEC_BCDADD + UNSPEC_BCDSUB + UNSPEC_BCD_OVERFLOW ]) (define_c_enum "unspecv" *************** *** 146,151 **** --- 158,165 ---- ;; Vec int modes (define_mode_iterator VI [V4SI V8HI V16QI]) + ;; Like VI, but add ISA 2.07 integer vector ops + (define_mode_iterator VI2 [V4SI V8HI V16QI V2DI]) ;; Short vec in modes (define_mode_iterator VIshort [V8HI V16QI]) ;; Vec float modes *************** *** 154,166 **** (define_mode_iterator V [V4SI V8HI V16QI V4SF]) ;; Vec modes for move/logical/permute ops, include vector types for move not ;; otherwise handled by altivec (v2df, v2di, ti) ! (define_mode_iterator VM [V4SI V8HI V16QI V4SF V2DF V2DI TI]) ;; Like VM, except don't do TImode ! (define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI]) ! (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")]) ! (define_mode_attr VI_scalar [(V4SI "SI") (V8HI "HI") (V16QI "QI")]) ;; Vector move instructions. (define_insn "*altivec_mov" --- 168,191 ---- (define_mode_iterator V [V4SI V8HI V16QI V4SF]) ;; Vec modes for move/logical/permute ops, include vector types for move not ;; otherwise handled by altivec (v2df, v2di, ti) ! (define_mode_iterator VM [V4SI V8HI V16QI V4SF V2DF V2DI V1TI TI]) ;; Like VM, except don't do TImode ! (define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI V1TI]) ! (define_mode_attr VI_char [(V2DI "d") (V4SI "w") (V8HI "h") (V16QI "b")]) ! (define_mode_attr VI_scalar [(V2DI "DI") (V4SI "SI") (V8HI "HI") (V16QI "QI")]) ! (define_mode_attr VI_unit [(V16QI "VECTOR_UNIT_ALTIVEC_P (V16QImode)") ! (V8HI "VECTOR_UNIT_ALTIVEC_P (V8HImode)") ! (V4SI "VECTOR_UNIT_ALTIVEC_P (V4SImode)") ! (V2DI "VECTOR_UNIT_P8_VECTOR_P (V2DImode)") ! (V1TI "VECTOR_UNIT_ALTIVEC_P (V1TImode)")]) ! ! ;; Vector pack/unpack ! (define_mode_iterator VP [V2DI V4SI V8HI]) ! (define_mode_attr VP_small [(V2DI "V4SI") (V4SI "V8HI") (V8HI "V16QI")]) ! (define_mode_attr VP_small_lc [(V2DI "v4si") (V4SI "v8hi") (V8HI "v16qi")]) ! (define_mode_attr VU_char [(V2DI "w") (V4SI "h") (V8HI "b")]) ;; Vector move instructions. (define_insn "*altivec_mov" *************** *** 378,387 **** ;; add (define_insn "add3" ! [(set (match_operand:VI 0 "register_operand" "=v") ! (plus:VI (match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v")))] ! "TARGET_ALTIVEC" "vaddum %0,%1,%2" [(set_attr "type" "vecsimple")]) --- 403,412 ---- ;; add (define_insn "add3" ! [(set (match_operand:VI2 0 "register_operand" "=v") ! (plus:VI2 (match_operand:VI2 1 "register_operand" "v") ! (match_operand:VI2 2 "register_operand" "v")))] ! "" "vaddum %0,%1,%2" [(set_attr "type" "vecsimple")]) *************** *** 398,414 **** (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VADDCUW))] ! "TARGET_ALTIVEC" "vaddcuw %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "altivec_vaddus" [(set (match_operand:VI 0 "register_operand" "=v") (unspec:VI [(match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v")] UNSPEC_VADDU)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "TARGET_ALTIVEC" "vaddus %0,%1,%2" [(set_attr "type" "vecsimple")]) --- 423,439 ---- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VADDCUW))] ! "VECTOR_UNIT_ALTIVEC_P (V4SImode)" "vaddcuw %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "altivec_vaddus" [(set (match_operand:VI 0 "register_operand" "=v") (unspec:VI [(match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v")] UNSPEC_VADDU)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "" "vaddus %0,%1,%2" [(set_attr "type" "vecsimple")]) *************** *** 418,433 **** (match_operand:VI 2 "register_operand" "v")] UNSPEC_VADDS)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "TARGET_ALTIVEC" "vaddss %0,%1,%2" [(set_attr "type" "vecsimple")]) ;; sub (define_insn "sub3" ! [(set (match_operand:VI 0 "register_operand" "=v") ! (minus:VI (match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v")))] ! "TARGET_ALTIVEC" "vsubum %0,%1,%2" [(set_attr "type" "vecsimple")]) --- 443,458 ---- (match_operand:VI 2 "register_operand" "v")] UNSPEC_VADDS)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "VECTOR_UNIT_ALTIVEC_P (mode)" "vaddss %0,%1,%2" [(set_attr "type" "vecsimple")]) ;; sub (define_insn "sub3" ! [(set (match_operand:VI2 0 "register_operand" "=v") ! (minus:VI2 (match_operand:VI2 1 "register_operand" "v") ! (match_operand:VI2 2 "register_operand" "v")))] ! "" "vsubum %0,%1,%2" [(set_attr "type" "vecsimple")]) *************** *** 444,450 **** (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUBCUW))] ! "TARGET_ALTIVEC" "vsubcuw %0,%1,%2" [(set_attr "type" "vecsimple")]) --- 469,475 ---- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUBCUW))] ! "VECTOR_UNIT_ALTIVEC_P (V4SImode)" "vsubcuw %0,%1,%2" [(set_attr "type" "vecsimple")]) *************** *** 454,460 **** (match_operand:VI 2 "register_operand" "v")] UNSPEC_VSUBU)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "TARGET_ALTIVEC" "vsubus %0,%1,%2" [(set_attr "type" "vecsimple")]) --- 479,485 ---- (match_operand:VI 2 "register_operand" "v")] UNSPEC_VSUBU)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "VECTOR_UNIT_ALTIVEC_P (mode)" "vsubus %0,%1,%2" [(set_attr "type" "vecsimple")]) *************** *** 464,470 **** (match_operand:VI 2 "register_operand" "v")] UNSPEC_VSUBS)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "TARGET_ALTIVEC" "vsubss %0,%1,%2" [(set_attr "type" "vecsimple")]) --- 489,495 ---- (match_operand:VI 2 "register_operand" "v")] UNSPEC_VSUBS)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "VECTOR_UNIT_ALTIVEC_P (mode)" "vsubss %0,%1,%2" [(set_attr "type" "vecsimple")]) *************** *** 483,489 **** (unspec:VI [(match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v")] UNSPEC_VAVGS))] ! "TARGET_ALTIVEC" "vavgs %0,%1,%2" [(set_attr "type" "vecsimple")]) --- 508,514 ---- (unspec:VI [(match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v")] UNSPEC_VAVGS))] ! "VECTOR_UNIT_ALTIVEC_P (mode)" "vavgs %0,%1,%2" [(set_attr "type" "vecsimple")]) *************** *** 492,522 **** (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v")] UNSPEC_VCMPBFP))] ! "TARGET_ALTIVEC" "vcmpbfp %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_eq" ! [(set (match_operand:VI 0 "altivec_register_operand" "=v") ! (eq:VI (match_operand:VI 1 "altivec_register_operand" "v") ! (match_operand:VI 2 "altivec_register_operand" "v")))] ! "TARGET_ALTIVEC" "vcmpequ %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_gt" ! [(set (match_operand:VI 0 "altivec_register_operand" "=v") ! (gt:VI (match_operand:VI 1 "altivec_register_operand" "v") ! (match_operand:VI 2 "altivec_register_operand" "v")))] ! "TARGET_ALTIVEC" "vcmpgts %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_gtu" ! [(set (match_operand:VI 0 "altivec_register_operand" "=v") ! (gtu:VI (match_operand:VI 1 "altivec_register_operand" "v") ! (match_operand:VI 2 "altivec_register_operand" "v")))] ! "TARGET_ALTIVEC" "vcmpgtu %0,%1,%2" [(set_attr "type" "veccmp")]) --- 517,547 ---- (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v")] UNSPEC_VCMPBFP))] ! "VECTOR_UNIT_ALTIVEC_P (V4SImode)" "vcmpbfp %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_eq" ! [(set (match_operand:VI2 0 "altivec_register_operand" "=v") ! (eq:VI2 (match_operand:VI2 1 "altivec_register_operand" "v") ! (match_operand:VI2 2 "altivec_register_operand" "v")))] ! "" "vcmpequ %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_gt" ! [(set (match_operand:VI2 0 "altivec_register_operand" "=v") ! (gt:VI2 (match_operand:VI2 1 "altivec_register_operand" "v") ! (match_operand:VI2 2 "altivec_register_operand" "v")))] ! "" "vcmpgts %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_gtu" ! [(set (match_operand:VI2 0 "altivec_register_operand" "=v") ! (gtu:VI2 (match_operand:VI2 1 "altivec_register_operand" "v") ! (match_operand:VI2 2 "altivec_register_operand" "v")))] ! "" "vcmpgtu %0,%1,%2" [(set_attr "type" "veccmp")]) *************** *** 642,648 **** convert_move (small_swap, swap, 0); low_product = gen_reg_rtx (V4SImode); ! emit_insn (gen_vec_widen_umult_odd_v8hi (low_product, one, two)); high_product = gen_reg_rtx (V4SImode); emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero)); --- 667,673 ---- convert_move (small_swap, swap, 0); low_product = gen_reg_rtx (V4SImode); ! emit_insn (gen_altivec_vmulouh (low_product, one, two)); high_product = gen_reg_rtx (V4SImode); emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero)); *************** *** 666,678 **** rtx high = gen_reg_rtx (V4SImode); rtx low = gen_reg_rtx (V4SImode); ! emit_insn (gen_vec_widen_smult_even_v8hi (even, operands[1], operands[2])); ! emit_insn (gen_vec_widen_smult_odd_v8hi (odd, operands[1], operands[2])); ! ! emit_insn (gen_altivec_vmrghw (high, even, odd)); ! emit_insn (gen_altivec_vmrglw (low, even, odd)); ! ! emit_insn (gen_altivec_vpkuwum (operands[0], high, low)); DONE; }") --- 691,712 ---- rtx high = gen_reg_rtx (V4SImode); rtx low = gen_reg_rtx (V4SImode); ! if (BYTES_BIG_ENDIAN) ! { ! emit_insn (gen_altivec_vmulesh (even, operands[1], operands[2])); ! emit_insn (gen_altivec_vmulosh (odd, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghw_direct (high, even, odd)); ! emit_insn (gen_altivec_vmrglw_direct (low, even, odd)); ! emit_insn (gen_altivec_vpkuwum_direct (operands[0], high, low)); ! } ! else ! { ! emit_insn (gen_altivec_vmulosh (even, operands[1], operands[2])); ! emit_insn (gen_altivec_vmulesh (odd, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghw_direct (high, odd, even)); ! emit_insn (gen_altivec_vmrglw_direct (low, odd, even)); ! emit_insn (gen_altivec_vpkuwum_direct (operands[0], low, high)); ! } DONE; }") *************** *** 744,761 **** ;; max (define_insn "umax3" ! [(set (match_operand:VI 0 "register_operand" "=v") ! (umax:VI (match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v")))] ! "TARGET_ALTIVEC" "vmaxu %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "smax3" ! [(set (match_operand:VI 0 "register_operand" "=v") ! (smax:VI (match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v")))] ! "TARGET_ALTIVEC" "vmaxs %0,%1,%2" [(set_attr "type" "vecsimple")]) --- 778,795 ---- ;; max (define_insn "umax3" ! [(set (match_operand:VI2 0 "register_operand" "=v") ! (umax:VI2 (match_operand:VI2 1 "register_operand" "v") ! (match_operand:VI2 2 "register_operand" "v")))] ! "" "vmaxu %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "smax3" ! [(set (match_operand:VI2 0 "register_operand" "=v") ! (smax:VI2 (match_operand:VI2 1 "register_operand" "v") ! (match_operand:VI2 2 "register_operand" "v")))] ! "" "vmaxs %0,%1,%2" [(set_attr "type" "vecsimple")]) *************** *** 768,785 **** [(set_attr "type" "veccmp")]) (define_insn "umin3" ! [(set (match_operand:VI 0 "register_operand" "=v") ! (umin:VI (match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v")))] ! "TARGET_ALTIVEC" "vminu %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "smin3" ! [(set (match_operand:VI 0 "register_operand" "=v") ! (smin:VI (match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v")))] ! "TARGET_ALTIVEC" "vmins %0,%1,%2" [(set_attr "type" "vecsimple")]) --- 802,819 ---- [(set_attr "type" "veccmp")]) (define_insn "umin3" ! [(set (match_operand:VI2 0 "register_operand" "=v") ! (umin:VI2 (match_operand:VI2 1 "register_operand" "v") ! (match_operand:VI2 2 "register_operand" "v")))] ! "" "vminu %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "smin3" ! [(set (match_operand:VI2 0 "register_operand" "=v") ! (smin:VI2 (match_operand:VI2 1 "register_operand" "v") ! (match_operand:VI2 2 "register_operand" "v")))] ! "" "vmins %0,%1,%2" [(set_attr "type" "vecsimple")]) *************** *** 823,831 **** "vmladduhm %0,%1,%2,%3" [(set_attr "type" "veccomplex")]) ! (define_insn "altivec_vmrghb" [(set (match_operand:V16QI 0 "register_operand" "=v") ! (vec_select:V16QI (vec_concat:V32QI (match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")) --- 857,897 ---- "vmladduhm %0,%1,%2,%3" [(set_attr "type" "veccomplex")]) ! (define_expand "altivec_vmrghb" ! [(use (match_operand:V16QI 0 "register_operand" "")) ! (use (match_operand:V16QI 1 "register_operand" "")) ! (use (match_operand:V16QI 2 "register_operand" ""))] ! "TARGET_ALTIVEC" ! { ! rtvec v; ! rtx x; ! ! /* Special handling for LE with -maltivec=be. */ ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! { ! v = gen_rtvec (16, GEN_INT (8), GEN_INT (24), GEN_INT (9), GEN_INT (25), ! GEN_INT (10), GEN_INT (26), GEN_INT (11), GEN_INT (27), ! GEN_INT (12), GEN_INT (28), GEN_INT (13), GEN_INT (29), ! GEN_INT (14), GEN_INT (30), GEN_INT (15), GEN_INT (31)); ! x = gen_rtx_VEC_CONCAT (V32QImode, operands[2], operands[1]); ! } ! else ! { ! v = gen_rtvec (16, GEN_INT (0), GEN_INT (16), GEN_INT (1), GEN_INT (17), ! GEN_INT (2), GEN_INT (18), GEN_INT (3), GEN_INT (19), ! GEN_INT (4), GEN_INT (20), GEN_INT (5), GEN_INT (21), ! GEN_INT (6), GEN_INT (22), GEN_INT (7), GEN_INT (23)); ! x = gen_rtx_VEC_CONCAT (V32QImode, operands[1], operands[2]); ! } ! ! x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v)); ! emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); ! DONE; ! }) ! ! (define_insn "*altivec_vmrghb_internal" [(set (match_operand:V16QI 0 "register_operand" "=v") ! (vec_select:V16QI (vec_concat:V32QI (match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")) *************** *** 838,849 **** (const_int 6) (const_int 22) (const_int 7) (const_int 23)])))] "TARGET_ALTIVEC" "vmrghb %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vmrghh" [(set (match_operand:V8HI 0 "register_operand" "=v") ! (vec_select:V8HI (vec_concat:V16HI (match_operand:V8HI 1 "register_operand" "v") (match_operand:V8HI 2 "register_operand" "v")) --- 904,957 ---- (const_int 6) (const_int 22) (const_int 7) (const_int 23)])))] "TARGET_ALTIVEC" + { + if (BYTES_BIG_ENDIAN) + return "vmrghb %0,%1,%2"; + else + return "vmrglb %0,%2,%1"; + } + [(set_attr "type" "vecperm")]) + + (define_insn "altivec_vmrghb_direct" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] + UNSPEC_VMRGH_DIRECT))] + "TARGET_ALTIVEC" "vmrghb %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_expand "altivec_vmrghh" ! [(use (match_operand:V8HI 0 "register_operand" "")) ! (use (match_operand:V8HI 1 "register_operand" "")) ! (use (match_operand:V8HI 2 "register_operand" ""))] ! "TARGET_ALTIVEC" ! { ! rtvec v; ! rtx x; ! ! /* Special handling for LE with -maltivec=be. */ ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! { ! v = gen_rtvec (8, GEN_INT (4), GEN_INT (12), GEN_INT (5), GEN_INT (13), ! GEN_INT (6), GEN_INT (14), GEN_INT (7), GEN_INT (15)); ! x = gen_rtx_VEC_CONCAT (V16HImode, operands[2], operands[1]); ! } ! else ! { ! v = gen_rtvec (8, GEN_INT (0), GEN_INT (8), GEN_INT (1), GEN_INT (9), ! GEN_INT (2), GEN_INT (10), GEN_INT (3), GEN_INT (11)); ! x = gen_rtx_VEC_CONCAT (V16HImode, operands[1], operands[2]); ! } ! ! x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v)); ! emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); ! DONE; ! }) ! ! (define_insn "*altivec_vmrghh_internal" [(set (match_operand:V8HI 0 "register_operand" "=v") ! (vec_select:V8HI (vec_concat:V16HI (match_operand:V8HI 1 "register_operand" "v") (match_operand:V8HI 2 "register_operand" "v")) *************** *** 852,861 **** (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))] "TARGET_ALTIVEC" "vmrghh %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vmrghw" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_select:V4SI (vec_concat:V8SI --- 960,1009 ---- (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))] "TARGET_ALTIVEC" + { + if (BYTES_BIG_ENDIAN) + return "vmrghh %0,%1,%2"; + else + return "vmrglh %0,%2,%1"; + } + [(set_attr "type" "vecperm")]) + + (define_insn "altivec_vmrghh_direct" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] + UNSPEC_VMRGH_DIRECT))] + "TARGET_ALTIVEC" "vmrghh %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_expand "altivec_vmrghw" ! [(use (match_operand:V4SI 0 "register_operand" "")) ! (use (match_operand:V4SI 1 "register_operand" "")) ! (use (match_operand:V4SI 2 "register_operand" ""))] ! "VECTOR_MEM_ALTIVEC_P (V4SImode)" ! { ! rtvec v; ! rtx x; ! ! /* Special handling for LE with -maltivec=be. */ ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! { ! v = gen_rtvec (4, GEN_INT (2), GEN_INT (6), GEN_INT (3), GEN_INT (7)); ! x = gen_rtx_VEC_CONCAT (V8SImode, operands[2], operands[1]); ! } ! else ! { ! v = gen_rtvec (4, GEN_INT (0), GEN_INT (4), GEN_INT (1), GEN_INT (5)); ! x = gen_rtx_VEC_CONCAT (V8SImode, operands[1], operands[2]); ! } ! ! x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v)); ! emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); ! DONE; ! }) ! ! (define_insn "*altivec_vmrghw_internal" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_select:V4SI (vec_concat:V8SI *************** *** 864,869 **** --- 1012,1031 ---- (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_ALTIVEC_P (V4SImode)" + { + if (BYTES_BIG_ENDIAN) + return "vmrghw %0,%1,%2"; + else + return "vmrglw %0,%2,%1"; + } + [(set_attr "type" "vecperm")]) + + (define_insn "altivec_vmrghw_direct" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] + UNSPEC_VMRGH_DIRECT))] + "TARGET_ALTIVEC" "vmrghw %0,%1,%2" [(set_attr "type" "vecperm")]) *************** *** 876,885 **** (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_ALTIVEC_P (V4SFmode)" ! "vmrghw %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vmrglb" [(set (match_operand:V16QI 0 "register_operand" "=v") (vec_select:V16QI (vec_concat:V32QI --- 1038,1084 ---- (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_ALTIVEC_P (V4SFmode)" ! { ! if (BYTES_BIG_ENDIAN) ! return "vmrghw %0,%1,%2"; ! else ! return "vmrglw %0,%2,%1"; ! } [(set_attr "type" "vecperm")]) ! (define_expand "altivec_vmrglb" ! [(use (match_operand:V16QI 0 "register_operand" "")) ! (use (match_operand:V16QI 1 "register_operand" "")) ! (use (match_operand:V16QI 2 "register_operand" ""))] ! "TARGET_ALTIVEC" ! { ! rtvec v; ! rtx x; ! ! /* Special handling for LE with -maltivec=be. */ ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! { ! v = gen_rtvec (16, GEN_INT (0), GEN_INT (16), GEN_INT (1), GEN_INT (17), ! GEN_INT (2), GEN_INT (18), GEN_INT (3), GEN_INT (19), ! GEN_INT (4), GEN_INT (20), GEN_INT (5), GEN_INT (21), ! GEN_INT (6), GEN_INT (22), GEN_INT (7), GEN_INT (23)); ! x = gen_rtx_VEC_CONCAT (V32QImode, operands[2], operands[1]); ! } ! else ! { ! v = gen_rtvec (16, GEN_INT (8), GEN_INT (24), GEN_INT (9), GEN_INT (25), ! GEN_INT (10), GEN_INT (26), GEN_INT (11), GEN_INT (27), ! GEN_INT (12), GEN_INT (28), GEN_INT (13), GEN_INT (29), ! GEN_INT (14), GEN_INT (30), GEN_INT (15), GEN_INT (31)); ! x = gen_rtx_VEC_CONCAT (V32QImode, operands[1], operands[2]); ! } ! ! x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v)); ! emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); ! DONE; ! }) ! ! (define_insn "*altivec_vmrglb_internal" [(set (match_operand:V16QI 0 "register_operand" "=v") (vec_select:V16QI (vec_concat:V32QI *************** *** 894,903 **** (const_int 14) (const_int 30) (const_int 15) (const_int 31)])))] "TARGET_ALTIVEC" "vmrglb %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vmrglh" [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_select:V8HI (vec_concat:V16HI --- 1093,1144 ---- (const_int 14) (const_int 30) (const_int 15) (const_int 31)])))] "TARGET_ALTIVEC" + { + if (BYTES_BIG_ENDIAN) + return "vmrglb %0,%1,%2"; + else + return "vmrghb %0,%2,%1"; + } + [(set_attr "type" "vecperm")]) + + (define_insn "altivec_vmrglb_direct" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] + UNSPEC_VMRGL_DIRECT))] + "TARGET_ALTIVEC" "vmrglb %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_expand "altivec_vmrglh" ! [(use (match_operand:V8HI 0 "register_operand" "")) ! (use (match_operand:V8HI 1 "register_operand" "")) ! (use (match_operand:V8HI 2 "register_operand" ""))] ! "TARGET_ALTIVEC" ! { ! rtvec v; ! rtx x; ! ! /* Special handling for LE with -maltivec=be. */ ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! { ! v = gen_rtvec (8, GEN_INT (0), GEN_INT (8), GEN_INT (1), GEN_INT (9), ! GEN_INT (2), GEN_INT (10), GEN_INT (3), GEN_INT (11)); ! x = gen_rtx_VEC_CONCAT (V16HImode, operands[2], operands[1]); ! } ! else ! { ! v = gen_rtvec (8, GEN_INT (4), GEN_INT (12), GEN_INT (5), GEN_INT (13), ! GEN_INT (6), GEN_INT (14), GEN_INT (7), GEN_INT (15)); ! x = gen_rtx_VEC_CONCAT (V16HImode, operands[1], operands[2]); ! } ! ! x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v)); ! emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); ! DONE; ! }) ! ! (define_insn "*altivec_vmrglh_internal" [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_select:V8HI (vec_concat:V16HI *************** *** 908,917 **** (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))] "TARGET_ALTIVEC" "vmrglh %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vmrglw" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_select:V4SI (vec_concat:V8SI --- 1149,1198 ---- (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))] "TARGET_ALTIVEC" + { + if (BYTES_BIG_ENDIAN) + return "vmrglh %0,%1,%2"; + else + return "vmrghh %0,%2,%1"; + } + [(set_attr "type" "vecperm")]) + + (define_insn "altivec_vmrglh_direct" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] + UNSPEC_VMRGL_DIRECT))] + "TARGET_ALTIVEC" "vmrglh %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_expand "altivec_vmrglw" ! [(use (match_operand:V4SI 0 "register_operand" "")) ! (use (match_operand:V4SI 1 "register_operand" "")) ! (use (match_operand:V4SI 2 "register_operand" ""))] ! "VECTOR_MEM_ALTIVEC_P (V4SImode)" ! { ! rtvec v; ! rtx x; ! ! /* Special handling for LE with -maltivec=be. */ ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! { ! v = gen_rtvec (4, GEN_INT (0), GEN_INT (4), GEN_INT (1), GEN_INT (5)); ! x = gen_rtx_VEC_CONCAT (V8SImode, operands[2], operands[1]); ! } ! else ! { ! v = gen_rtvec (4, GEN_INT (2), GEN_INT (6), GEN_INT (3), GEN_INT (7)); ! x = gen_rtx_VEC_CONCAT (V8SImode, operands[1], operands[2]); ! } ! ! x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v)); ! emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); ! DONE; ! }) ! ! (define_insn "*altivec_vmrglw_internal" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_select:V4SI (vec_concat:V8SI *************** *** 920,925 **** --- 1201,1220 ---- (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_ALTIVEC_P (V4SImode)" + { + if (BYTES_BIG_ENDIAN) + return "vmrglw %0,%1,%2"; + else + return "vmrghw %0,%2,%1"; + } + [(set_attr "type" "vecperm")]) + + (define_insn "altivec_vmrglw_direct" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] + UNSPEC_VMRGL_DIRECT))] + "TARGET_ALTIVEC" "vmrglw %0,%1,%2" [(set_attr "type" "vecperm")]) *************** *** 932,941 **** (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_ALTIVEC_P (V4SFmode)" ! "vmrglw %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "vec_widen_umult_even_v16qi" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] --- 1227,1380 ---- (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_ALTIVEC_P (V4SFmode)" ! { ! if (BYTES_BIG_ENDIAN) ! return "vmrglw %0,%1,%2"; ! else ! return "vmrghw %0,%2,%1"; ! } [(set_attr "type" "vecperm")]) ! ;; Power8 vector merge even/odd ! (define_insn "p8_vmrgew" ! [(set (match_operand:V4SI 0 "register_operand" "=v") ! (vec_select:V4SI ! (vec_concat:V8SI ! (match_operand:V4SI 1 "register_operand" "v") ! (match_operand:V4SI 2 "register_operand" "v")) ! (parallel [(const_int 0) (const_int 4) ! (const_int 2) (const_int 6)])))] ! "TARGET_P8_VECTOR" ! { ! if (BYTES_BIG_ENDIAN) ! return "vmrgew %0,%1,%2"; ! else ! return "vmrgow %0,%2,%1"; ! } ! [(set_attr "type" "vecperm")]) ! ! (define_insn "p8_vmrgow" ! [(set (match_operand:V4SI 0 "register_operand" "=v") ! (vec_select:V4SI ! (vec_concat:V8SI ! (match_operand:V4SI 1 "register_operand" "v") ! (match_operand:V4SI 2 "register_operand" "v")) ! (parallel [(const_int 1) (const_int 5) ! (const_int 3) (const_int 7)])))] ! "TARGET_P8_VECTOR" ! { ! if (BYTES_BIG_ENDIAN) ! return "vmrgow %0,%1,%2"; ! else ! return "vmrgew %0,%2,%1"; ! } ! [(set_attr "type" "vecperm")]) ! ! (define_expand "vec_widen_umult_even_v16qi" ! [(use (match_operand:V8HI 0 "register_operand" "")) ! (use (match_operand:V16QI 1 "register_operand" "")) ! (use (match_operand:V16QI 2 "register_operand" ""))] ! "TARGET_ALTIVEC" ! { ! if (VECTOR_ELT_ORDER_BIG) ! emit_insn (gen_altivec_vmuleub (operands[0], operands[1], operands[2])); ! else ! emit_insn (gen_altivec_vmuloub (operands[0], operands[1], operands[2])); ! DONE; ! }) ! ! (define_expand "vec_widen_smult_even_v16qi" ! [(use (match_operand:V8HI 0 "register_operand" "")) ! (use (match_operand:V16QI 1 "register_operand" "")) ! (use (match_operand:V16QI 2 "register_operand" ""))] ! "TARGET_ALTIVEC" ! { ! if (VECTOR_ELT_ORDER_BIG) ! emit_insn (gen_altivec_vmulesb (operands[0], operands[1], operands[2])); ! else ! emit_insn (gen_altivec_vmulosb (operands[0], operands[1], operands[2])); ! DONE; ! }) ! ! (define_expand "vec_widen_umult_even_v8hi" ! [(use (match_operand:V4SI 0 "register_operand" "")) ! (use (match_operand:V8HI 1 "register_operand" "")) ! (use (match_operand:V8HI 2 "register_operand" ""))] ! "TARGET_ALTIVEC" ! { ! if (VECTOR_ELT_ORDER_BIG) ! emit_insn (gen_altivec_vmuleuh (operands[0], operands[1], operands[2])); ! else ! emit_insn (gen_altivec_vmulouh (operands[0], operands[1], operands[2])); ! DONE; ! }) ! ! (define_expand "vec_widen_smult_even_v8hi" ! [(use (match_operand:V4SI 0 "register_operand" "")) ! (use (match_operand:V8HI 1 "register_operand" "")) ! (use (match_operand:V8HI 2 "register_operand" ""))] ! "TARGET_ALTIVEC" ! { ! if (VECTOR_ELT_ORDER_BIG) ! emit_insn (gen_altivec_vmulesh (operands[0], operands[1], operands[2])); ! else ! emit_insn (gen_altivec_vmulosh (operands[0], operands[1], operands[2])); ! DONE; ! }) ! ! (define_expand "vec_widen_umult_odd_v16qi" ! [(use (match_operand:V8HI 0 "register_operand" "")) ! (use (match_operand:V16QI 1 "register_operand" "")) ! (use (match_operand:V16QI 2 "register_operand" ""))] ! "TARGET_ALTIVEC" ! { ! if (VECTOR_ELT_ORDER_BIG) ! emit_insn (gen_altivec_vmuloub (operands[0], operands[1], operands[2])); ! else ! emit_insn (gen_altivec_vmuleub (operands[0], operands[1], operands[2])); ! DONE; ! }) ! ! (define_expand "vec_widen_smult_odd_v16qi" ! [(use (match_operand:V8HI 0 "register_operand" "")) ! (use (match_operand:V16QI 1 "register_operand" "")) ! (use (match_operand:V16QI 2 "register_operand" ""))] ! "TARGET_ALTIVEC" ! { ! if (VECTOR_ELT_ORDER_BIG) ! emit_insn (gen_altivec_vmulosb (operands[0], operands[1], operands[2])); ! else ! emit_insn (gen_altivec_vmulesb (operands[0], operands[1], operands[2])); ! DONE; ! }) ! ! (define_expand "vec_widen_umult_odd_v8hi" ! [(use (match_operand:V4SI 0 "register_operand" "")) ! (use (match_operand:V8HI 1 "register_operand" "")) ! (use (match_operand:V8HI 2 "register_operand" ""))] ! "TARGET_ALTIVEC" ! { ! if (VECTOR_ELT_ORDER_BIG) ! emit_insn (gen_altivec_vmulouh (operands[0], operands[1], operands[2])); ! else ! emit_insn (gen_altivec_vmuleuh (operands[0], operands[1], operands[2])); ! DONE; ! }) ! ! (define_expand "vec_widen_smult_odd_v8hi" ! [(use (match_operand:V4SI 0 "register_operand" "")) ! (use (match_operand:V8HI 1 "register_operand" "")) ! (use (match_operand:V8HI 2 "register_operand" ""))] ! "TARGET_ALTIVEC" ! { ! if (VECTOR_ELT_ORDER_BIG) ! emit_insn (gen_altivec_vmulosh (operands[0], operands[1], operands[2])); ! else ! emit_insn (gen_altivec_vmulesh (operands[0], operands[1], operands[2])); ! DONE; ! }) ! ! (define_insn "altivec_vmuleub" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] *************** *** 944,986 **** "vmuleub %0,%1,%2" [(set_attr "type" "veccomplex")]) ! (define_insn "vec_widen_smult_even_v16qi" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] ! UNSPEC_VMULESB))] ! "TARGET_ALTIVEC" ! "vmulesb %0,%1,%2" ! [(set_attr "type" "veccomplex")]) ! ! (define_insn "vec_widen_umult_even_v8hi" ! [(set (match_operand:V4SI 0 "register_operand" "=v") ! (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") ! (match_operand:V8HI 2 "register_operand" "v")] ! UNSPEC_VMULEUH))] ! "TARGET_ALTIVEC" ! "vmuleuh %0,%1,%2" ! [(set_attr "type" "veccomplex")]) ! ! (define_insn "vec_widen_smult_even_v8hi" ! [(set (match_operand:V4SI 0 "register_operand" "=v") ! (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") ! (match_operand:V8HI 2 "register_operand" "v")] ! UNSPEC_VMULESH))] "TARGET_ALTIVEC" ! "vmulesh %0,%1,%2" [(set_attr "type" "veccomplex")]) ! (define_insn "vec_widen_umult_odd_v16qi" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] ! UNSPEC_VMULOUB))] "TARGET_ALTIVEC" ! "vmuloub %0,%1,%2" [(set_attr "type" "veccomplex")]) ! (define_insn "vec_widen_smult_odd_v16qi" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] --- 1383,1407 ---- "vmuleub %0,%1,%2" [(set_attr "type" "veccomplex")]) ! (define_insn "altivec_vmuloub" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] ! UNSPEC_VMULOUB))] "TARGET_ALTIVEC" ! "vmuloub %0,%1,%2" [(set_attr "type" "veccomplex")]) ! (define_insn "altivec_vmulesb" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] ! UNSPEC_VMULESB))] "TARGET_ALTIVEC" ! "vmulesb %0,%1,%2" [(set_attr "type" "veccomplex")]) ! (define_insn "altivec_vmulosb" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] *************** *** 989,995 **** "vmulosb %0,%1,%2" [(set_attr "type" "veccomplex")]) ! (define_insn "vec_widen_umult_odd_v8hi" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (match_operand:V8HI 2 "register_operand" "v")] --- 1410,1425 ---- "vmulosb %0,%1,%2" [(set_attr "type" "veccomplex")]) ! (define_insn "altivec_vmuleuh" ! [(set (match_operand:V4SI 0 "register_operand" "=v") ! (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") ! (match_operand:V8HI 2 "register_operand" "v")] ! UNSPEC_VMULEUH))] ! "TARGET_ALTIVEC" ! "vmuleuh %0,%1,%2" ! [(set_attr "type" "veccomplex")]) ! ! (define_insn "altivec_vmulouh" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (match_operand:V8HI 2 "register_operand" "v")] *************** *** 998,1155 **** "vmulouh %0,%1,%2" [(set_attr "type" "veccomplex")]) ! (define_insn "vec_widen_smult_odd_v8hi" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (match_operand:V8HI 2 "register_operand" "v")] ! UNSPEC_VMULOSH))] "TARGET_ALTIVEC" ! "vmulosh %0,%1,%2" [(set_attr "type" "veccomplex")]) ! ! ;; logical ops. Have the logical ops follow the memory ops in ! ;; terms of whether to prefer VSX or Altivec ! ! (define_insn "*altivec_and3" ! [(set (match_operand:VM 0 "register_operand" "=v") ! (and:VM (match_operand:VM 1 "register_operand" "v") ! (match_operand:VM 2 "register_operand" "v")))] ! "VECTOR_MEM_ALTIVEC_P (mode)" ! "vand %0,%1,%2" ! [(set_attr "type" "vecsimple")]) ! ! (define_insn "*altivec_ior3" ! [(set (match_operand:VM 0 "register_operand" "=v") ! (ior:VM (match_operand:VM 1 "register_operand" "v") ! (match_operand:VM 2 "register_operand" "v")))] ! "VECTOR_MEM_ALTIVEC_P (mode)" ! "vor %0,%1,%2" ! [(set_attr "type" "vecsimple")]) ! ! (define_insn "*altivec_xor3" ! [(set (match_operand:VM 0 "register_operand" "=v") ! (xor:VM (match_operand:VM 1 "register_operand" "v") ! (match_operand:VM 2 "register_operand" "v")))] ! "VECTOR_MEM_ALTIVEC_P (mode)" ! "vxor %0,%1,%2" ! [(set_attr "type" "vecsimple")]) ! ! (define_insn "*altivec_one_cmpl2" ! [(set (match_operand:VM 0 "register_operand" "=v") ! (not:VM (match_operand:VM 1 "register_operand" "v")))] ! "VECTOR_MEM_ALTIVEC_P (mode)" ! "vnor %0,%1,%1" ! [(set_attr "type" "vecsimple")]) ! ! (define_insn "*altivec_nor3" ! [(set (match_operand:VM 0 "register_operand" "=v") ! (not:VM (ior:VM (match_operand:VM 1 "register_operand" "v") ! (match_operand:VM 2 "register_operand" "v"))))] ! "VECTOR_MEM_ALTIVEC_P (mode)" ! "vnor %0,%1,%2" ! [(set_attr "type" "vecsimple")]) ! ! (define_insn "*altivec_andc3" ! [(set (match_operand:VM 0 "register_operand" "=v") ! (and:VM (not:VM (match_operand:VM 2 "register_operand" "v")) ! (match_operand:VM 1 "register_operand" "v")))] ! "VECTOR_MEM_ALTIVEC_P (mode)" ! "vandc %0,%1,%2" ! [(set_attr "type" "vecsimple")]) ! ! (define_insn "altivec_vpkuhum" ! [(set (match_operand:V16QI 0 "register_operand" "=v") ! (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") ! (match_operand:V8HI 2 "register_operand" "v")] ! UNSPEC_VPKUHUM))] "TARGET_ALTIVEC" ! "vpkuhum %0,%1,%2" ! [(set_attr "type" "vecperm")]) - (define_insn "altivec_vpkuwum" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] - UNSPEC_VPKUWUM))] - "TARGET_ALTIVEC" - "vpkuwum %0,%1,%2" - [(set_attr "type" "vecperm")]) (define_insn "altivec_vpkpx" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VPKPX))] "TARGET_ALTIVEC" ! "vpkpx %0,%1,%2" ! [(set_attr "type" "vecperm")]) ! ! (define_insn "altivec_vpkshss" ! [(set (match_operand:V16QI 0 "register_operand" "=v") ! (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") ! (match_operand:V8HI 2 "register_operand" "v")] ! UNSPEC_VPKSHSS)) ! (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "TARGET_ALTIVEC" ! "vpkshss %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vpkswss" ! [(set (match_operand:V8HI 0 "register_operand" "=v") ! (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") ! (match_operand:V4SI 2 "register_operand" "v")] ! UNSPEC_VPKSWSS)) ! (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "TARGET_ALTIVEC" ! "vpkswss %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vpkuhus" ! [(set (match_operand:V16QI 0 "register_operand" "=v") ! (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") ! (match_operand:V8HI 2 "register_operand" "v")] ! UNSPEC_VPKUHUS)) ! (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "TARGET_ALTIVEC" ! "vpkuhus %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vpkshus" ! [(set (match_operand:V16QI 0 "register_operand" "=v") ! (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") ! (match_operand:V8HI 2 "register_operand" "v")] ! UNSPEC_VPKSHUS)) ! (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "TARGET_ALTIVEC" ! "vpkshus %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vpkuwus" ! [(set (match_operand:V8HI 0 "register_operand" "=v") ! (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") ! (match_operand:V4SI 2 "register_operand" "v")] ! UNSPEC_VPKUWUS)) ! (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "TARGET_ALTIVEC" ! "vpkuwus %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vpkswus" ! [(set (match_operand:V8HI 0 "register_operand" "=v") ! (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") ! (match_operand:V4SI 2 "register_operand" "v")] ! UNSPEC_VPKSWUS)) ! (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] ! "TARGET_ALTIVEC" ! "vpkswus %0,%1,%2" [(set_attr "type" "vecperm")]) (define_insn "*altivec_vrl" ! [(set (match_operand:VI 0 "register_operand" "=v") ! (rotate:VI (match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v")))] ! "TARGET_ALTIVEC" "vrl %0,%1,%2" [(set_attr "type" "vecsimple")]) --- 1428,1548 ---- "vmulouh %0,%1,%2" [(set_attr "type" "veccomplex")]) ! (define_insn "altivec_vmulesh" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (match_operand:V8HI 2 "register_operand" "v")] ! UNSPEC_VMULESH))] "TARGET_ALTIVEC" ! "vmulesh %0,%1,%2" [(set_attr "type" "veccomplex")]) ! (define_insn "altivec_vmulosh" ! [(set (match_operand:V4SI 0 "register_operand" "=v") ! (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") ! (match_operand:V8HI 2 "register_operand" "v")] ! UNSPEC_VMULOSH))] "TARGET_ALTIVEC" ! "vmulosh %0,%1,%2" ! [(set_attr "type" "veccomplex")]) + ;; Vector pack/unpack (define_insn "altivec_vpkpx" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VPKPX))] "TARGET_ALTIVEC" ! "* ! { ! if (VECTOR_ELT_ORDER_BIG) ! return \"vpkpx %0,%1,%2\"; ! else ! return \"vpkpx %0,%2,%1\"; ! }" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vpksss" ! [(set (match_operand: 0 "register_operand" "=v") ! (unspec: [(match_operand:VP 1 "register_operand" "v") ! (match_operand:VP 2 "register_operand" "v")] ! UNSPEC_VPACK_SIGN_SIGN_SAT))] ! "" ! "* ! { ! if (VECTOR_ELT_ORDER_BIG) ! return \"vpksss %0,%1,%2\"; ! else ! return \"vpksss %0,%2,%1\"; ! }" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vpksus" ! [(set (match_operand: 0 "register_operand" "=v") ! (unspec: [(match_operand:VP 1 "register_operand" "v") ! (match_operand:VP 2 "register_operand" "v")] ! UNSPEC_VPACK_SIGN_UNS_SAT))] ! "" ! "* ! { ! if (VECTOR_ELT_ORDER_BIG) ! return \"vpksus %0,%1,%2\"; ! else ! return \"vpksus %0,%2,%1\"; ! }" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vpkuus" ! [(set (match_operand: 0 "register_operand" "=v") ! (unspec: [(match_operand:VP 1 "register_operand" "v") ! (match_operand:VP 2 "register_operand" "v")] ! UNSPEC_VPACK_UNS_UNS_SAT))] ! "" ! "* ! { ! if (VECTOR_ELT_ORDER_BIG) ! return \"vpkuus %0,%1,%2\"; ! else ! return \"vpkuus %0,%2,%1\"; ! }" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vpkuum" ! [(set (match_operand: 0 "register_operand" "=v") ! (unspec: [(match_operand:VP 1 "register_operand" "v") ! (match_operand:VP 2 "register_operand" "v")] ! UNSPEC_VPACK_UNS_UNS_MOD))] ! "" ! "* ! { ! if (VECTOR_ELT_ORDER_BIG) ! return \"vpkuum %0,%1,%2\"; ! else ! return \"vpkuum %0,%2,%1\"; ! }" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vpkuum_direct" ! [(set (match_operand: 0 "register_operand" "=v") ! (unspec: [(match_operand:VP 1 "register_operand" "v") ! (match_operand:VP 2 "register_operand" "v")] ! UNSPEC_VPACK_UNS_UNS_MOD_DIRECT))] ! "" ! "* ! { ! if (BYTES_BIG_ENDIAN) ! return \"vpkuum %0,%1,%2\"; ! else ! return \"vpkuum %0,%2,%1\"; ! }" [(set_attr "type" "vecperm")]) (define_insn "*altivec_vrl" ! [(set (match_operand:VI2 0 "register_operand" "=v") ! (rotate:VI2 (match_operand:VI2 1 "register_operand" "v") ! (match_operand:VI2 2 "register_operand" "v")))] ! "" "vrl %0,%1,%2" [(set_attr "type" "vecsimple")]) *************** *** 1172,1197 **** [(set_attr "type" "vecperm")]) (define_insn "*altivec_vsl" ! [(set (match_operand:VI 0 "register_operand" "=v") ! (ashift:VI (match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v")))] ! "TARGET_ALTIVEC" "vsl %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "*altivec_vsr" ! [(set (match_operand:VI 0 "register_operand" "=v") ! (lshiftrt:VI (match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v")))] ! "TARGET_ALTIVEC" "vsr %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "*altivec_vsra" ! [(set (match_operand:VI 0 "register_operand" "=v") ! (ashiftrt:VI (match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v")))] ! "TARGET_ALTIVEC" "vsra %0,%1,%2" [(set_attr "type" "vecsimple")]) --- 1565,1590 ---- [(set_attr "type" "vecperm")]) (define_insn "*altivec_vsl" ! [(set (match_operand:VI2 0 "register_operand" "=v") ! (ashift:VI2 (match_operand:VI2 1 "register_operand" "v") ! (match_operand:VI2 2 "register_operand" "v")))] ! "" "vsl %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "*altivec_vsr" ! [(set (match_operand:VI2 0 "register_operand" "=v") ! (lshiftrt:VI2 (match_operand:VI2 1 "register_operand" "v") ! (match_operand:VI2 2 "register_operand" "v")))] ! "" "vsr %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "*altivec_vsra" ! [(set (match_operand:VI2 0 "register_operand" "=v") ! (ashiftrt:VI2 (match_operand:VI2 1 "register_operand" "v") ! (match_operand:VI2 2 "register_operand" "v")))] ! "" "vsra %0,%1,%2" [(set_attr "type" "vecsimple")]) *************** *** 1233,1296 **** "vsum4ss %0,%1,%2" [(set_attr "type" "veccomplex")]) (define_insn "altivec_vsum2sws" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUM2SWS)) ! (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "TARGET_ALTIVEC" ! "vsum2sws %0,%1,%2" ! [(set_attr "type" "veccomplex")]) (define_insn "altivec_vsumsws" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUMSWS)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "TARGET_ALTIVEC" "vsumsws %0,%1,%2" [(set_attr "type" "veccomplex")]) ! (define_insn "altivec_vspltb" [(set (match_operand:V16QI 0 "register_operand" "=v") (vec_duplicate:V16QI (vec_select:QI (match_operand:V16QI 1 "register_operand" "v") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "")]))))] "TARGET_ALTIVEC" "vspltb %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vsplth" [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_duplicate:V8HI (vec_select:HI (match_operand:V8HI 1 "register_operand" "v") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "")]))))] "TARGET_ALTIVEC" "vsplth %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vspltw" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_duplicate:V4SI (vec_select:SI (match_operand:V4SI 1 "register_operand" "v") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))] "TARGET_ALTIVEC" "vspltw %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vspltsf" [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_duplicate:V4SF (vec_select:SF (match_operand:V4SF 1 "register_operand" "v") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))] "VECTOR_UNIT_ALTIVEC_P (V4SFmode)" ! "vspltw %0,%1,%2" [(set_attr "type" "vecperm")]) (define_insn "altivec_vspltis" --- 1626,1867 ---- "vsum4ss %0,%1,%2" [(set_attr "type" "veccomplex")]) + ;; FIXME: For the following two patterns, the scratch should only be + ;; allocated for !VECTOR_ELT_ORDER_BIG, and the instructions should + ;; be emitted separately. (define_insn "altivec_vsum2sws" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUM2SWS)) ! (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR)) ! (clobber (match_scratch:V4SI 3 "=v"))] "TARGET_ALTIVEC" ! { ! if (VECTOR_ELT_ORDER_BIG) ! return "vsum2sws %0,%1,%2"; ! else ! return "vsldoi %3,%2,%2,12\n\tvsum2sws %3,%1,%3\n\tvsldoi %0,%3,%3,4"; ! } ! [(set_attr "type" "veccomplex") ! (set (attr "length") ! (if_then_else ! (match_test "VECTOR_ELT_ORDER_BIG") ! (const_string "4") ! (const_string "12")))]) (define_insn "altivec_vsumsws" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUMSWS)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR)) + (clobber (match_scratch:V4SI 3 "=v"))] + "TARGET_ALTIVEC" + { + if (VECTOR_ELT_ORDER_BIG) + return "vsumsws %0,%1,%2"; + else + return "vspltw %3,%2,0\n\tvsumsws %3,%1,%3\n\tvsldoi %0,%3,%3,12"; + } + [(set_attr "type" "veccomplex") + (set (attr "length") + (if_then_else + (match_test "(VECTOR_ELT_ORDER_BIG)") + (const_string "4") + (const_string "12")))]) + + (define_insn "altivec_vsumsws_direct" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] + UNSPEC_VSUMSWS_DIRECT)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "TARGET_ALTIVEC" "vsumsws %0,%1,%2" [(set_attr "type" "veccomplex")]) ! (define_expand "altivec_vspltb" ! [(use (match_operand:V16QI 0 "register_operand" "")) ! (use (match_operand:V16QI 1 "register_operand" "")) ! (use (match_operand:QI 2 "u5bit_cint_operand" ""))] ! "TARGET_ALTIVEC" ! { ! rtvec v; ! rtx x; ! ! /* Special handling for LE with -maltivec=be. We have to reflect ! the actual selected index for the splat in the RTL. */ ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! operands[2] = GEN_INT (15 - INTVAL (operands[2])); ! ! v = gen_rtvec (1, operands[2]); ! x = gen_rtx_VEC_SELECT (QImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v)); ! x = gen_rtx_VEC_DUPLICATE (V16QImode, x); ! emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); ! DONE; ! }) ! ! (define_insn "*altivec_vspltb_internal" [(set (match_operand:V16QI 0 "register_operand" "=v") (vec_duplicate:V16QI (vec_select:QI (match_operand:V16QI 1 "register_operand" "v") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "")]))))] "TARGET_ALTIVEC" + { + /* For true LE, this adjusts the selected index. For LE with + -maltivec=be, this reverses what was done in the define_expand + because the instruction already has big-endian bias. */ + if (!BYTES_BIG_ENDIAN) + operands[2] = GEN_INT (15 - INTVAL (operands[2])); + + return "vspltb %0,%1,%2"; + } + [(set_attr "type" "vecperm")]) + + (define_insn "altivec_vspltb_direct" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:QI 2 "u5bit_cint_operand" "i")] + UNSPEC_VSPLT_DIRECT))] + "TARGET_ALTIVEC" "vspltb %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_expand "altivec_vsplth" ! [(use (match_operand:V8HI 0 "register_operand" "")) ! (use (match_operand:V8HI 1 "register_operand" "")) ! (use (match_operand:QI 2 "u5bit_cint_operand" ""))] ! "TARGET_ALTIVEC" ! { ! rtvec v; ! rtx x; ! ! /* Special handling for LE with -maltivec=be. We have to reflect ! the actual selected index for the splat in the RTL. */ ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! operands[2] = GEN_INT (7 - INTVAL (operands[2])); ! ! v = gen_rtvec (1, operands[2]); ! x = gen_rtx_VEC_SELECT (HImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v)); ! x = gen_rtx_VEC_DUPLICATE (V8HImode, x); ! emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); ! DONE; ! }) ! ! (define_insn "*altivec_vsplth_internal" [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_duplicate:V8HI (vec_select:HI (match_operand:V8HI 1 "register_operand" "v") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "")]))))] "TARGET_ALTIVEC" + { + /* For true LE, this adjusts the selected index. For LE with + -maltivec=be, this reverses what was done in the define_expand + because the instruction already has big-endian bias. */ + if (!BYTES_BIG_ENDIAN) + operands[2] = GEN_INT (7 - INTVAL (operands[2])); + + return "vsplth %0,%1,%2"; + } + [(set_attr "type" "vecperm")]) + + (define_insn "altivec_vsplth_direct" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:QI 2 "u5bit_cint_operand" "i")] + UNSPEC_VSPLT_DIRECT))] + "TARGET_ALTIVEC" "vsplth %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_expand "altivec_vspltw" ! [(use (match_operand:V4SI 0 "register_operand" "")) ! (use (match_operand:V4SI 1 "register_operand" "")) ! (use (match_operand:QI 2 "u5bit_cint_operand" ""))] ! "TARGET_ALTIVEC" ! { ! rtvec v; ! rtx x; ! ! /* Special handling for LE with -maltivec=be. We have to reflect ! the actual selected index for the splat in the RTL. */ ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! operands[2] = GEN_INT (3 - INTVAL (operands[2])); ! ! v = gen_rtvec (1, operands[2]); ! x = gen_rtx_VEC_SELECT (SImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v)); ! x = gen_rtx_VEC_DUPLICATE (V4SImode, x); ! emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); ! DONE; ! }) ! ! (define_insn "*altivec_vspltw_internal" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_duplicate:V4SI (vec_select:SI (match_operand:V4SI 1 "register_operand" "v") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))] "TARGET_ALTIVEC" + { + /* For true LE, this adjusts the selected index. For LE with + -maltivec=be, this reverses what was done in the define_expand + because the instruction already has big-endian bias. */ + if (!BYTES_BIG_ENDIAN) + operands[2] = GEN_INT (3 - INTVAL (operands[2])); + + return "vspltw %0,%1,%2"; + } + [(set_attr "type" "vecperm")]) + + (define_insn "altivec_vspltw_direct" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:QI 2 "u5bit_cint_operand" "i")] + UNSPEC_VSPLT_DIRECT))] + "TARGET_ALTIVEC" "vspltw %0,%1,%2" [(set_attr "type" "vecperm")]) ! (define_expand "altivec_vspltsf" ! [(use (match_operand:V4SF 0 "register_operand" "")) ! (use (match_operand:V4SF 1 "register_operand" "")) ! (use (match_operand:QI 2 "u5bit_cint_operand" ""))] ! "TARGET_ALTIVEC" ! { ! rtvec v; ! rtx x; ! ! /* Special handling for LE with -maltivec=be. We have to reflect ! the actual selected index for the splat in the RTL. */ ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! operands[2] = GEN_INT (3 - INTVAL (operands[2])); ! ! v = gen_rtvec (1, operands[2]); ! x = gen_rtx_VEC_SELECT (SFmode, operands[1], gen_rtx_PARALLEL (VOIDmode, v)); ! x = gen_rtx_VEC_DUPLICATE (V4SFmode, x); ! emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); ! DONE; ! }) ! ! (define_insn "*altivec_vspltsf_internal" [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_duplicate:V4SF (vec_select:SF (match_operand:V4SF 1 "register_operand" "v") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))] "VECTOR_UNIT_ALTIVEC_P (V4SFmode)" ! { ! /* For true LE, this adjusts the selected index. For LE with ! -maltivec=be, this reverses what was done in the define_expand ! because the instruction already has big-endian bias. */ ! if (!BYTES_BIG_ENDIAN) ! operands[2] = GEN_INT (3 - INTVAL (operands[2])); ! ! return "vspltw %0,%1,%2"; ! } [(set_attr "type" "vecperm")]) (define_insn "altivec_vspltis" *************** *** 1308,1314 **** "vrfiz %0,%1" [(set_attr "type" "vecfloat")]) ! (define_insn "altivec_vperm_" [(set (match_operand:VM 0 "register_operand" "=v") (unspec:VM [(match_operand:VM 1 "register_operand" "v") (match_operand:VM 2 "register_operand" "v") --- 1879,1900 ---- "vrfiz %0,%1" [(set_attr "type" "vecfloat")]) ! (define_expand "altivec_vperm_" ! [(set (match_operand:VM 0 "register_operand" "=v") ! (unspec:VM [(match_operand:VM 1 "register_operand" "v") ! (match_operand:VM 2 "register_operand" "v") ! (match_operand:V16QI 3 "register_operand" "v")] ! UNSPEC_VPERM))] ! "TARGET_ALTIVEC" ! { ! if (!VECTOR_ELT_ORDER_BIG) ! { ! altivec_expand_vec_perm_le (operands); ! DONE; ! } ! }) ! ! (define_insn "*altivec_vperm__internal" [(set (match_operand:VM 0 "register_operand" "=v") (unspec:VM [(match_operand:VM 1 "register_operand" "v") (match_operand:VM 2 "register_operand" "v") *************** *** 1318,1324 **** "vperm %0,%1,%2,%3" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vperm__uns" [(set (match_operand:VM 0 "register_operand" "=v") (unspec:VM [(match_operand:VM 1 "register_operand" "v") (match_operand:VM 2 "register_operand" "v") --- 1904,1925 ---- "vperm %0,%1,%2,%3" [(set_attr "type" "vecperm")]) ! (define_expand "altivec_vperm__uns" ! [(set (match_operand:VM 0 "register_operand" "=v") ! (unspec:VM [(match_operand:VM 1 "register_operand" "v") ! (match_operand:VM 2 "register_operand" "v") ! (match_operand:V16QI 3 "register_operand" "v")] ! UNSPEC_VPERM_UNS))] ! "TARGET_ALTIVEC" ! { ! if (!VECTOR_ELT_ORDER_BIG) ! { ! altivec_expand_vec_perm_le (operands); ! DONE; ! } ! }) ! ! (define_insn "*altivec_vperm__uns_internal" [(set (match_operand:VM 0 "register_operand" "=v") (unspec:VM [(match_operand:VM 1 "register_operand" "v") (match_operand:VM 2 "register_operand" "v") *************** *** 1335,1341 **** (match_operand:V16QI 3 "register_operand" "")] UNSPEC_VPERM))] "TARGET_ALTIVEC" ! "") (define_expand "vec_perm_constv16qi" [(match_operand:V16QI 0 "register_operand" "") --- 1936,1947 ---- (match_operand:V16QI 3 "register_operand" "")] UNSPEC_VPERM))] "TARGET_ALTIVEC" ! { ! if (!BYTES_BIG_ENDIAN) { ! altivec_expand_vec_perm_le (operands); ! DONE; ! } ! }) (define_expand "vec_perm_constv16qi" [(match_operand:V16QI 0 "register_operand" "") *************** *** 1476,1564 **** "vsldoi %0,%1,%2,%3" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vupkhsb" ! [(set (match_operand:V8HI 0 "register_operand" "=v") ! (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] ! UNSPEC_VUPKHSB))] ! "TARGET_ALTIVEC" ! "vupkhsb %0,%1" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vupkhpx" ! [(set (match_operand:V4SI 0 "register_operand" "=v") ! (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] ! UNSPEC_VUPKHPX))] ! "TARGET_ALTIVEC" ! "vupkhpx %0,%1" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vupkhsh" ! [(set (match_operand:V4SI 0 "register_operand" "=v") ! (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] ! UNSPEC_VUPKHSH))] ! "TARGET_ALTIVEC" ! "vupkhsh %0,%1" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vupklsb" ! [(set (match_operand:V8HI 0 "register_operand" "=v") ! (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] ! UNSPEC_VUPKLSB))] ! "TARGET_ALTIVEC" ! "vupklsb %0,%1" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vupklpx" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] ! UNSPEC_VUPKLPX))] "TARGET_ALTIVEC" ! "vupklpx %0,%1" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vupklsh" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] ! UNSPEC_VUPKLSH))] "TARGET_ALTIVEC" ! "vupklsh %0,%1" [(set_attr "type" "vecperm")]) ;; Compare vectors producing a vector result and a predicate, setting CR6 to ;; indicate a combined status (define_insn "*altivec_vcmpequ_p" [(set (reg:CC 74) ! (unspec:CC [(eq:CC (match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v"))] UNSPEC_PREDICATE)) ! (set (match_operand:VI 0 "register_operand" "=v") ! (eq:VI (match_dup 1) ! (match_dup 2)))] ! "VECTOR_UNIT_ALTIVEC_P (mode)" "vcmpequ. %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_vcmpgts_p" [(set (reg:CC 74) ! (unspec:CC [(gt:CC (match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v"))] UNSPEC_PREDICATE)) ! (set (match_operand:VI 0 "register_operand" "=v") ! (gt:VI (match_dup 1) ! (match_dup 2)))] ! "VECTOR_UNIT_ALTIVEC_P (mode)" "vcmpgts. %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_vcmpgtu_p" [(set (reg:CC 74) ! (unspec:CC [(gtu:CC (match_operand:VI 1 "register_operand" "v") ! (match_operand:VI 2 "register_operand" "v"))] UNSPEC_PREDICATE)) ! (set (match_operand:VI 0 "register_operand" "=v") ! (gtu:VI (match_dup 1) ! (match_dup 2)))] ! "VECTOR_UNIT_ALTIVEC_P (mode)" "vcmpgtu. %0,%1,%2" [(set_attr "type" "veccmp")]) --- 2082,2190 ---- "vsldoi %0,%1,%2,%3" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vupkhs" ! [(set (match_operand:VP 0 "register_operand" "=v") ! (unspec:VP [(match_operand: 1 "register_operand" "v")] ! UNSPEC_VUNPACK_HI_SIGN))] ! "" ! { ! if (VECTOR_ELT_ORDER_BIG) ! return "vupkhs %0,%1"; ! else ! return "vupkls %0,%1"; ! } [(set_attr "type" "vecperm")]) ! (define_insn "*altivec_vupkhs_direct" ! [(set (match_operand:VP 0 "register_operand" "=v") ! (unspec:VP [(match_operand: 1 "register_operand" "v")] ! UNSPEC_VUNPACK_HI_SIGN_DIRECT))] ! "" ! "vupkhs %0,%1" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vupkls" ! [(set (match_operand:VP 0 "register_operand" "=v") ! (unspec:VP [(match_operand: 1 "register_operand" "v")] ! UNSPEC_VUNPACK_LO_SIGN))] ! "" ! { ! if (VECTOR_ELT_ORDER_BIG) ! return "vupkls %0,%1"; ! else ! return "vupkhs %0,%1"; ! } [(set_attr "type" "vecperm")]) ! (define_insn "*altivec_vupkls_direct" ! [(set (match_operand:VP 0 "register_operand" "=v") ! (unspec:VP [(match_operand: 1 "register_operand" "v")] ! UNSPEC_VUNPACK_LO_SIGN_DIRECT))] ! "" ! "vupkls %0,%1" [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vupkhpx" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] ! UNSPEC_VUPKHPX))] "TARGET_ALTIVEC" ! { ! if (VECTOR_ELT_ORDER_BIG) ! return "vupkhpx %0,%1"; ! else ! return "vupklpx %0,%1"; ! } [(set_attr "type" "vecperm")]) ! (define_insn "altivec_vupklpx" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] ! UNSPEC_VUPKLPX))] "TARGET_ALTIVEC" ! { ! if (VECTOR_ELT_ORDER_BIG) ! return "vupklpx %0,%1"; ! else ! return "vupkhpx %0,%1"; ! } [(set_attr "type" "vecperm")]) ;; Compare vectors producing a vector result and a predicate, setting CR6 to ;; indicate a combined status (define_insn "*altivec_vcmpequ_p" [(set (reg:CC 74) ! (unspec:CC [(eq:CC (match_operand:VI2 1 "register_operand" "v") ! (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) ! (set (match_operand:VI2 0 "register_operand" "=v") ! (eq:VI2 (match_dup 1) ! (match_dup 2)))] ! "" "vcmpequ. %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_vcmpgts_p" [(set (reg:CC 74) ! (unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v") ! (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) ! (set (match_operand:VI2 0 "register_operand" "=v") ! (gt:VI2 (match_dup 1) ! (match_dup 2)))] ! "" "vcmpgts. %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_vcmpgtu_p" [(set (reg:CC 74) ! (unspec:CC [(gtu:CC (match_operand:VI2 1 "register_operand" "v") ! (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) ! (set (match_operand:VI2 0 "register_operand" "=v") ! (gtu:VI2 (match_dup 1) ! (match_dup 2)))] ! "" "vcmpgtu. %0,%1,%2" [(set_attr "type" "veccmp")]) *************** *** 1710,1716 **** ;; Parallel some of the LVE* and STV*'s with unspecs because some have ;; identical rtl but different instructions-- and gcc gets confused. ! (define_insn "altivec_lvex" [(parallel [(set (match_operand:VI 0 "register_operand" "=v") (match_operand:VI 1 "memory_operand" "Z")) --- 2336,2356 ---- ;; Parallel some of the LVE* and STV*'s with unspecs because some have ;; identical rtl but different instructions-- and gcc gets confused. ! (define_expand "altivec_lvex" ! [(parallel ! [(set (match_operand:VI 0 "register_operand" "=v") ! (match_operand:VI 1 "memory_operand" "Z")) ! (unspec [(const_int 0)] UNSPEC_LVE)])] ! "TARGET_ALTIVEC" ! { ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! { ! altivec_expand_lvx_be (operands[0], operands[1], mode, UNSPEC_LVE); ! DONE; ! } ! }) ! ! (define_insn "*altivec_lvex_internal" [(parallel [(set (match_operand:VI 0 "register_operand" "=v") (match_operand:VI 1 "memory_operand" "Z")) *************** *** 1728,1743 **** "lvewx %0,%y1" [(set_attr "type" "vecload")]) ! (define_insn "altivec_lvxl" [(parallel ! [(set (match_operand:V4SI 0 "register_operand" "=v") ! (match_operand:V4SI 1 "memory_operand" "Z")) (unspec [(const_int 0)] UNSPEC_SET_VSCR)])] "TARGET_ALTIVEC" ! "lvxl %0,%y1" [(set_attr "type" "vecload")]) ! (define_insn "altivec_lvx_" [(parallel [(set (match_operand:VM2 0 "register_operand" "=v") (match_operand:VM2 1 "memory_operand" "Z")) --- 2368,2411 ---- "lvewx %0,%y1" [(set_attr "type" "vecload")]) ! (define_expand "altivec_lvxl_" [(parallel ! [(set (match_operand:VM2 0 "register_operand" "=v") ! (match_operand:VM2 1 "memory_operand" "Z")) (unspec [(const_int 0)] UNSPEC_SET_VSCR)])] "TARGET_ALTIVEC" ! { ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! { ! altivec_expand_lvx_be (operands[0], operands[1], mode, UNSPEC_SET_VSCR); ! DONE; ! } ! }) ! ! (define_insn "*altivec_lvxl__internal" ! [(parallel ! [(set (match_operand:VM2 0 "register_operand" "=v") ! (match_operand:VM2 1 "memory_operand" "Z")) ! (unspec [(const_int 0)] UNSPEC_SET_VSCR)])] ! "TARGET_ALTIVEC" ! "lvx %0,%y1" [(set_attr "type" "vecload")]) ! (define_expand "altivec_lvx_" ! [(parallel ! [(set (match_operand:VM2 0 "register_operand" "=v") ! (match_operand:VM2 1 "memory_operand" "Z")) ! (unspec [(const_int 0)] UNSPEC_LVX)])] ! "TARGET_ALTIVEC" ! { ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! { ! altivec_expand_lvx_be (operands[0], operands[1], mode, UNSPEC_LVX); ! DONE; ! } ! }) ! ! (define_insn "*altivec_lvx__internal" [(parallel [(set (match_operand:VM2 0 "register_operand" "=v") (match_operand:VM2 1 "memory_operand" "Z")) *************** *** 1746,1752 **** "lvx %0,%y1" [(set_attr "type" "vecload")]) ! (define_insn "altivec_stvx_" [(parallel [(set (match_operand:VM2 0 "memory_operand" "=Z") (match_operand:VM2 1 "register_operand" "v")) --- 2414,2434 ---- "lvx %0,%y1" [(set_attr "type" "vecload")]) ! (define_expand "altivec_stvx_" ! [(parallel ! [(set (match_operand:VM2 0 "memory_operand" "=Z") ! (match_operand:VM2 1 "register_operand" "v")) ! (unspec [(const_int 0)] UNSPEC_STVX)])] ! "TARGET_ALTIVEC" ! { ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! { ! altivec_expand_stvx_be (operands[0], operands[1], mode, UNSPEC_STVX); ! DONE; ! } ! }) ! ! (define_insn "*altivec_stvx__internal" [(parallel [(set (match_operand:VM2 0 "memory_operand" "=Z") (match_operand:VM2 1 "register_operand" "v")) *************** *** 1755,1770 **** "stvx %1,%y0" [(set_attr "type" "vecstore")]) ! (define_insn "altivec_stvxl" [(parallel ! [(set (match_operand:V4SI 0 "memory_operand" "=Z") ! (match_operand:V4SI 1 "register_operand" "v")) (unspec [(const_int 0)] UNSPEC_STVXL)])] "TARGET_ALTIVEC" "stvxl %1,%y0" [(set_attr "type" "vecstore")]) ! (define_insn "altivec_stvex" [(set (match_operand: 0 "memory_operand" "=Z") (unspec: [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))] "TARGET_ALTIVEC" --- 2437,2478 ---- "stvx %1,%y0" [(set_attr "type" "vecstore")]) ! (define_expand "altivec_stvxl_" [(parallel ! [(set (match_operand:VM2 0 "memory_operand" "=Z") ! (match_operand:VM2 1 "register_operand" "v")) ! (unspec [(const_int 0)] UNSPEC_STVXL)])] ! "TARGET_ALTIVEC" ! { ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! { ! altivec_expand_stvx_be (operands[0], operands[1], mode, UNSPEC_STVXL); ! DONE; ! } ! }) ! ! (define_insn "*altivec_stvxl__internal" ! [(parallel ! [(set (match_operand:VM2 0 "memory_operand" "=Z") ! (match_operand:VM2 1 "register_operand" "v")) (unspec [(const_int 0)] UNSPEC_STVXL)])] "TARGET_ALTIVEC" "stvxl %1,%y0" [(set_attr "type" "vecstore")]) ! (define_expand "altivec_stvex" ! [(set (match_operand: 0 "memory_operand" "=Z") ! (unspec: [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))] ! "TARGET_ALTIVEC" ! { ! if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) ! { ! altivec_expand_stvex_be (operands[0], operands[1], mode, UNSPEC_STVE); ! DONE; ! } ! }) ! ! (define_insn "*altivec_stvex_internal" [(set (match_operand: 0 "memory_operand" "=Z") (unspec: [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))] "TARGET_ALTIVEC" *************** *** 1779,1798 **** [(set_attr "type" "vecstore")]) ;; Generate ! ;; vspltis? SCRATCH0,0 ;; vsubu?m SCRATCH2,SCRATCH1,%1 ;; vmaxs? %0,%1,SCRATCH2" (define_expand "abs2" ! [(set (match_dup 2) (vec_duplicate:VI (const_int 0))) ! (set (match_dup 3) ! (minus:VI (match_dup 2) ! (match_operand:VI 1 "register_operand" "v"))) ! (set (match_operand:VI 0 "register_operand" "=v") ! (smax:VI (match_dup 1) (match_dup 3)))] ! "TARGET_ALTIVEC" { ! operands[2] = gen_reg_rtx (GET_MODE (operands[0])); ! operands[3] = gen_reg_rtx (GET_MODE (operands[0])); }) ;; Generate --- 2487,2514 ---- [(set_attr "type" "vecstore")]) ;; Generate ! ;; xxlxor/vxor SCRATCH0,SCRATCH0,SCRATCH0 ;; vsubu?m SCRATCH2,SCRATCH1,%1 ;; vmaxs? %0,%1,SCRATCH2" (define_expand "abs2" ! [(set (match_dup 2) (match_dup 3)) ! (set (match_dup 4) ! (minus:VI2 (match_dup 2) ! (match_operand:VI2 1 "register_operand" "v"))) ! (set (match_operand:VI2 0 "register_operand" "=v") ! (smax:VI2 (match_dup 1) (match_dup 4)))] ! "" { ! int i, n_elt = GET_MODE_NUNITS (mode); ! rtvec v = rtvec_alloc (n_elt); ! ! /* Create an all 0 constant. */ ! for (i = 0; i < n_elt; ++i) ! RTVEC_ELT (v, i) = const0_rtx; ! ! operands[2] = gen_reg_rtx (mode); ! operands[3] = gen_rtx_CONST_VECTOR (mode, v); ! operands[4] = gen_reg_rtx (mode); }) ;; Generate *************** *** 1844,1850 **** emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); emit_insn (gen_altivec_vsum4ss (vtmp1, operands[1], vzero)); ! emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero)); DONE; }) --- 2560,2566 ---- emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); emit_insn (gen_altivec_vsum4ss (vtmp1, operands[1], vzero)); ! emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero)); DONE; }) *************** *** 1860,1866 **** emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero)); ! emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero)); DONE; }) --- 2576,2582 ---- emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero)); ! emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero)); DONE; }) *************** *** 1950,1998 **** DONE; }") ! (define_expand "vec_unpacks_hi_v16qi" ! [(set (match_operand:V8HI 0 "register_operand" "=v") ! (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] ! UNSPEC_VUPKHSB))] ! "TARGET_ALTIVEC" ! " ! { ! emit_insn (gen_altivec_vupkhsb (operands[0], operands[1])); ! DONE; ! }") ! ! (define_expand "vec_unpacks_hi_v8hi" ! [(set (match_operand:V4SI 0 "register_operand" "=v") ! (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] ! UNSPEC_VUPKHSH))] ! "TARGET_ALTIVEC" ! " ! { ! emit_insn (gen_altivec_vupkhsh (operands[0], operands[1])); ! DONE; ! }") ! ! (define_expand "vec_unpacks_lo_v16qi" ! [(set (match_operand:V8HI 0 "register_operand" "=v") ! (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] ! UNSPEC_VUPKLSB))] ! "TARGET_ALTIVEC" ! " ! { ! emit_insn (gen_altivec_vupklsb (operands[0], operands[1])); ! DONE; ! }") ! (define_expand "vec_unpacks_lo_v8hi" ! [(set (match_operand:V4SI 0 "register_operand" "=v") ! (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] ! UNSPEC_VUPKLSH))] ! "TARGET_ALTIVEC" ! " ! { ! emit_insn (gen_altivec_vupklsh (operands[0], operands[1])); ! DONE; ! }") (define_insn "vperm_v8hiv4si" [(set (match_operand:V4SI 0 "register_operand" "=v") --- 2666,2684 ---- DONE; }") ! (define_expand "vec_unpacks_hi_" ! [(set (match_operand:VP 0 "register_operand" "=v") ! (unspec:VP [(match_operand: 1 "register_operand" "v")] ! UNSPEC_VUNPACK_HI_SIGN_DIRECT))] ! "" ! "") ! (define_expand "vec_unpacks_lo_" ! [(set (match_operand:VP 0 "register_operand" "=v") ! (unspec:VP [(match_operand: 1 "register_operand" "v")] ! UNSPEC_VUNPACK_LO_SIGN_DIRECT))] ! "" ! "") (define_insn "vperm_v8hiv4si" [(set (match_operand:V4SI 0 "register_operand" "=v") *************** *** 2025,2049 **** rtx vzero = gen_reg_rtx (V8HImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); emit_insn (gen_altivec_vspltish (vzero, const0_rtx)); ! RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 0); ! RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1); ! RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 2); ! RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3); ! RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 4); ! RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5); ! RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 6); ! RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7); emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask)); --- 2711,2736 ---- rtx vzero = gen_reg_rtx (V8HImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); + bool be = BYTES_BIG_ENDIAN; emit_insn (gen_altivec_vspltish (vzero, const0_rtx)); ! RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 7); ! RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 0 : 16); ! RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 16 : 6); ! RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 1 : 16); ! RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 5); ! RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 2 : 16); ! RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 16 : 4); ! RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 3 : 16); ! RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 3); ! RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 4 : 16); ! RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 16 : 2); ! RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 5 : 16); ! RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 1); ! RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 6 : 16); ! RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 16 : 0); ! RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 7 : 16); emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask)); *************** *** 2060,2084 **** rtx vzero = gen_reg_rtx (V4SImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); ! RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17); ! RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 0); ! RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1); ! RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17); ! RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 2); ! RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3); ! RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17); ! RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 4); ! RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5); ! RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17); ! RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 6); ! RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7); emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask)); --- 2747,2772 ---- rtx vzero = gen_reg_rtx (V4SImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); + bool be = BYTES_BIG_ENDIAN; emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); ! RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 7); ! RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 17 : 6); ! RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 0 : 17); ! RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 1 : 16); ! RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 5); ! RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 17 : 4); ! RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 2 : 17); ! RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 3 : 16); ! RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 3); ! RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 17 : 2); ! RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 4 : 17); ! RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 5 : 16); ! RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 1); ! RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 17 : 0); ! RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 6 : 17); ! RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 7 : 16); emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask)); *************** *** 2095,2119 **** rtx vzero = gen_reg_rtx (V8HImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); emit_insn (gen_altivec_vspltish (vzero, const0_rtx)); ! RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 8); ! RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9); ! RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10); ! RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11); ! RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 12); ! RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13); ! RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 14); ! RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15); emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask)); --- 2783,2808 ---- rtx vzero = gen_reg_rtx (V8HImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); + bool be = BYTES_BIG_ENDIAN; emit_insn (gen_altivec_vspltish (vzero, const0_rtx)); ! RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 15); ! RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 8 : 16); ! RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 16 : 14); ! RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 9 : 16); ! RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 13); ! RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 10 : 16); ! RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 16 : 12); ! RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 11 : 16); ! RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 11); ! RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 12 : 16); ! RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 16 : 10); ! RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 13 : 16); ! RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 9); ! RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 14 : 16); ! RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 16 : 8); ! RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 15 : 16); emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask)); *************** *** 2130,2154 **** rtx vzero = gen_reg_rtx (V4SImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); ! RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17); ! RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 8); ! RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9); ! RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17); ! RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10); ! RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11); ! RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17); ! RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 12); ! RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13); ! RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16); ! RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17); ! RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 14); ! RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15); emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask)); --- 2819,2844 ---- rtx vzero = gen_reg_rtx (V4SImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); + bool be = BYTES_BIG_ENDIAN; emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); ! RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 15); ! RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 17 : 14); ! RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 8 : 17); ! RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 9 : 16); ! RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 13); ! RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 17 : 12); ! RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 10 : 17); ! RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 11 : 16); ! RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 11); ! RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 17 : 10); ! RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 12 : 17); ! RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 13 : 16); ! RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 9); ! RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 17 : 8); ! RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 14 : 17); ! RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 15 : 16); emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask)); *************** *** 2166,2174 **** rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); ! emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2])); ! emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghh (operands[0], ve, vo)); DONE; }") --- 2856,2873 ---- rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); ! if (BYTES_BIG_ENDIAN) ! { ! emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo)); ! } ! else ! { ! emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve)); ! } DONE; }") *************** *** 2183,2191 **** rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); ! emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2])); ! emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrglh (operands[0], ve, vo)); DONE; }") --- 2882,2899 ---- rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); ! if (BYTES_BIG_ENDIAN) ! { ! emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo)); ! } ! else ! { ! emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve)); ! } DONE; }") *************** *** 2200,2208 **** rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); ! emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2])); ! emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghh (operands[0], ve, vo)); DONE; }") --- 2908,2925 ---- rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); ! if (BYTES_BIG_ENDIAN) ! { ! emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo)); ! } ! else ! { ! emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve)); ! } DONE; }") *************** *** 2217,2225 **** rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); ! emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2])); ! emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrglh (operands[0], ve, vo)); DONE; }") --- 2934,2951 ---- rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); ! if (BYTES_BIG_ENDIAN) ! { ! emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo)); ! } ! else ! { ! emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve)); ! } DONE; }") *************** *** 2234,2242 **** rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); ! emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2])); ! emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghw (operands[0], ve, vo)); DONE; }") --- 2960,2977 ---- rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); ! if (BYTES_BIG_ENDIAN) ! { ! emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghw_direct (operands[0], ve, vo)); ! } ! else ! { ! emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve)); ! } DONE; }") *************** *** 2251,2259 **** rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); ! emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2])); ! emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrglw (operands[0], ve, vo)); DONE; }") --- 2986,3003 ---- rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); ! if (BYTES_BIG_ENDIAN) ! { ! emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrglw_direct (operands[0], ve, vo)); ! } ! else ! { ! emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve)); ! } DONE; }") *************** *** 2268,2276 **** rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); ! emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2])); ! emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghw (operands[0], ve, vo)); DONE; }") --- 3012,3029 ---- rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); ! if (BYTES_BIG_ENDIAN) ! { ! emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghw_direct (operands[0], ve, vo)); ! } ! else ! { ! emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve)); ! } DONE; }") *************** *** 2285,2319 **** rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); ! emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2])); ! emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrglw (operands[0], ve, vo)); DONE; }") ! (define_expand "vec_pack_trunc_v8hi" ! [(set (match_operand:V16QI 0 "register_operand" "=v") ! (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") ! (match_operand:V8HI 2 "register_operand" "v")] ! UNSPEC_VPKUHUM))] ! "TARGET_ALTIVEC" ! " ! { ! emit_insn (gen_altivec_vpkuhum (operands[0], operands[1], operands[2])); ! DONE; ! }") ! ! (define_expand "vec_pack_trunc_v4si" ! [(set (match_operand:V8HI 0 "register_operand" "=v") ! (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") ! (match_operand:V4SI 2 "register_operand" "v")] ! UNSPEC_VPKUWUM))] ! "TARGET_ALTIVEC" ! " ! { ! emit_insn (gen_altivec_vpkuwum (operands[0], operands[1], operands[2])); ! DONE; ! }") (define_expand "altivec_negv4sf2" [(use (match_operand:V4SF 0 "register_operand" "")) --- 3038,3065 ---- rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); ! if (BYTES_BIG_ENDIAN) ! { ! emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrglw_direct (operands[0], ve, vo)); ! } ! else ! { ! emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2])); ! emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2])); ! emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve)); ! } DONE; }") ! (define_expand "vec_pack_trunc_" ! [(set (match_operand: 0 "register_operand" "=v") ! (unspec: [(match_operand:VP 1 "register_operand" "v") ! (match_operand:VP 2 "register_operand" "v")] ! UNSPEC_VPACK_UNS_UNS_MOD))] ! "" ! "") (define_expand "altivec_negv4sf2" [(use (match_operand:V4SF 0 "register_operand" "")) *************** *** 2460,2462 **** --- 3206,3448 ---- emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx)); DONE; }") + + + ;; Power8 vector instructions encoded as Altivec instructions + + ;; Vector count leading zeros + (define_insn "*p8v_clz2" + [(set (match_operand:VI2 0 "register_operand" "=v") + (clz:VI2 (match_operand:VI2 1 "register_operand" "v")))] + "TARGET_P8_VECTOR" + "vclz %0,%1" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + ;; Vector population count + (define_insn "*p8v_popcount2" + [(set (match_operand:VI2 0 "register_operand" "=v") + (popcount:VI2 (match_operand:VI2 1 "register_operand" "v")))] + "TARGET_P8_VECTOR" + "vpopcnt %0,%1" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + ;; Vector Gather Bits by Bytes by Doubleword + (define_insn "p8v_vgbbd" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] + UNSPEC_VGBBD))] + "TARGET_P8_VECTOR" + "vgbbd %0,%1" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + + ;; 128-bit binary integer arithmetic + ;; We have a special container type (V1TImode) to allow operations using the + ;; ISA 2.07 128-bit binary support to target the VMX/altivec registers without + ;; having to worry about the register allocator deciding GPRs are better. + + (define_insn "altivec_vadduqm" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (plus:V1TI (match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v")))] + "TARGET_VADDUQM" + "vadduqm %0,%1,%2" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + (define_insn "altivec_vaddcuq" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v")] + UNSPEC_VADDCUQ))] + "TARGET_VADDUQM" + "vaddcuq %0,%1,%2" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + (define_insn "altivec_vsubuqm" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (minus:V1TI (match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v")))] + "TARGET_VADDUQM" + "vsubuqm %0,%1,%2" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + (define_insn "altivec_vsubcuq" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v")] + UNSPEC_VSUBCUQ))] + "TARGET_VADDUQM" + "vsubcuq %0,%1,%2" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + (define_insn "altivec_vaddeuqm" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:V1TI 3 "register_operand" "v")] + UNSPEC_VADDEUQM))] + "TARGET_VADDUQM" + "vaddeuqm %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + (define_insn "altivec_vaddecuq" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:V1TI 3 "register_operand" "v")] + UNSPEC_VADDECUQ))] + "TARGET_VADDUQM" + "vaddecuq %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + (define_insn "altivec_vsubeuqm" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:V1TI 3 "register_operand" "v")] + UNSPEC_VSUBEUQM))] + "TARGET_VADDUQM" + "vsubeuqm %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + (define_insn "altivec_vsubecuq" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:V1TI 3 "register_operand" "v")] + UNSPEC_VSUBECUQ))] + "TARGET_VADDUQM" + "vsubecuq %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + ;; We use V2DI as the output type to simplify converting the permute + ;; bits into an integer + (define_insn "altivec_vbpermq" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] + UNSPEC_VBPERMQ))] + "TARGET_P8_VECTOR" + "vbpermq %0,%1,%2" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + ;; Decimal Integer operations + (define_int_iterator UNSPEC_BCD_ADD_SUB [UNSPEC_BCDADD UNSPEC_BCDSUB]) + + (define_int_attr bcd_add_sub [(UNSPEC_BCDADD "add") + (UNSPEC_BCDSUB "sub")]) + + (define_code_iterator BCD_TEST [eq lt gt unordered]) + + (define_insn "bcd" + [(set (match_operand:V1TI 0 "register_operand" "") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "") + (match_operand:V1TI 2 "register_operand" "") + (match_operand:QI 3 "const_0_to_1_operand" "")] + UNSPEC_BCD_ADD_SUB)) + (clobber (reg:CCFP 74))] + "TARGET_P8_VECTOR" + "bcd. %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + ;; Use a floating point type (V2DFmode) for the compare to set CR6 so that we + ;; can use the unordered test for BCD nans and add/subtracts that overflow. An + ;; UNORDERED test on an integer type (like V1TImode) is not defined. The type + ;; probably should be one that can go in the VMX (Altivec) registers, so we + ;; can't use DDmode or DFmode. + (define_insn "*bcd_test" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:QI 3 "const_0_to_1_operand" "i")] + UNSPEC_BCD_ADD_SUB) + (match_operand:V2DF 4 "zero_constant" "j"))) + (clobber (match_scratch:V1TI 0 "=v"))] + "TARGET_P8_VECTOR" + "bcd. %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + (define_insn "*bcd_test2" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:QI 3 "const_0_to_1_operand" "i")] + UNSPEC_BCD_ADD_SUB)) + (set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_BCD_ADD_SUB) + (match_operand:V2DF 4 "zero_constant" "j")))] + "TARGET_P8_VECTOR" + "bcd. %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + (define_expand "bcd_" + [(parallel [(set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "") + (match_operand:V1TI 2 "register_operand" "") + (match_operand:QI 3 "const_0_to_1_operand" "")] + UNSPEC_BCD_ADD_SUB) + (match_dup 4))) + (clobber (match_scratch:V1TI 5 ""))]) + (set (match_operand:SI 0 "register_operand" "") + (BCD_TEST:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P8_VECTOR" + { + operands[4] = CONST0_RTX (V2DFmode); + }) + + ;; Peephole2 pattern to combine a bcdadd/bcdsub that calculates the value and + ;; the bcdadd/bcdsub that tests the value. The combiner won't work since + ;; CR6 is a hard coded register. Unfortunately, all of the Altivec predicate + ;; support is hard coded to use the fixed register CR6 instead of creating + ;; a register class for CR6. + + (define_peephole2 + [(parallel [(set (match_operand:V1TI 0 "register_operand" "") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "") + (match_operand:V1TI 2 "register_operand" "") + (match_operand:QI 3 "const_0_to_1_operand" "")] + UNSPEC_BCD_ADD_SUB)) + (clobber (reg:CCFP 74))]) + (parallel [(set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_BCD_ADD_SUB) + (match_operand:V2DF 4 "zero_constant" ""))) + (clobber (match_operand:V1TI 5 "register_operand" ""))])] + "TARGET_P8_VECTOR" + [(parallel [(set (match_dup 0) + (unspec:V1TI [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_BCD_ADD_SUB)) + (set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_BCD_ADD_SUB) + (match_dup 4)))])]) diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/constraints.md gcc-4.8.3/gcc/config/rs6000/constraints.md *** gcc-4.8.2/gcc/config/rs6000/constraints.md Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/rs6000/constraints.md Fri Apr 4 13:39:27 2014 *************** *** 52,72 **** "@internal") ;; Use w as a prefix to add VSX modes ! ;; vector double (V2DF) (define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]" ! "@internal") - ;; vector float (V4SF) (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]" ! "@internal") - ;; scalar double (DF) (define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]" ! "@internal") ! ;; any VSX register ! (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" ! "@internal") ;; Altivec style load/store that ignores the bottom bits of the address (define_memory_constraint "wZ" --- 52,112 ---- "@internal") ;; Use w as a prefix to add VSX modes ! ;; any VSX register ! (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" ! "Any VSX register if the -mvsx option was used or NO_REGS.") ! (define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]" ! "VSX vector register to hold vector double data or NO_REGS.") (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]" ! "VSX vector register to hold vector float data or NO_REGS.") ! ! (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" ! "If -mmfpgpr was used, a floating point register or NO_REGS.") ! ! (define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" ! "Floating point register if the LFIWAX instruction is enabled or NO_REGS.") ! ! (define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]" ! "VSX register if direct move instructions are enabled, or NO_REGS.") ! ! ;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use ! ;; direct move directly, and movsf can't to move between the register sets. ! ;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode ! (define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).") ! ! (define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]" ! "General purpose register if 64-bit instructions are enabled or NO_REGS.") (define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]" ! "VSX vector register to hold scalar double values or NO_REGS.") ! (define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]" ! "VSX vector register to hold 128 bit integer or NO_REGS.") ! ! (define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]" ! "Altivec register to use for float/32-bit int loads/stores or NO_REGS.") ! ! (define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]" ! "Altivec register to use for double loads/stores or NO_REGS.") ! ! (define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]" ! "FP or VSX register to perform float operations under -mvsx or NO_REGS.") ! ! (define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]" ! "Floating point register if the STFIWX instruction is enabled or NO_REGS.") ! ! (define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]" ! "VSX vector register to hold scalar float values or NO_REGS.") ! ! (define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]" ! "Floating point register if the LFIWZX instruction is enabled or NO_REGS.") ! ! ;; Lq/stq validates the address for load/store quad ! (define_memory_constraint "wQ" ! "Memory operand suitable for the load/store quad instructions" ! (match_operand 0 "quad_memory_operand")) ;; Altivec style load/store that ignores the bottom bits of the address (define_memory_constraint "wZ" diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/crypto.md gcc-4.8.3/gcc/config/rs6000/crypto.md *** gcc-4.8.2/gcc/config/rs6000/crypto.md Thu Jan 1 00:00:00 1970 --- gcc-4.8.3/gcc/config/rs6000/crypto.md Fri Apr 4 13:39:27 2014 *************** *** 0 **** --- 1,101 ---- + ;; Cryptographic instructions added in ISA 2.07 + ;; Copyright (C) 2012-2013 Free Software Foundation, Inc. + ;; Contributed by Michael Meissner (meissner@linux.vnet.ibm.com) + + ;; This file is part of GCC. + + ;; GCC is free software; you can redistribute it and/or modify it + ;; under the terms of the GNU General Public License as published + ;; by the Free Software Foundation; either version 3, or (at your + ;; option) any later version. + + ;; GCC is distributed in the hope that it will be useful, but WITHOUT + ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + ;; License for more details. + + ;; You should have received a copy of the GNU General Public License + ;; along with GCC; see the file COPYING3. If not see + ;; . + + (define_c_enum "unspec" + [UNSPEC_VCIPHER + UNSPEC_VNCIPHER + UNSPEC_VCIPHERLAST + UNSPEC_VNCIPHERLAST + UNSPEC_VSBOX + UNSPEC_VSHASIGMA + UNSPEC_VPERMXOR + UNSPEC_VPMSUM]) + + ;; Iterator for VPMSUM/VPERMXOR + (define_mode_iterator CR_mode [V16QI V8HI V4SI V2DI]) + + (define_mode_attr CR_char [(V16QI "b") + (V8HI "h") + (V4SI "w") + (V2DI "d")]) + + ;; Iterator for VSHASIGMAD/VSHASIGMAW + (define_mode_iterator CR_hash [V4SI V2DI]) + + ;; Iterator for the other crypto functions + (define_int_iterator CR_code [UNSPEC_VCIPHER + UNSPEC_VNCIPHER + UNSPEC_VCIPHERLAST + UNSPEC_VNCIPHERLAST]) + + (define_int_attr CR_insn [(UNSPEC_VCIPHER "vcipher") + (UNSPEC_VNCIPHER "vncipher") + (UNSPEC_VCIPHERLAST "vcipherlast") + (UNSPEC_VNCIPHERLAST "vncipherlast")]) + + ;; 2 operand crypto instructions + (define_insn "crypto_" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v") + (match_operand:V2DI 2 "register_operand" "v")] + CR_code))] + "TARGET_CRYPTO" + " %0,%1,%2" + [(set_attr "type" "crypto")]) + + (define_insn "crypto_vpmsum" + [(set (match_operand:CR_mode 0 "register_operand" "=v") + (unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v") + (match_operand:CR_mode 2 "register_operand" "v")] + UNSPEC_VPMSUM))] + "TARGET_CRYPTO" + "vpmsum %0,%1,%2" + [(set_attr "type" "crypto")]) + + ;; 3 operand crypto instructions + (define_insn "crypto_vpermxor_" + [(set (match_operand:CR_mode 0 "register_operand" "=v") + (unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v") + (match_operand:CR_mode 2 "register_operand" "v") + (match_operand:CR_mode 3 "register_operand" "v")] + UNSPEC_VPERMXOR))] + "TARGET_CRYPTO" + "vpermxor %0,%1,%2,%3" + [(set_attr "type" "crypto")]) + + ;; 1 operand crypto instruction + (define_insn "crypto_vsbox" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")] + UNSPEC_VSBOX))] + "TARGET_CRYPTO" + "vsbox %0,%1" + [(set_attr "type" "crypto")]) + + ;; Hash crypto instructions + (define_insn "crypto_vshasigma" + [(set (match_operand:CR_hash 0 "register_operand" "=v") + (unspec:CR_hash [(match_operand:CR_hash 1 "register_operand" "v") + (match_operand:SI 2 "const_0_to_1_operand" "n") + (match_operand:SI 3 "const_0_to_15_operand" "n")] + UNSPEC_VSHASIGMA))] + "TARGET_CRYPTO" + "vshasigma %0,%1,%2,%3" + [(set_attr "type" "crypto")]) diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/darwin.h gcc-4.8.3/gcc/config/rs6000/darwin.h *** gcc-4.8.2/gcc/config/rs6000/darwin.h Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/rs6000/darwin.h Fri Apr 4 13:45:28 2014 *************** extern int darwin_emit_branch_islands; *** 205,211 **** "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ "vrsave", "vscr", \ "spe_acc", "spefscr", \ ! "sfp" \ } /* This outputs NAME to FILE. */ --- 205,212 ---- "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ "vrsave", "vscr", \ "spe_acc", "spefscr", \ ! "sfp", \ ! "tfhar", "tfiar", "texasr" \ } /* This outputs NAME to FILE. */ diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/dfp.md gcc-4.8.3/gcc/config/rs6000/dfp.md *** gcc-4.8.2/gcc/config/rs6000/dfp.md Mon Aug 19 17:55:50 2013 --- gcc-4.8.3/gcc/config/rs6000/dfp.md Wed Apr 30 20:04:12 2014 *************** *** 29,105 **** ]) - (define_expand "movsd" - [(set (match_operand:SD 0 "nonimmediate_operand" "") - (match_operand:SD 1 "any_operand" ""))] - "TARGET_HARD_FLOAT && TARGET_FPRS" - "{ rs6000_emit_move (operands[0], operands[1], SDmode); DONE; }") - - (define_split - [(set (match_operand:SD 0 "gpc_reg_operand" "") - (match_operand:SD 1 "const_double_operand" ""))] - "reload_completed - && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) - || (GET_CODE (operands[0]) == SUBREG - && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) <= 31))" - [(set (match_dup 2) (match_dup 3))] - " - { - long l; - REAL_VALUE_TYPE rv; - - REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); - REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l); - - if (! TARGET_POWERPC64) - operands[2] = operand_subword (operands[0], 0, 0, SDmode); - else - operands[2] = gen_lowpart (SImode, operands[0]); - - operands[3] = gen_int_mode (l, SImode); - }") - - (define_insn "movsd_hardfloat" - [(set (match_operand:SD 0 "nonimmediate_operand" "=r,r,m,f,*c*l,!r,*h,!r,!r") - (match_operand:SD 1 "input_operand" "r,m,r,f,r,h,0,G,Fn"))] - "(gpc_reg_operand (operands[0], SDmode) - || gpc_reg_operand (operands[1], SDmode)) - && (TARGET_HARD_FLOAT && TARGET_FPRS)" - "@ - mr %0,%1 - lwz%U1%X1 %0,%1 - stw%U0%X0 %1,%0 - fmr %0,%1 - mt%0 %1 - mf%1 %0 - nop - # - #" - [(set_attr "type" "*,load,store,fp,mtjmpr,mfjmpr,*,*,*") - (set_attr "length" "4,4,4,4,4,4,4,4,8")]) - - (define_insn "movsd_softfloat" - [(set (match_operand:SD 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,r,*h") - (match_operand:SD 1 "input_operand" "r,r,h,m,r,I,L,R,G,Fn,0"))] - "(gpc_reg_operand (operands[0], SDmode) - || gpc_reg_operand (operands[1], SDmode)) - && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" - "@ - mr %0,%1 - mt%0 %1 - mf%1 %0 - lwz%U1%X1 %0,%1 - stw%U0%X0 %1,%0 - li %0,%1 - lis %0,%v1 - la %0,%a1 - # - # - nop" - [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*,*") - (set_attr "length" "4,4,4,4,4,4,4,4,4,8,4")]) - (define_insn "movsd_store" [(set (match_operand:DD 0 "nonimmediate_operand" "=m") (unspec:DD [(match_operand:SD 1 "input_operand" "d")] --- 29,34 ---- *************** *** 108,114 **** || gpc_reg_operand (operands[1], SDmode)) && TARGET_HARD_FLOAT && TARGET_FPRS" "stfd%U0%X0 %1,%0" ! [(set_attr "type" "fpstore") (set_attr "length" "4")]) (define_insn "movsd_load" --- 37,50 ---- || gpc_reg_operand (operands[1], SDmode)) && TARGET_HARD_FLOAT && TARGET_FPRS" "stfd%U0%X0 %1,%0" ! [(set (attr "type") ! (if_then_else ! (match_test "update_indexed_address_mem (operands[0], VOIDmode)") ! (const_string "fpstore_ux") ! (if_then_else ! (match_test "update_address_mem (operands[0], VOIDmode)") ! (const_string "fpstore_u") ! (const_string "fpstore")))) (set_attr "length" "4")]) (define_insn "movsd_load" *************** *** 119,125 **** || gpc_reg_operand (operands[1], DDmode)) && TARGET_HARD_FLOAT && TARGET_FPRS" "lfd%U1%X1 %0,%1" ! [(set_attr "type" "fpload") (set_attr "length" "4")]) ;; Hardware support for decimal floating point operations. --- 55,68 ---- || gpc_reg_operand (operands[1], DDmode)) && TARGET_HARD_FLOAT && TARGET_FPRS" "lfd%U1%X1 %0,%1" ! [(set (attr "type") ! (if_then_else ! (match_test "update_indexed_address_mem (operands[1], VOIDmode)") ! (const_string "fpload_ux") ! (if_then_else ! (match_test "update_address_mem (operands[1], VOIDmode)") ! (const_string "fpload_u") ! (const_string "fpload")))) (set_attr "length" "4")]) ;; Hardware support for decimal floating point operations. *************** *** 182,392 **** "fnabs %0,%1" [(set_attr "type" "fp")]) - (define_expand "movdd" - [(set (match_operand:DD 0 "nonimmediate_operand" "") - (match_operand:DD 1 "any_operand" ""))] - "" - "{ rs6000_emit_move (operands[0], operands[1], DDmode); DONE; }") - - (define_split - [(set (match_operand:DD 0 "gpc_reg_operand" "") - (match_operand:DD 1 "const_int_operand" ""))] - "! TARGET_POWERPC64 && reload_completed - && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) - || (GET_CODE (operands[0]) == SUBREG - && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) <= 31))" - [(set (match_dup 2) (match_dup 4)) - (set (match_dup 3) (match_dup 1))] - " - { - int endian = (WORDS_BIG_ENDIAN == 0); - HOST_WIDE_INT value = INTVAL (operands[1]); - - operands[2] = operand_subword (operands[0], endian, 0, DDmode); - operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode); - #if HOST_BITS_PER_WIDE_INT == 32 - operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; - #else - operands[4] = GEN_INT (value >> 32); - operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); - #endif - }") - - (define_split - [(set (match_operand:DD 0 "gpc_reg_operand" "") - (match_operand:DD 1 "const_double_operand" ""))] - "! TARGET_POWERPC64 && reload_completed - && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) - || (GET_CODE (operands[0]) == SUBREG - && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) <= 31))" - [(set (match_dup 2) (match_dup 4)) - (set (match_dup 3) (match_dup 5))] - " - { - int endian = (WORDS_BIG_ENDIAN == 0); - long l[2]; - REAL_VALUE_TYPE rv; - - REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); - REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l); - - operands[2] = operand_subword (operands[0], endian, 0, DDmode); - operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode); - operands[4] = gen_int_mode (l[endian], SImode); - operands[5] = gen_int_mode (l[1 - endian], SImode); - }") - - (define_split - [(set (match_operand:DD 0 "gpc_reg_operand" "") - (match_operand:DD 1 "const_double_operand" ""))] - "TARGET_POWERPC64 && reload_completed - && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) - || (GET_CODE (operands[0]) == SUBREG - && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) <= 31))" - [(set (match_dup 2) (match_dup 3))] - " - { - int endian = (WORDS_BIG_ENDIAN == 0); - long l[2]; - REAL_VALUE_TYPE rv; - #if HOST_BITS_PER_WIDE_INT >= 64 - HOST_WIDE_INT val; - #endif - - REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); - REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l); - - operands[2] = gen_lowpart (DImode, operands[0]); - /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ - #if HOST_BITS_PER_WIDE_INT >= 64 - val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 - | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); - - operands[3] = gen_int_mode (val, DImode); - #else - operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); - #endif - }") - - ;; Don't have reload use general registers to load a constant. First, - ;; it might not work if the output operand is the equivalent of - ;; a non-offsettable memref, but also it is less efficient than loading - ;; the constant into an FP register, since it will probably be used there. - ;; The "??" is a kludge until we can figure out a more reasonable way - ;; of handling these non-offsettable values. - (define_insn "*movdd_hardfloat32" - [(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r") - (match_operand:DD 1 "input_operand" "r,m,r,d,m,d,G,H,F"))] - "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS - && (gpc_reg_operand (operands[0], DDmode) - || gpc_reg_operand (operands[1], DDmode))" - "* - { - switch (which_alternative) - { - default: - gcc_unreachable (); - case 0: - case 1: - case 2: - return \"#\"; - case 3: - return \"fmr %0,%1\"; - case 4: - return \"lfd%U1%X1 %0,%1\"; - case 5: - return \"stfd%U0%X0 %1,%0\"; - case 6: - case 7: - case 8: - return \"#\"; - } - }" - [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*") - (set_attr "length" "8,16,16,4,4,4,8,12,16")]) - - (define_insn "*movdd_softfloat32" - [(set (match_operand:DD 0 "nonimmediate_operand" "=r,r,m,r,r,r") - (match_operand:DD 1 "input_operand" "r,m,r,G,H,F"))] - "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) - && (gpc_reg_operand (operands[0], DDmode) - || gpc_reg_operand (operands[1], DDmode))" - "#" - [(set_attr "type" "two,load,store,*,*,*") - (set_attr "length" "8,8,8,8,12,16")]) - - ; ld/std require word-aligned displacements -> 'Y' constraint. - ; List Y->r and r->Y before r->r for reload. - (define_insn "*movdd_hardfloat64_mfpgpr" - [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d") - (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))] - "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS - && (gpc_reg_operand (operands[0], DDmode) - || gpc_reg_operand (operands[1], DDmode))" - "@ - std%U0%X0 %1,%0 - ld%U1%X1 %0,%1 - mr %0,%1 - fmr %0,%1 - lfd%U1%X1 %0,%1 - stfd%U0%X0 %1,%0 - mt%0 %1 - mf%1 %0 - nop - # - # - # - mftgpr %0,%1 - mffgpr %0,%1" - [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr") - (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")]) - - ; ld/std require word-aligned displacements -> 'Y' constraint. - ; List Y->r and r->Y before r->r for reload. - (define_insn "*movdd_hardfloat64" - [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r") - (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))] - "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS - && (gpc_reg_operand (operands[0], DDmode) - || gpc_reg_operand (operands[1], DDmode))" - "@ - std%U0%X0 %1,%0 - ld%U1%X1 %0,%1 - mr %0,%1 - fmr %0,%1 - lfd%U1%X1 %0,%1 - stfd%U0%X0 %1,%0 - mt%0 %1 - mf%1 %0 - nop - # - # - #" - [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*") - (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) - - (define_insn "*movdd_softfloat64" - [(set (match_operand:DD 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") - (match_operand:DD 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] - "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) - && (gpc_reg_operand (operands[0], DDmode) - || gpc_reg_operand (operands[1], DDmode))" - "@ - ld%U1%X1 %0,%1 - std%U0%X0 %1,%0 - mr %0,%1 - mt%0 %1 - mf%1 %0 - # - # - # - nop" - [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*") - (set_attr "length" "4,4,4,4,4,8,12,16,4")]) - (define_expand "negtd2" [(set (match_operand:TD 0 "gpc_reg_operand" "") (neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))] --- 125,130 ---- *************** *** 410,448 **** "") (define_insn "*abstd2_fpr" ! [(set (match_operand:TD 0 "gpc_reg_operand" "=d") ! (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] "TARGET_HARD_FLOAT && TARGET_FPRS" ! "fabs %0,%1" ! [(set_attr "type" "fp")]) (define_insn "*nabstd2_fpr" ! [(set (match_operand:TD 0 "gpc_reg_operand" "=d") ! (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d"))))] ! "TARGET_HARD_FLOAT && TARGET_FPRS" ! "fnabs %0,%1" ! [(set_attr "type" "fp")]) ! ! (define_expand "movtd" ! [(set (match_operand:TD 0 "general_operand" "") ! (match_operand:TD 1 "any_operand" ""))] "TARGET_HARD_FLOAT && TARGET_FPRS" ! "{ rs6000_emit_move (operands[0], operands[1], TDmode); DONE; }") ! ! ; It's important to list the Y->r and r->Y moves before r->r because ! ; otherwise reload, given m->r, will try to pick r->r and reload it, ! ; which doesn't make progress. ! (define_insn_and_split "*movtd_internal" ! [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r") ! (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))] ! "TARGET_HARD_FLOAT && TARGET_FPRS ! && (gpc_reg_operand (operands[0], TDmode) ! || gpc_reg_operand (operands[1], TDmode))" ! "#" ! "&& reload_completed" ! [(pc)] ! { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } ! [(set_attr "length" "8,8,8,20,20,16")]) ;; Hardware support for decimal floating point operations. --- 148,171 ---- "") (define_insn "*abstd2_fpr" ! [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d") ! (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))] "TARGET_HARD_FLOAT && TARGET_FPRS" ! "@ ! fabs %0,%1 ! fabs %0,%1\;fmr %L0,%L1" ! [(set_attr "type" "fp") ! (set_attr "length" "4,8")]) (define_insn "*nabstd2_fpr" ! [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d") ! (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))] "TARGET_HARD_FLOAT && TARGET_FPRS" ! "@ ! fnabs %0,%1 ! fnabs %0,%1\;fmr %L0,%L1" ! [(set_attr "type" "fp") ! (set_attr "length" "4,8")]) ;; Hardware support for decimal floating point operations. *************** *** 599,601 **** --- 322,393 ---- "TARGET_DFP" "dctfixq %0,%1" [(set_attr "type" "fp")]) + + + ;; Decimal builtin support + + (define_c_enum "unspec" + [UNSPEC_DDEDPD + UNSPEC_DENBCD + UNSPEC_DXEX + UNSPEC_DIEX + UNSPEC_DSCLI + UNSPEC_DSCRI]) + + (define_mode_iterator D64_D128 [DD TD]) + + (define_mode_attr dfp_suffix [(DD "") + (TD "q")]) + + (define_insn "dfp_ddedpd_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i") + (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + UNSPEC_DDEDPD))] + "TARGET_DFP" + "ddedpd %1,%0,%2" + [(set_attr "type" "fp")]) + + (define_insn "dfp_denbcd_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i") + (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + UNSPEC_DENBCD))] + "TARGET_DFP" + "denbcd %1,%0,%2" + [(set_attr "type" "fp")]) + + (define_insn "dfp_dxex_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")] + UNSPEC_DXEX))] + "TARGET_DFP" + "dxex %0,%1" + [(set_attr "type" "fp")]) + + (define_insn "dfp_diex_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") + (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + UNSPEC_DXEX))] + "TARGET_DFP" + "diex %0,%1,%2" + [(set_attr "type" "fp")]) + + (define_insn "dfp_dscli_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") + (match_operand:QI 2 "immediate_operand" "i")] + UNSPEC_DSCLI))] + "TARGET_DFP" + "dscli %0,%1,%2" + [(set_attr "type" "fp")]) + + (define_insn "dfp_dscri_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") + (match_operand:QI 2 "immediate_operand" "i")] + UNSPEC_DSCRI))] + "TARGET_DFP" + "dscri %0,%1,%2" + [(set_attr "type" "fp")]) diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/htm.md gcc-4.8.3/gcc/config/rs6000/htm.md *** gcc-4.8.2/gcc/config/rs6000/htm.md Thu Jan 1 00:00:00 1970 --- gcc-4.8.3/gcc/config/rs6000/htm.md Fri Apr 4 13:45:28 2014 *************** *** 0 **** --- 1,366 ---- + ;; Hardware Transactional Memory (HTM) patterns. + ;; Copyright (C) 2013 Free Software Foundation, Inc. + ;; Contributed by Peter Bergner . + + ;; This file is part of GCC. + + ;; GCC is free software; you can redistribute it and/or modify it + ;; under the terms of the GNU General Public License as published + ;; by the Free Software Foundation; either version 3, or (at your + ;; option) any later version. + + ;; GCC is distributed in the hope that it will be useful, but WITHOUT + ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + ;; License for more details. + + ;; You should have received a copy of the GNU General Public License + ;; along with GCC; see the file COPYING3. If not see + ;; . + + (define_constants + [(TFHAR_SPR 128) + (TFIAR_SPR 129) + (TEXASR_SPR 130) + (TEXASRU_SPR 131) + (MAX_HTM_OPERANDS 4) + ]) + + ;; + ;; UNSPEC_VOLATILE usage + ;; + + (define_c_enum "unspecv" + [UNSPECV_HTM_TABORT + UNSPECV_HTM_TABORTDC + UNSPECV_HTM_TABORTDCI + UNSPECV_HTM_TABORTWC + UNSPECV_HTM_TABORTWCI + UNSPECV_HTM_TBEGIN + UNSPECV_HTM_TCHECK + UNSPECV_HTM_TEND + UNSPECV_HTM_TRECHKPT + UNSPECV_HTM_TRECLAIM + UNSPECV_HTM_TSR + UNSPECV_HTM_MFSPR + UNSPECV_HTM_MTSPR + ]) + + + (define_expand "tabort" + [(set (match_dup 2) + (unspec_volatile:CC [(match_operand:SI 1 "int_reg_operand" "")] + UNSPECV_HTM_TABORT)) + (set (match_dup 3) + (eq:SI (match_dup 2) + (const_int 0))) + (set (match_operand:SI 0 "int_reg_operand" "") + (minus:SI (const_int 1) (match_dup 3)))] + "TARGET_HTM" + { + operands[2] = gen_rtx_REG (CCmode, CR0_REGNO); + operands[3] = gen_reg_rtx (SImode); + }) + + (define_insn "*tabort_internal" + [(set (match_operand:CC 1 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand:SI 0 "int_reg_operand" "r")] + UNSPECV_HTM_TABORT))] + "TARGET_HTM" + "tabort. %0" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + + (define_expand "tabortdc" + [(set (match_dup 4) + (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n") + (match_operand:SI 2 "gpc_reg_operand" "r") + (match_operand:SI 3 "gpc_reg_operand" "r")] + UNSPECV_HTM_TABORTDC)) + (set (match_dup 5) + (eq:SI (match_dup 4) + (const_int 0))) + (set (match_operand:SI 0 "int_reg_operand" "") + (minus:SI (const_int 1) (match_dup 5)))] + "TARGET_HTM" + { + operands[4] = gen_rtx_REG (CCmode, CR0_REGNO); + operands[5] = gen_reg_rtx (SImode); + }) + + (define_insn "*tabortdc_internal" + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n") + (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")] + UNSPECV_HTM_TABORTDC))] + "TARGET_HTM" + "tabortdc. %0,%1,%2" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + + (define_expand "tabortdci" + [(set (match_dup 4) + (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n") + (match_operand:SI 2 "gpc_reg_operand" "r") + (match_operand 3 "s5bit_cint_operand" "n")] + UNSPECV_HTM_TABORTDCI)) + (set (match_dup 5) + (eq:SI (match_dup 4) + (const_int 0))) + (set (match_operand:SI 0 "int_reg_operand" "") + (minus:SI (const_int 1) (match_dup 5)))] + "TARGET_HTM" + { + operands[4] = gen_rtx_REG (CCmode, CR0_REGNO); + operands[5] = gen_reg_rtx (SImode); + }) + + (define_insn "*tabortdci_internal" + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n") + (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand 2 "s5bit_cint_operand" "n")] + UNSPECV_HTM_TABORTDCI))] + "TARGET_HTM" + "tabortdci. %0,%1,%2" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + + (define_expand "tabortwc" + [(set (match_dup 4) + (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n") + (match_operand:SI 2 "gpc_reg_operand" "r") + (match_operand:SI 3 "gpc_reg_operand" "r")] + UNSPECV_HTM_TABORTWC)) + (set (match_dup 5) + (eq:SI (match_dup 4) + (const_int 0))) + (set (match_operand:SI 0 "int_reg_operand" "") + (minus:SI (const_int 1) (match_dup 5)))] + "TARGET_HTM" + { + operands[4] = gen_rtx_REG (CCmode, CR0_REGNO); + operands[5] = gen_reg_rtx (SImode); + }) + + (define_insn "*tabortwc_internal" + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n") + (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")] + UNSPECV_HTM_TABORTWC))] + "TARGET_HTM" + "tabortwc. %0,%1,%2" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + + (define_expand "tabortwci" + [(set (match_dup 4) + (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n") + (match_operand:SI 2 "gpc_reg_operand" "r") + (match_operand 3 "s5bit_cint_operand" "n")] + UNSPECV_HTM_TABORTWCI)) + (set (match_dup 5) + (eq:SI (match_dup 4) + (const_int 0))) + (set (match_operand:SI 0 "int_reg_operand" "") + (minus:SI (const_int 1) (match_dup 5)))] + "TARGET_HTM" + { + operands[4] = gen_rtx_REG (CCmode, CR0_REGNO); + operands[5] = gen_reg_rtx (SImode); + }) + + (define_expand "ttest" + [(set (match_dup 1) + (unspec_volatile:CC [(const_int 0) + (reg:SI 0) + (const_int 0)] + UNSPECV_HTM_TABORTWCI)) + (set (subreg:CC (match_dup 2) 0) (match_dup 1)) + (set (match_dup 3) (lshiftrt:SI (match_dup 2) (const_int 24))) + (parallel [(set (match_operand:SI 0 "int_reg_operand" "") + (and:SI (match_dup 3) (const_int 15))) + (clobber (scratch:CC))])] + "TARGET_HTM" + { + operands[1] = gen_rtx_REG (CCmode, CR0_REGNO); + operands[2] = gen_reg_rtx (SImode); + operands[3] = gen_reg_rtx (SImode); + }) + + (define_insn "*tabortwci_internal" + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n") + (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand 2 "s5bit_cint_operand" "n")] + UNSPECV_HTM_TABORTWCI))] + "TARGET_HTM" + "tabortwci. %0,%1,%2" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + + (define_expand "tbegin" + [(set (match_dup 2) + (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")] + UNSPECV_HTM_TBEGIN)) + (set (match_dup 3) + (eq:SI (match_dup 2) + (const_int 0))) + (set (match_operand:SI 0 "int_reg_operand" "") + (minus:SI (const_int 1) (match_dup 3)))] + "TARGET_HTM" + { + operands[2] = gen_rtx_REG (CCmode, CR0_REGNO); + operands[3] = gen_reg_rtx (SImode); + }) + + (define_insn "*tbegin_internal" + [(set (match_operand:CC 1 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")] + UNSPECV_HTM_TBEGIN))] + "TARGET_HTM" + "tbegin. %0" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + + (define_expand "tcheck" + [(set (match_dup 2) + (unspec_volatile:CC [(match_operand 1 "u3bit_cint_operand" "n")] + UNSPECV_HTM_TCHECK)) + (set (match_dup 3) + (eq:SI (match_dup 2) + (const_int 0))) + (set (match_operand:SI 0 "int_reg_operand" "") + (minus:SI (const_int 1) (match_dup 3)))] + "TARGET_HTM" + { + operands[2] = gen_rtx_REG (CCmode, CR0_REGNO); + operands[3] = gen_reg_rtx (SImode); + }) + + (define_insn "*tcheck_internal" + [(set (match_operand:CC 1 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand 0 "u3bit_cint_operand" "n")] + UNSPECV_HTM_TCHECK))] + "TARGET_HTM" + "tcheck. %0" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + + (define_expand "tend" + [(set (match_dup 2) + (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")] + UNSPECV_HTM_TEND)) + (set (match_dup 3) + (eq:SI (match_dup 2) + (const_int 0))) + (set (match_operand:SI 0 "int_reg_operand" "") + (minus:SI (const_int 1) (match_dup 3)))] + "TARGET_HTM" + { + operands[2] = gen_rtx_REG (CCmode, CR0_REGNO); + operands[3] = gen_reg_rtx (SImode); + }) + + (define_insn "*tend_internal" + [(set (match_operand:CC 1 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")] + UNSPECV_HTM_TEND))] + "TARGET_HTM" + "tend. %0" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + + (define_expand "trechkpt" + [(set (match_dup 1) + (unspec_volatile:CC [(const_int 0)] + UNSPECV_HTM_TRECHKPT)) + (set (match_dup 2) + (eq:SI (match_dup 1) + (const_int 0))) + (set (match_operand:SI 0 "int_reg_operand" "") + (minus:SI (const_int 1) (match_dup 2)))] + "TARGET_HTM" + { + operands[1] = gen_rtx_REG (CCmode, CR0_REGNO); + operands[2] = gen_reg_rtx (SImode); + }) + + (define_insn "*trechkpt_internal" + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (unspec_volatile:CC [(const_int 0)] + UNSPECV_HTM_TRECHKPT))] + "TARGET_HTM" + "trechkpt." + [(set_attr "type" "htm") + (set_attr "length" "4")]) + + (define_expand "treclaim" + [(set (match_dup 2) + (unspec_volatile:CC [(match_operand:SI 1 "gpc_reg_operand" "r")] + UNSPECV_HTM_TRECLAIM)) + (set (match_dup 3) + (eq:SI (match_dup 2) + (const_int 0))) + (set (match_operand:SI 0 "int_reg_operand" "") + (minus:SI (const_int 1) (match_dup 3)))] + "TARGET_HTM" + { + operands[2] = gen_rtx_REG (CCmode, CR0_REGNO); + operands[3] = gen_reg_rtx (SImode); + }) + + (define_insn "*treclaim_internal" + [(set (match_operand:CC 1 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")] + UNSPECV_HTM_TRECLAIM))] + "TARGET_HTM" + "treclaim. %0" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + + (define_expand "tsr" + [(set (match_dup 2) + (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")] + UNSPECV_HTM_TSR)) + (set (match_dup 3) + (eq:SI (match_dup 2) + (const_int 0))) + (set (match_operand:SI 0 "int_reg_operand" "") + (minus:SI (const_int 1) (match_dup 3)))] + "TARGET_HTM" + { + operands[2] = gen_rtx_REG (CCmode, CR0_REGNO); + operands[3] = gen_reg_rtx (SImode); + }) + + (define_insn "*tsr_internal" + [(set (match_operand:CC 1 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")] + UNSPECV_HTM_TSR))] + "TARGET_HTM" + "tsr. %0" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + + (define_insn "htm_mfspr_" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (unspec_volatile:P [(match_operand 1 "u10bit_cint_operand" "n") + (match_operand:P 2 "htm_spr_reg_operand" "")] + UNSPECV_HTM_MFSPR))] + "TARGET_HTM" + "mfspr %0,%1"; + [(set_attr "type" "htm") + (set_attr "length" "4")]) + + (define_insn "htm_mtspr_" + [(set (match_operand:P 2 "htm_spr_reg_operand" "") + (unspec_volatile:P [(match_operand:P 0 "gpc_reg_operand" "r") + (match_operand 1 "u10bit_cint_operand" "n")] + UNSPECV_HTM_MTSPR))] + "TARGET_HTM" + "mtspr %1,%0"; + [(set_attr "type" "htm") + (set_attr "length" "4")]) diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/htmintrin.h gcc-4.8.3/gcc/config/rs6000/htmintrin.h *** gcc-4.8.2/gcc/config/rs6000/htmintrin.h Thu Jan 1 00:00:00 1970 --- gcc-4.8.3/gcc/config/rs6000/htmintrin.h Fri Apr 4 13:45:28 2014 *************** *** 0 **** --- 1,131 ---- + /* Hardware Transactional Memory (HTM) intrinsics. + Copyright (C) 2013 Free Software Foundation, Inc. + Contributed by Peter Bergner . + + This file is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This file is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + + #ifndef __HTM__ + # error "HTM instruction set not enabled" + #endif /* __HTM__ */ + + #ifndef _HTMINTRIN_H + #define _HTMINTRIN_H + + #include + + typedef uint64_t texasr_t; + typedef uint32_t texasru_t; + typedef uint32_t texasrl_t; + typedef uintptr_t tfiar_t; + typedef uintptr_t tfhar_t; + + #define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3) + #define _HTM_NONTRANSACTIONAL 0x0 + #define _HTM_SUSPENDED 0x1 + #define _HTM_TRANSACTIONAL 0x2 + + /* The following macros use the IBM bit numbering for BITNUM + as used in the ISA documentation. */ + + #define _TEXASR_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \ + (((TEXASR) >> (63-(BITNUM))) & ((1<<(SIZE))-1)) + #define _TEXASRU_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \ + (((TEXASR) >> (31-(BITNUM))) & ((1<<(SIZE))-1)) + + #define _TEXASR_FAILURE_CODE(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 7, 8) + #define _TEXASRU_FAILURE_CODE(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 8) + + #define _TEXASR_FAILURE_PERSISTENT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 7, 1) + #define _TEXASRU_FAILURE_PERSISTENT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 1) + + #define _TEXASR_DISALLOWED(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 8, 1) + #define _TEXASRU_DISALLOWED(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 8, 1) + + #define _TEXASR_NESTING_OVERFLOW(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 9, 1) + #define _TEXASRU_NESTING_OVERFLOW(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 9, 1) + + #define _TEXASR_FOOTPRINT_OVERFLOW(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 10, 1) + #define _TEXASRU_FOOTPRINT_OVERFLOW(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 10, 1) + + #define _TEXASR_SELF_INDUCED_CONFLICT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 11, 1) + #define _TEXASRU_SELF_INDUCED_CONFLICT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 11, 1) + + #define _TEXASR_NON_TRANSACTIONAL_CONFLICT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 12, 1) + #define _TEXASRU_NON_TRANSACTIONAL_CONFLICT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 12, 1) + + #define _TEXASR_TRANSACTION_CONFLICT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 13, 1) + #define _TEXASRU_TRANSACTION_CONFLICT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 13, 1) + + #define _TEXASR_TRANSLATION_INVALIDATION_CONFLICT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 14, 1) + #define _TEXASRU_TRANSLATION_INVALIDATION_CONFLICT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 14, 1) + + #define _TEXASR_IMPLEMENTAION_SPECIFIC(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 15, 1) + #define _TEXASRU_IMPLEMENTAION_SPECIFIC(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 15, 1) + + #define _TEXASR_INSTRUCTION_FETCH_CONFLICT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 16, 1) + #define _TEXASRU_INSTRUCTION_FETCH_CONFLICT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 16, 1) + + #define _TEXASR_ABORT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 31, 1) + #define _TEXASRU_ABORT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 31, 1) + + + #define _TEXASR_SUSPENDED(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 32, 1) + + #define _TEXASR_PRIVILEGE(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 35, 2) + + #define _TEXASR_FAILURE_SUMMARY(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 36, 1) + + #define _TEXASR_TFIAR_EXACT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 37, 1) + + #define _TEXASR_ROT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 38, 1) + + #define _TEXASR_TRANSACTION_LEVEL(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 63, 12) + + #endif /* _HTMINTRIN_H */ diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/htmxlintrin.h gcc-4.8.3/gcc/config/rs6000/htmxlintrin.h *** gcc-4.8.2/gcc/config/rs6000/htmxlintrin.h Thu Jan 1 00:00:00 1970 --- gcc-4.8.3/gcc/config/rs6000/htmxlintrin.h Fri May 16 03:46:23 2014 *************** *** 0 **** --- 1,213 ---- + /* XL compiler Hardware Transactional Memory (HTM) execution intrinsics. + Copyright (C) 2013 Free Software Foundation, Inc. + Contributed by Peter Bergner . + + This file is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This file is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + + #ifndef __HTM__ + # error "HTM instruction set not enabled" + #endif /* __HTM__ */ + + #ifndef _HTMXLINTRIN_H + #define _HTMXLINTRIN_H + + #include + #include + + #ifdef __cplusplus + extern "C" { + #endif + + #define _TEXASR_PTR(TM_BUF) \ + ((texasr_t *)((TM_BUF)+0)) + #define _TEXASRU_PTR(TM_BUF) \ + ((texasru_t *)((TM_BUF)+0)) + #define _TEXASRL_PTR(TM_BUF) \ + ((texasrl_t *)((TM_BUF)+4)) + #define _TFIAR_PTR(TM_BUF) \ + ((tfiar_t *)((TM_BUF)+8)) + + typedef char TM_buff_type[16]; + + /* Compatibility macro with s390. This macro can be used to determine + whether a transaction was successfully started from the __TM_begin() + and __TM_simple_begin() intrinsic functions below. */ + #define _HTM_TBEGIN_STARTED 1 + + extern __inline long + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_simple_begin (void) + { + if (__builtin_expect (__builtin_tbegin (0), 1)) + return _HTM_TBEGIN_STARTED; + return 0; + } + + extern __inline long + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_begin (void* const TM_buff) + { + *_TEXASRL_PTR (TM_buff) = 0; + if (__builtin_expect (__builtin_tbegin (0), 1)) + return _HTM_TBEGIN_STARTED; + #ifdef __powerpc64__ + *_TEXASR_PTR (TM_buff) = __builtin_get_texasr (); + #else + *_TEXASRU_PTR (TM_buff) = __builtin_get_texasru (); + *_TEXASRL_PTR (TM_buff) = __builtin_get_texasr (); + #endif + *_TFIAR_PTR (TM_buff) = __builtin_get_tfiar (); + return 0; + } + + extern __inline long + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_end (void) + { + if (__builtin_expect (__builtin_tend (0), 1)) + return 1; + return 0; + } + + extern __inline void + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_abort (void) + { + __builtin_tabort (0); + } + + extern __inline void + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_named_abort (unsigned char const code) + { + __builtin_tabort (code); + } + + extern __inline void + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_resume (void) + { + __builtin_tresume (); + } + + extern __inline void + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_suspend (void) + { + __builtin_tsuspend (); + } + + extern __inline long + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_is_user_abort (void* const TM_buff) + { + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + return _TEXASRU_ABORT (texasru); + } + + extern __inline long + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_is_named_user_abort (void* const TM_buff, unsigned char *code) + { + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + + *code = _TEXASRU_FAILURE_CODE (texasru); + return _TEXASRU_ABORT (texasru); + } + + extern __inline long + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_is_illegal (void* const TM_buff) + { + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + return _TEXASRU_DISALLOWED (texasru); + } + + extern __inline long + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_is_footprint_exceeded (void* const TM_buff) + { + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + return _TEXASRU_FOOTPRINT_OVERFLOW (texasru); + } + + extern __inline long + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_nesting_depth (void* const TM_buff) + { + texasrl_t texasrl; + + if (_HTM_STATE (__builtin_ttest ()) == _HTM_NONTRANSACTIONAL) + { + texasrl = *_TEXASRL_PTR (TM_buff); + if (!_TEXASR_FAILURE_SUMMARY (texasrl)) + texasrl = 0; + } + else + texasrl = (texasrl_t) __builtin_get_texasr (); + + return _TEXASR_TRANSACTION_LEVEL (texasrl); + } + + extern __inline long + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_is_nested_too_deep(void* const TM_buff) + { + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + return _TEXASRU_NESTING_OVERFLOW (texasru); + } + + extern __inline long + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_is_conflict(void* const TM_buff) + { + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + /* Return TEXASR bits 11 (Self-Induced Conflict) through + 14 (Translation Invalidation Conflict). */ + return (_TEXASRU_EXTRACT_BITS (texasru, 14, 4)) ? 1 : 0; + } + + extern __inline long + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_is_failure_persistent(void* const TM_buff) + { + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + return _TEXASRU_FAILURE_PERSISTENT (texasru); + } + + extern __inline long + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_failure_address(void* const TM_buff) + { + return *_TFIAR_PTR (TM_buff); + } + + extern __inline long long + __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) + __TM_failure_code(void* const TM_buff) + { + return *_TEXASR_PTR (TM_buff); + } + + #ifdef __cplusplus + } + #endif + + #endif /* _HTMXLINTRIN_H */ diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/linux64.h gcc-4.8.3/gcc/config/rs6000/linux64.h *** gcc-4.8.2/gcc/config/rs6000/linux64.h Wed Jun 19 01:18:38 2013 --- gcc-4.8.3/gcc/config/rs6000/linux64.h Fri Apr 4 15:10:24 2014 *************** *** 25,33 **** #ifndef RS6000_BI_ARCH - #undef DEFAULT_ABI - #define DEFAULT_ABI ABI_AIX - #undef TARGET_64BIT #define TARGET_64BIT 1 --- 25,30 ---- *************** extern int dot_symbols; *** 74,80 **** --- 71,81 ---- #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER7 #undef PROCESSOR_DEFAULT64 + #ifdef LINUX64_DEFAULT_ABI_ELFv2 + #define PROCESSOR_DEFAULT64 PROCESSOR_POWER8 + #else #define PROCESSOR_DEFAULT64 PROCESSOR_POWER7 + #endif /* We don't need to generate entries in .fixup, except when -mrelocatable or -mrelocatable-lib is given. */ *************** extern int dot_symbols; *** 88,93 **** --- 89,100 ---- #define INVALID_64BIT "-m%s not supported in this configuration" #define INVALID_32BIT INVALID_64BIT + #ifdef LINUX64_DEFAULT_ABI_ELFv2 + #define ELFv2_ABI_CHECK (rs6000_elf_abi != 1) + #else + #define ELFv2_ABI_CHECK (rs6000_elf_abi == 2) + #endif + #undef SUBSUBTARGET_OVERRIDE_OPTIONS #define SUBSUBTARGET_OVERRIDE_OPTIONS \ do \ *************** extern int dot_symbols; *** 102,107 **** --- 109,120 ---- error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ + if (ELFv2_ABI_CHECK) \ + { \ + rs6000_current_abi = ABI_ELFv2; \ + if (dot_symbols) \ + error ("-mcall-aixdesc incompatible with -mabi=elfv2"); \ + } \ if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ *************** extern int dot_symbols; *** 136,143 **** SET_CMODEL (CMODEL_MEDIUM); \ if (rs6000_current_cmodel != CMODEL_SMALL) \ { \ ! TARGET_NO_FP_IN_TOC = 0; \ ! TARGET_NO_SUM_IN_TOC = 0; \ } \ } \ } \ --- 149,159 ---- SET_CMODEL (CMODEL_MEDIUM); \ if (rs6000_current_cmodel != CMODEL_SMALL) \ { \ ! if (!global_options_set.x_TARGET_NO_FP_IN_TOC) \ ! TARGET_NO_FP_IN_TOC \ ! = rs6000_current_cmodel == CMODEL_MEDIUM; \ ! if (!global_options_set.x_TARGET_NO_SUM_IN_TOC) \ ! TARGET_NO_SUM_IN_TOC = 0; \ } \ } \ } \ *************** extern int dot_symbols; *** 351,357 **** #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)" #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" ! #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld64.so.1" #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0" #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0" #if DEFAULT_LIBC == LIBC_UCLIBC --- 367,377 ---- #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)" #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" ! #ifdef LINUX64_DEFAULT_ABI_ELFv2 ! #define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/lib64/ld64.so.1;:/lib64/ld64.so.2}" ! #else ! #define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/lib64/ld64.so.2;:/lib64/ld64.so.1}" ! #endif #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0" #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0" #if DEFAULT_LIBC == LIBC_UCLIBC diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/option-defaults.h gcc-4.8.3/gcc/config/rs6000/option-defaults.h *** gcc-4.8.2/gcc/config/rs6000/option-defaults.h Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/rs6000/option-defaults.h Fri Apr 4 14:17:55 2014 *************** *** 54,59 **** --- 54,60 ---- --with-float is ignored if -mhard-float or -msoft-float are specified. */ #define OPTION_DEFAULT_SPECS \ + {"abi", "%{!mabi=elfv*:-mabi=%(VALUE)}" }, \ {"tune", "%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}" }, \ {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \ {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \ diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/power8.md gcc-4.8.3/gcc/config/rs6000/power8.md *** gcc-4.8.2/gcc/config/rs6000/power8.md Thu Jan 1 00:00:00 1970 --- gcc-4.8.3/gcc/config/rs6000/power8.md Fri Apr 4 13:39:27 2014 *************** *** 0 **** --- 1,373 ---- + ;; Scheduling description for IBM POWER8 processor. + ;; Copyright (C) 2013 Free Software Foundation, Inc. + ;; + ;; Contributed by Pat Haugen (pthaugen@us.ibm.com). + + ;; This file is part of GCC. + ;; + ;; GCC is free software; you can redistribute it and/or modify it + ;; under the terms of the GNU General Public License as published + ;; by the Free Software Foundation; either version 3, or (at your + ;; option) any later version. + ;; + ;; GCC is distributed in the hope that it will be useful, but WITHOUT + ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + ;; License for more details. + ;; + ;; You should have received a copy of the GNU General Public License + ;; along with GCC; see the file COPYING3. If not see + ;; . + + (define_automaton "power8fxu,power8lsu,power8vsu,power8misc") + + (define_cpu_unit "fxu0_power8,fxu1_power8" "power8fxu") + (define_cpu_unit "lu0_power8,lu1_power8" "power8lsu") + (define_cpu_unit "lsu0_power8,lsu1_power8" "power8lsu") + (define_cpu_unit "vsu0_power8,vsu1_power8" "power8vsu") + (define_cpu_unit "bpu_power8,cru_power8" "power8misc") + (define_cpu_unit "du0_power8,du1_power8,du2_power8,du3_power8,du4_power8,\ + du5_power8,du6_power8" "power8misc") + + + ; Dispatch group reservations + (define_reservation "DU_any_power8" + "du0_power8|du1_power8|du2_power8|du3_power8|du4_power8|\ + du5_power8") + + ; 2-way Cracked instructions go in slots 0-1 + ; (can also have a second in slots 3-4 if insns are adjacent) + (define_reservation "DU_cracked_power8" + "du0_power8+du1_power8") + + ; Insns that are first in group + (define_reservation "DU_first_power8" + "du0_power8") + + ; Insns that are first and last in group + (define_reservation "DU_both_power8" + "du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+\ + du5_power8+du6_power8") + + ; Dispatch slots are allocated in order conforming to program order. + (absence_set "du0_power8" "du1_power8,du2_power8,du3_power8,du4_power8,\ + du5_power8,du6_power8") + (absence_set "du1_power8" "du2_power8,du3_power8,du4_power8,du5_power8,\ + du6_power8") + (absence_set "du2_power8" "du3_power8,du4_power8,du5_power8,du6_power8") + (absence_set "du3_power8" "du4_power8,du5_power8,du6_power8") + (absence_set "du4_power8" "du5_power8,du6_power8") + (absence_set "du5_power8" "du6_power8") + + + ; Execution unit reservations + (define_reservation "FXU_power8" + "fxu0_power8|fxu1_power8") + + (define_reservation "LU_power8" + "lu0_power8|lu1_power8") + + (define_reservation "LSU_power8" + "lsu0_power8|lsu1_power8") + + (define_reservation "LU_or_LSU_power8" + "lu0_power8|lu1_power8|lsu0_power8|lsu1_power8") + + (define_reservation "VSU_power8" + "vsu0_power8|vsu1_power8") + + + ; LS Unit + (define_insn_reservation "power8-load" 3 + (and (eq_attr "type" "load") + (eq_attr "cpu" "power8")) + "DU_any_power8,LU_or_LSU_power8") + + (define_insn_reservation "power8-load-update" 3 + (and (eq_attr "type" "load_u,load_ux") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,LU_or_LSU_power8+FXU_power8") + + (define_insn_reservation "power8-load-ext" 3 + (and (eq_attr "type" "load_ext") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,LU_or_LSU_power8,FXU_power8") + + (define_insn_reservation "power8-load-ext-update" 3 + (and (eq_attr "type" "load_ext_u,load_ext_ux") + (eq_attr "cpu" "power8")) + "DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8") + + (define_insn_reservation "power8-fpload" 5 + (and (eq_attr "type" "fpload,vecload") + (eq_attr "cpu" "power8")) + "DU_any_power8,LU_power8") + + (define_insn_reservation "power8-fpload-update" 5 + (and (eq_attr "type" "fpload_u,fpload_ux") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,LU_power8+FXU_power8") + + (define_insn_reservation "power8-store" 5 ; store-forwarding latency + (and (eq_attr "type" "store,store_u") + (eq_attr "cpu" "power8")) + "DU_any_power8,LSU_power8+LU_power8") + + (define_insn_reservation "power8-store-update-indexed" 5 + (and (eq_attr "type" "store_ux") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,LSU_power8+LU_power8") + + (define_insn_reservation "power8-fpstore" 5 + (and (eq_attr "type" "fpstore") + (eq_attr "cpu" "power8")) + "DU_any_power8,LSU_power8+VSU_power8") + + (define_insn_reservation "power8-fpstore-update" 5 + (and (eq_attr "type" "fpstore_u,fpstore_ux") + (eq_attr "cpu" "power8")) + "DU_any_power8,LSU_power8+VSU_power8") + + (define_insn_reservation "power8-vecstore" 5 + (and (eq_attr "type" "vecstore") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,LSU_power8+VSU_power8") + + (define_insn_reservation "power8-larx" 3 + (and (eq_attr "type" "load_l") + (eq_attr "cpu" "power8")) + "DU_both_power8,LU_or_LSU_power8") + + (define_insn_reservation "power8-stcx" 10 + (and (eq_attr "type" "store_c") + (eq_attr "cpu" "power8")) + "DU_both_power8,LSU_power8+LU_power8") + + (define_insn_reservation "power8-sync" 1 + (and (eq_attr "type" "sync,isync") + (eq_attr "cpu" "power8")) + "DU_both_power8,LSU_power8") + + + ; FX Unit + (define_insn_reservation "power8-1cyc" 1 + (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ + var_shift_rotate,exts,isel") + (eq_attr "cpu" "power8")) + "DU_any_power8,FXU_power8") + + ; Extra cycle to LU/LSU + (define_bypass 2 "power8-1cyc" + "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ + power8-vecstore,power8-larx,power8-stcx") + ; "power8-load,power8-load-update,power8-load-ext,\ + ; power8-load-ext-update,power8-fpload,power8-fpload-update,\ + ; power8-store,power8-store-update,power8-store-update-indexed,\ + ; power8-fpstore,power8-fpstore-update,power8-vecstore,\ + ; power8-larx,power8-stcx") + + (define_insn_reservation "power8-2cyc" 2 + (and (eq_attr "type" "cntlz,popcnt") + (eq_attr "cpu" "power8")) + "DU_any_power8,FXU_power8") + + (define_insn_reservation "power8-two" 2 + (and (eq_attr "type" "two") + (eq_attr "cpu" "power8")) + "DU_any_power8+DU_any_power8,FXU_power8,FXU_power8") + + (define_insn_reservation "power8-three" 3 + (and (eq_attr "type" "three") + (eq_attr "cpu" "power8")) + "DU_any_power8+DU_any_power8+DU_any_power8,FXU_power8,FXU_power8,FXU_power8") + + ; cmp - Normal compare insns + (define_insn_reservation "power8-cmp" 2 + (and (eq_attr "type" "cmp") + (eq_attr "cpu" "power8")) + "DU_any_power8,FXU_power8") + + ; fast_compare : add./and./nor./etc + (define_insn_reservation "power8-fast-compare" 2 + (and (eq_attr "type" "fast_compare") + (eq_attr "cpu" "power8")) + "DU_any_power8,FXU_power8") + + ; compare : rldicl./exts./etc + ; delayed_compare : rlwinm./slwi./etc + ; var_delayed_compare : rlwnm./slw./etc + (define_insn_reservation "power8-compare" 2 + (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,FXU_power8,FXU_power8") + + ; Extra cycle to LU/LSU + (define_bypass 3 "power8-fast-compare,power8-compare" + "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ + power8-vecstore,power8-larx,power8-stcx") + + ; 5 cycle CR latency + (define_bypass 5 "power8-fast-compare,power8-compare" + "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch") + + (define_insn_reservation "power8-mul" 4 + (and (eq_attr "type" "imul,imul2,imul3,lmul") + (eq_attr "cpu" "power8")) + "DU_any_power8,FXU_power8") + + (define_insn_reservation "power8-mul-compare" 4 + (and (eq_attr "type" "imul_compare,lmul_compare") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,FXU_power8") + + ; Extra cycle to LU/LSU + (define_bypass 5 "power8-mul,power8-mul-compare" + "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ + power8-vecstore,power8-larx,power8-stcx") + + ; 7 cycle CR latency + (define_bypass 7 "power8-mul,power8-mul-compare" + "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch") + + ; FXU divides are not pipelined + (define_insn_reservation "power8-idiv" 37 + (and (eq_attr "type" "idiv") + (eq_attr "cpu" "power8")) + "DU_any_power8,fxu0_power8*37|fxu1_power8*37") + + (define_insn_reservation "power8-ldiv" 68 + (and (eq_attr "type" "ldiv") + (eq_attr "cpu" "power8")) + "DU_any_power8,fxu0_power8*68|fxu1_power8*68") + + (define_insn_reservation "power8-mtjmpr" 5 + (and (eq_attr "type" "mtjmpr") + (eq_attr "cpu" "power8")) + "DU_first_power8,FXU_power8") + + ; Should differentiate between 1 cr field and > 1 since mtocrf is not microcode + (define_insn_reservation "power8-mtcr" 3 + (and (eq_attr "type" "mtcr") + (eq_attr "cpu" "power8")) + "DU_both_power8,FXU_power8") + + + ; CR Unit + (define_insn_reservation "power8-mfjmpr" 5 + (and (eq_attr "type" "mfjmpr") + (eq_attr "cpu" "power8")) + "DU_first_power8,cru_power8+FXU_power8") + + (define_insn_reservation "power8-crlogical" 3 + (and (eq_attr "type" "cr_logical,delayed_cr") + (eq_attr "cpu" "power8")) + "DU_first_power8,cru_power8") + + (define_insn_reservation "power8-mfcr" 5 + (and (eq_attr "type" "mfcr") + (eq_attr "cpu" "power8")) + "DU_both_power8,cru_power8") + + (define_insn_reservation "power8-mfcrf" 3 + (and (eq_attr "type" "mfcrf") + (eq_attr "cpu" "power8")) + "DU_first_power8,cru_power8") + + + ; BR Unit + ; Branches take dispatch slot 7, but reserve any remaining prior slots to + ; prevent other insns from grabbing them once this is assigned. + (define_insn_reservation "power8-branch" 3 + (and (eq_attr "type" "jmpreg,branch") + (eq_attr "cpu" "power8")) + "(du6_power8\ + |du5_power8+du6_power8\ + |du4_power8+du5_power8+du6_power8\ + |du3_power8+du4_power8+du5_power8+du6_power8\ + |du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\ + |du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\ + |du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+\ + du6_power8),bpu_power8") + + ; Branch updating LR/CTR feeding mf[lr|ctr] + (define_bypass 4 "power8-branch" "power8-mfjmpr") + + + ; VS Unit (includes FP/VSX/VMX/DFP/Crypto) + (define_insn_reservation "power8-fp" 6 + (and (eq_attr "type" "fp,dmul") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + + ; Additional 3 cycles for any CR result + (define_bypass 9 "power8-fp" "power8-crlogical,power8-mfcr*,power8-branch") + + (define_insn_reservation "power8-fpcompare" 8 + (and (eq_attr "type" "fpcompare") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + + (define_insn_reservation "power8-sdiv" 27 + (and (eq_attr "type" "sdiv") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + + (define_insn_reservation "power8-ddiv" 33 + (and (eq_attr "type" "ddiv") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + + (define_insn_reservation "power8-sqrt" 32 + (and (eq_attr "type" "ssqrt") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + + (define_insn_reservation "power8-dsqrt" 44 + (and (eq_attr "type" "dsqrt") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + + (define_insn_reservation "power8-vecsimple" 2 + (and (eq_attr "type" "vecperm,vecsimple,veccmp") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + + (define_insn_reservation "power8-vecnormal" 6 + (and (eq_attr "type" "vecfloat,vecdouble") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + + (define_bypass 7 "power8-vecnormal" + "power8-vecsimple,power8-veccomplex,power8-fpstore*,\ + power8-vecstore") + + (define_insn_reservation "power8-veccomplex" 7 + (and (eq_attr "type" "veccomplex") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + + (define_insn_reservation "power8-vecfdiv" 25 + (and (eq_attr "type" "vecfdiv") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + + (define_insn_reservation "power8-vecdiv" 31 + (and (eq_attr "type" "vecdiv") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + + (define_insn_reservation "power8-mffgpr" 5 + (and (eq_attr "type" "mffgpr") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + + (define_insn_reservation "power8-mftgpr" 6 + (and (eq_attr "type" "mftgpr") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + + (define_insn_reservation "power8-crypto" 7 + (and (eq_attr "type" "crypto") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/ppc-asm.h gcc-4.8.3/gcc/config/rs6000/ppc-asm.h *** gcc-4.8.2/gcc/config/rs6000/ppc-asm.h Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/rs6000/ppc-asm.h Fri Apr 4 14:17:55 2014 *************** see the files COPYING3 and COPYING.RUNTI *** 256,262 **** * the real function with one or two leading periods respectively. */ ! #if defined (__powerpc64__) #define FUNC_NAME(name) GLUE(.,name) #define JUMP_TARGET(name) FUNC_NAME(name) #define FUNC_START(name) \ --- 256,285 ---- * the real function with one or two leading periods respectively. */ ! #if defined(__powerpc64__) && _CALL_ELF == 2 ! ! /* Defining "toc" above breaks @toc in assembler code. */ ! #undef toc ! ! #define FUNC_NAME(name) GLUE(__USER_LABEL_PREFIX__,name) ! #define JUMP_TARGET(name) FUNC_NAME(name) ! #define FUNC_START(name) \ ! .type FUNC_NAME(name),@function; \ ! .globl FUNC_NAME(name); \ ! FUNC_NAME(name): \ ! 0: addis 2,12,(.TOC.-0b)@ha; \ ! addi 2,2,(.TOC.-0b)@l; \ ! .localentry FUNC_NAME(name),.-FUNC_NAME(name) ! ! #define HIDDEN_FUNC(name) \ ! FUNC_START(name) \ ! .hidden FUNC_NAME(name); ! ! #define FUNC_END(name) \ ! .size FUNC_NAME(name),.-FUNC_NAME(name) ! ! #elif defined (__powerpc64__) ! #define FUNC_NAME(name) GLUE(.,name) #define JUMP_TARGET(name) FUNC_NAME(name) #define FUNC_START(name) \ diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/predicates.md gcc-4.8.3/gcc/config/rs6000/predicates.md *** gcc-4.8.2/gcc/config/rs6000/predicates.md Mon Sep 23 14:19:31 2013 --- gcc-4.8.3/gcc/config/rs6000/predicates.md Wed Apr 30 20:04:12 2014 *************** *** 124,129 **** --- 124,134 ---- (and (match_code "const_int") (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15"))) + ;; Return 1 if op is a unsigned 3-bit constant integer. + (define_predicate "u3bit_cint_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7"))) + ;; Return 1 if op is a unsigned 5-bit constant integer. (define_predicate "u5bit_cint_operand" (and (match_code "const_int") *************** *** 135,140 **** --- 140,150 ---- (and (match_code "const_int") (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127"))) + ;; Return 1 if op is a unsigned 10-bit constant integer. + (define_predicate "u10bit_cint_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023"))) + ;; Return 1 if op is a constant integer that can fit in a D field. (define_predicate "short_cint_operand" (and (match_code "const_int") *************** *** 161,171 **** --- 171,191 ---- (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 0, 1)"))) + ;; Match op = 0..3. + (define_predicate "const_0_to_3_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) + ;; Match op = 2 or op = 3. (define_predicate "const_2_to_3_operand" (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 2, 3)"))) + ;; Match op = 0..15 + (define_predicate "const_0_to_15_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) + ;; Return 1 if op is a register that is not special. (define_predicate "gpc_reg_operand" (match_operand 0 "register_operand") *************** *** 182,190 **** --- 202,296 ---- if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op))) return 1; + if (TARGET_VSX && VSX_REGNO_P (REGNO (op))) + return 1; + return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op)); }) + ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't + ;; allow floating point or vector registers. + (define_predicate "int_reg_operand" + (match_operand 0 "register_operand") + { + if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode)) + return 0; + + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + if (!REG_P (op)) + return 0; + + if (REGNO (op) >= FIRST_PSEUDO_REGISTER) + return 1; + + return INT_REGNO_P (REGNO (op)); + }) + + ;; Like int_reg_operand, but only return true for base registers + (define_predicate "base_reg_operand" + (match_operand 0 "int_reg_operand") + { + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + if (!REG_P (op)) + return 0; + + return (REGNO (op) != FIRST_GPR_REGNO); + }) + + ;; Return 1 if op is a HTM specific SPR register. + (define_predicate "htm_spr_reg_operand" + (match_operand 0 "register_operand") + { + if (!TARGET_HTM) + return 0; + + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + if (!REG_P (op)) + return 0; + + switch (REGNO (op)) + { + case TFHAR_REGNO: + case TFIAR_REGNO: + case TEXASR_REGNO: + return 1; + default: + break; + } + + /* Unknown SPR. */ + return 0; + }) + + ;; Return 1 if op is a general purpose register that is an even register + ;; which suitable for a load/store quad operation + (define_predicate "quad_int_reg_operand" + (match_operand 0 "register_operand") + { + HOST_WIDE_INT r; + + if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC) + return 0; + + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + if (!REG_P (op)) + return 0; + + r = REGNO (op); + if (r >= FIRST_PSEUDO_REGISTER) + return 1; + + return (INT_REGNO_P (r) && ((r & 1) == 0)); + }) + ;; Return 1 if op is a register that is a condition register field. (define_predicate "cc_reg_operand" (match_operand 0 "register_operand") *************** *** 315,320 **** --- 421,431 ---- && CONST_DOUBLE_HIGH (op) == 0") (match_operand 0 "gpc_reg_operand")))) + ;; Like reg_or_logical_cint_operand, but allow vsx registers + (define_predicate "vsx_reg_or_cint_operand" + (ior (match_operand 0 "vsx_register_operand") + (match_operand 0 "reg_or_logical_cint_operand"))) + ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register ;; with no more than one instruction per word. (define_predicate "easy_fp_constant" *************** *** 333,338 **** --- 444,454 ---- && mode != DImode) return 1; + /* The constant 0.0 is easy under VSX. */ + if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode) + && VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode)) + return 1; + if (DECIMAL_FLOAT_MODE_P (mode)) return 0; *************** *** 521,526 **** --- 637,691 ---- (and (match_operand 0 "memory_operand") (match_test "offsettable_nonstrict_memref_p (op)"))) + ;; Return 1 if the operand is suitable for load/store quad memory. + ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx). + (define_predicate "quad_memory_operand" + (match_code "mem") + { + rtx addr, op0, op1; + int ret; + + if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI) + ret = 0; + + else if (!memory_operand (op, mode)) + ret = 0; + + else if (GET_MODE_SIZE (GET_MODE (op)) != 16) + ret = 0; + + else if (MEM_ALIGN (op) < 128) + ret = 0; + + else + { + addr = XEXP (op, 0); + if (int_reg_operand (addr, Pmode)) + ret = 1; + + else if (GET_CODE (addr) != PLUS) + ret = 0; + + else + { + op0 = XEXP (addr, 0); + op1 = XEXP (addr, 1); + ret = (int_reg_operand (op0, Pmode) + && GET_CODE (op1) == CONST_INT + && IN_RANGE (INTVAL (op1), -32768, 32767) + && (INTVAL (op1) & 15) == 0); + } + } + + if (TARGET_DEBUG_ADDR) + { + fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false"); + debug_rtx (op); + } + + return ret; + }) + ;; Return 1 if the operand is an indexed or indirect memory operand. (define_predicate "indexed_or_indirect_operand" (match_code "mem") *************** *** 535,540 **** --- 700,718 ---- return indexed_or_indirect_address (op, mode); }) + ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct + ;; moves are supported. + (define_predicate "reg_or_indexed_operand" + (match_code "mem,reg") + { + if (MEM_P (op)) + return indexed_or_indirect_operand (op, mode); + else if (TARGET_DIRECT_MOVE) + return register_operand (op, mode); + return + 0; + }) + ;; Return 1 if the operand is an indexed or indirect memory operand with an ;; AND -16 in it, used to recognize when we need to switch to Altivec loads ;; to realign loops instead of VSX (altivec silently ignores the bottom bits, *************** *** 560,565 **** --- 738,765 ---- && REG_P (XEXP (op, 1)))") (match_operand 0 "address_operand"))) + ;; Return 1 if the operand is an index-form address. + (define_special_predicate "indexed_address" + (match_test "(GET_CODE (op) == PLUS + && REG_P (XEXP (op, 0)) + && REG_P (XEXP (op, 1)))")) + + ;; Return 1 if the operand is a MEM with an update-form address. This may + ;; also include update-indexed form. + (define_special_predicate "update_address_mem" + (match_test "(MEM_P (op) + && (GET_CODE (XEXP (op, 0)) == PRE_INC + || GET_CODE (XEXP (op, 0)) == PRE_DEC + || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))")) + + ;; Return 1 if the operand is a MEM with an update-indexed-form address. Note + ;; that PRE_INC/PRE_DEC will always be non-indexed (i.e. non X-form) since the + ;; increment is based on the mode size and will therefor always be a const. + (define_special_predicate "update_indexed_address_mem" + (match_test "(MEM_P (op) + && GET_CODE (XEXP (op, 0)) == PRE_MODIFY + && indexed_address (XEXP (XEXP (op, 0), 1), mode))")) + ;; Used for the destination of the fix_truncdfsi2 expander. ;; If stfiwx will be used, the result goes to memory; otherwise, ;; we're going to emit a store and a load of a subreg, so the dest is a *************** *** 883,889 **** (and (match_code "symbol_ref") (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) && ((SYMBOL_REF_LOCAL_P (op) ! && (DEFAULT_ABI != ABI_AIX || !SYMBOL_REF_EXTERNAL_P (op))) || (op == XEXP (DECL_RTL (current_function_decl), 0)))"))) --- 1083,1090 ---- (and (match_code "symbol_ref") (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) && ((SYMBOL_REF_LOCAL_P (op) ! && ((DEFAULT_ABI != ABI_AIX ! && DEFAULT_ABI != ABI_ELFv2) || !SYMBOL_REF_EXTERNAL_P (op))) || (op == XEXP (DECL_RTL (current_function_decl), 0)))"))) *************** *** 1364,1369 **** --- 1565,1590 ---- return 1; }) + ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL. + (define_predicate "crsave_operation" + (match_code "parallel") + { + int count = XVECLEN (op, 0); + int i; + + for (i = 1; i < count; i++) + { + rtx exp = XVECEXP (op, 0, i); + + if (GET_CODE (exp) != USE + || GET_CODE (XEXP (exp, 0)) != REG + || GET_MODE (XEXP (exp, 0)) != CCmode + || ! CR_REGNO_P (REGNO (XEXP (exp, 0)))) + return 0; + } + return 1; + }) + ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL. (define_predicate "lmw_operation" (match_code "parallel") *************** *** 1534,1536 **** --- 1755,1853 ---- return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL; }) + + ;; Match the first insn (addis) in fusing the combination of addis and loads to + ;; GPR registers on power8. + (define_predicate "fusion_gpr_addis" + (match_code "const_int,high,plus") + { + HOST_WIDE_INT value; + rtx int_const; + + if (GET_CODE (op) == HIGH) + return 1; + + if (CONST_INT_P (op)) + int_const = op; + + else if (GET_CODE (op) == PLUS + && base_reg_operand (XEXP (op, 0), Pmode) + && CONST_INT_P (XEXP (op, 1))) + int_const = XEXP (op, 1); + + else + return 0; + + /* Power8 currently will only do the fusion if the top 11 bits of the addis + value are all 1's or 0's. */ + value = INTVAL (int_const); + if ((value & (HOST_WIDE_INT)0xffff) != 0) + return 0; + + if ((value & (HOST_WIDE_INT)0xffff0000) == 0) + return 0; + + return (IN_RANGE (value >> 16, -32, 31)); + }) + + ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis + ;; and loads to GPR registers on power8. + (define_predicate "fusion_gpr_mem_load" + (match_code "mem,sign_extend,zero_extend") + { + rtx addr; + + /* Handle sign/zero extend. */ + if (GET_CODE (op) == ZERO_EXTEND + || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND)) + { + op = XEXP (op, 0); + mode = GET_MODE (op); + } + + if (!MEM_P (op)) + return 0; + + switch (mode) + { + case QImode: + case HImode: + case SImode: + break; + + case DImode: + if (!TARGET_POWERPC64) + return 0; + break; + + default: + return 0; + } + + addr = XEXP (op, 0); + if (GET_CODE (addr) == PLUS) + { + rtx base = XEXP (addr, 0); + rtx offset = XEXP (addr, 1); + + return (base_reg_operand (base, GET_MODE (base)) + && satisfies_constraint_I (offset)); + } + + else if (GET_CODE (addr) == LO_SUM) + { + rtx base = XEXP (addr, 0); + rtx offset = XEXP (addr, 1); + + if (!base_reg_operand (base, GET_MODE (base))) + return 0; + + else if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) + return small_toc_ref (offset, GET_MODE (offset)); + + else if (TARGET_ELF && !TARGET_POWERPC64) + return CONSTANT_P (offset); + } + + return 0; + }) diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/rs6000-builtin.def gcc-4.8.3/gcc/config/rs6000/rs6000-builtin.def *** gcc-4.8.2/gcc/config/rs6000/rs6000-builtin.def Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/rs6000/rs6000-builtin.def Mon May 5 02:18:35 2014 *************** *** 30,36 **** RS6000_BUILTIN_A -- ABS builtins RS6000_BUILTIN_D -- DST builtins RS6000_BUILTIN_E -- SPE EVSEL builtins. ! RS6000_BUILTIN_P -- Altivec and VSX predicate builtins RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins RS6000_BUILTIN_S -- SPE predicate builtins RS6000_BUILTIN_X -- special builtins --- 30,37 ---- RS6000_BUILTIN_A -- ABS builtins RS6000_BUILTIN_D -- DST builtins RS6000_BUILTIN_E -- SPE EVSEL builtins. ! RS6000_BUILTIN_H -- HTM builtins ! RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins RS6000_BUILTIN_S -- SPE predicate builtins RS6000_BUILTIN_X -- special builtins *************** *** 66,71 **** --- 67,76 ---- #error "RS6000_BUILTIN_E is not defined." #endif + #ifndef RS6000_BUILTIN_H + #error "RS6000_BUILTIN_H is not defined." + #endif + #ifndef RS6000_BUILTIN_P #error "RS6000_BUILTIN_P is not defined." #endif *************** *** 301,306 **** --- 306,479 ---- | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ + /* ISA 2.07 (power8) vector convenience macros. */ + /* For the instructions that are encoded as altivec instructions use + __builtin_altivec_ as the builtin name. */ + #define BU_P8V_AV_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_P8V_AV_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_P8V_AV_3(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_3 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_P8V_AV_P(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_P (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_PREDICATE), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + /* For the instructions encoded as VSX instructions use __builtin_vsx as the + builtin name. */ + #define BU_P8V_VSX_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_vsx_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_P8V_OVERLOAD_1(ENUM, NAME) \ + RS6000_BUILTIN_1 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ + "__builtin_vec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_nothing) /* ICODE */ + + #define BU_P8V_OVERLOAD_2(ENUM, NAME) \ + RS6000_BUILTIN_2 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ + "__builtin_vec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_nothing) /* ICODE */ + + #define BU_P8V_OVERLOAD_3(ENUM, NAME) \ + RS6000_BUILTIN_3 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ + "__builtin_vec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_nothing) /* ICODE */ + + /* Crypto convenience macros. */ + #define BU_CRYPTO_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_CRYPTO, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_CRYPTO_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_CRYPTO, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_CRYPTO_3(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_CRYPTO, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_CRYPTO_OVERLOAD_1(ENUM, NAME) \ + RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_CRYPTO, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_nothing) /* ICODE */ + + #define BU_CRYPTO_OVERLOAD_2(ENUM, NAME) \ + RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_CRYPTO, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_nothing) /* ICODE */ + + #define BU_CRYPTO_OVERLOAD_3(ENUM, NAME) \ + RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_CRYPTO, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_nothing) /* ICODE */ + + /* HTM convenience macros. */ + #define BU_HTM_0(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HTM, /* MASK */ \ + RS6000_BTC_ ## ATTR, /* ATTR */ \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_HTM_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HTM, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_HTM_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HTM, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_HTM_3(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HTM, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_HTM_SPR0(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HTM, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPR), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_HTM_SPR1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HTM, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY \ + | RS6000_BTC_SPR \ + | RS6000_BTC_VOID), \ + CODE_FOR_ ## ICODE) /* ICODE */ + /* SPE convenience macros. */ #define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ *************** *** 397,402 **** --- 570,644 ---- MASK, /* MASK */ \ (ATTR | RS6000_BTC_SPECIAL), /* ATTR */ \ CODE_FOR_nothing) /* ICODE */ + + + /* Decimal floating point builtins for instructions. */ + #define BU_DFP_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_DFP, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_DFP_MISC_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_DFP, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + + /* Miscellaneous builtins for instructions added in ISA 2.06. These + instructions don't require either the DFP or VSX options, just the basic ISA + 2.06 (popcntd) enablement since they operate on general purpose + registers. */ + #define BU_P7_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_POPCNTD, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_P7_MISC_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_POPCNTD, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + + /* Miscellaneous builtins for instructions added in ISA 2.07. These + instructions do require the ISA 2.07 vector support, but they aren't vector + instructions. */ + #define BU_P8V_MISC_3(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_3 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + /* Miscellaneous builtins. */ + #define BU_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HARD_FLOAT, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + #define BU_MISC_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HARD_FLOAT, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + #endif /* Insure 0 is not a legitimate index. */ *************** BU_ALTIVEC_3 (VMSUMSHM, "vmsumshm" *** 414,425 **** --- 656,669 ---- BU_ALTIVEC_3 (VMSUMUHS, "vmsumuhs", SAT, altivec_vmsumuhs) BU_ALTIVEC_3 (VMSUMSHS, "vmsumshs", SAT, altivec_vmsumshs) BU_ALTIVEC_3 (VNMSUBFP, "vnmsubfp", FP, nfmsv4sf4) + BU_ALTIVEC_3 (VPERM_1TI, "vperm_1ti", CONST, altivec_vperm_v1ti) BU_ALTIVEC_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df) BU_ALTIVEC_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di) BU_ALTIVEC_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf) BU_ALTIVEC_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si) BU_ALTIVEC_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi) BU_ALTIVEC_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi_uns) + BU_ALTIVEC_3 (VPERM_1TI_UNS, "vperm_1ti_uns", CONST, altivec_vperm_v1ti_uns) BU_ALTIVEC_3 (VPERM_2DI_UNS, "vperm_2di_uns", CONST, altivec_vperm_v2di_uns) BU_ALTIVEC_3 (VPERM_4SI_UNS, "vperm_4si_uns", CONST, altivec_vperm_v4si_uns) BU_ALTIVEC_3 (VPERM_8HI_UNS, "vperm_8hi_uns", CONST, altivec_vperm_v8hi_uns) *************** BU_ALTIVEC_3 (VSEL_8HI, "vsel_8hi" *** 430,439 **** --- 674,685 ---- BU_ALTIVEC_3 (VSEL_16QI, "vsel_16qi", CONST, vector_select_v16qi) BU_ALTIVEC_3 (VSEL_2DF, "vsel_2df", CONST, vector_select_v2df) BU_ALTIVEC_3 (VSEL_2DI, "vsel_2di", CONST, vector_select_v2di) + BU_ALTIVEC_3 (VSEL_1TI, "vsel_1ti", CONST, vector_select_v1ti) BU_ALTIVEC_3 (VSEL_4SI_UNS, "vsel_4si_uns", CONST, vector_select_v4si_uns) BU_ALTIVEC_3 (VSEL_8HI_UNS, "vsel_8hi_uns", CONST, vector_select_v8hi_uns) BU_ALTIVEC_3 (VSEL_16QI_UNS, "vsel_16qi_uns", CONST, vector_select_v16qi_uns) BU_ALTIVEC_3 (VSEL_2DI_UNS, "vsel_2di_uns", CONST, vector_select_v2di_uns) + BU_ALTIVEC_3 (VSEL_1TI_UNS, "vsel_1ti_uns", CONST, vector_select_v1ti_uns) BU_ALTIVEC_3 (VSLDOI_16QI, "vsldoi_16qi", CONST, altivec_vsldoi_v16qi) BU_ALTIVEC_3 (VSLDOI_8HI, "vsldoi_8hi", CONST, altivec_vsldoi_v8hi) BU_ALTIVEC_3 (VSLDOI_4SI, "vsldoi_4si", CONST, altivec_vsldoi_v4si) *************** BU_ALTIVEC_X (ST_INTERNAL_2df, "st_inter *** 626,631 **** --- 872,879 ---- BU_ALTIVEC_X (LD_INTERNAL_2df, "ld_internal_2df", MEM) BU_ALTIVEC_X (ST_INTERNAL_2di, "st_internal_2di", MEM) BU_ALTIVEC_X (LD_INTERNAL_2di, "ld_internal_2di", MEM) + BU_ALTIVEC_X (ST_INTERNAL_1ti, "st_internal_1ti", MEM) + BU_ALTIVEC_X (LD_INTERNAL_1ti, "ld_internal_1ti", MEM) BU_ALTIVEC_X (MTVSCR, "mtvscr", MISC) BU_ALTIVEC_X (MFVSCR, "mfvscr", MISC) BU_ALTIVEC_X (DSSALL, "dssall", MISC) *************** BU_ALTIVEC_X (LVEBX, "lvebx", MEM) *** 636,643 **** --- 884,909 ---- BU_ALTIVEC_X (LVEHX, "lvehx", MEM) BU_ALTIVEC_X (LVEWX, "lvewx", MEM) BU_ALTIVEC_X (LVXL, "lvxl", MEM) + BU_ALTIVEC_X (LVXL_V2DF, "lvxl_v2df", MEM) + BU_ALTIVEC_X (LVXL_V2DI, "lvxl_v2di", MEM) + BU_ALTIVEC_X (LVXL_V4SF, "lvxl_v4sf", MEM) + BU_ALTIVEC_X (LVXL_V4SI, "lvxl_v4si", MEM) + BU_ALTIVEC_X (LVXL_V8HI, "lvxl_v8hi", MEM) + BU_ALTIVEC_X (LVXL_V16QI, "lvxl_v16qi", MEM) BU_ALTIVEC_X (LVX, "lvx", MEM) + BU_ALTIVEC_X (LVX_V2DF, "lvx_v2df", MEM) + BU_ALTIVEC_X (LVX_V2DI, "lvx_v2di", MEM) + BU_ALTIVEC_X (LVX_V4SF, "lvx_v4sf", MEM) + BU_ALTIVEC_X (LVX_V4SI, "lvx_v4si", MEM) + BU_ALTIVEC_X (LVX_V8HI, "lvx_v8hi", MEM) + BU_ALTIVEC_X (LVX_V16QI, "lvx_v16qi", MEM) BU_ALTIVEC_X (STVX, "stvx", MEM) + BU_ALTIVEC_X (STVX_V2DF, "stvx_v2df", MEM) + BU_ALTIVEC_X (STVX_V2DI, "stvx_v2di", MEM) + BU_ALTIVEC_X (STVX_V4SF, "stvx_v4sf", MEM) + BU_ALTIVEC_X (STVX_V4SI, "stvx_v4si", MEM) + BU_ALTIVEC_X (STVX_V8HI, "stvx_v8hi", MEM) + BU_ALTIVEC_X (STVX_V16QI, "stvx_v16qi", MEM) BU_ALTIVEC_C (LVLX, "lvlx", MEM) BU_ALTIVEC_C (LVLXL, "lvlxl", MEM) BU_ALTIVEC_C (LVRX, "lvrx", MEM) *************** BU_ALTIVEC_X (STVEBX, "stvebx", MEM *** 646,651 **** --- 912,923 ---- BU_ALTIVEC_X (STVEHX, "stvehx", MEM) BU_ALTIVEC_X (STVEWX, "stvewx", MEM) BU_ALTIVEC_X (STVXL, "stvxl", MEM) + BU_ALTIVEC_X (STVXL_V2DF, "stvxl_v2df", MEM) + BU_ALTIVEC_X (STVXL_V2DI, "stvxl_v2di", MEM) + BU_ALTIVEC_X (STVXL_V4SF, "stvxl_v4sf", MEM) + BU_ALTIVEC_X (STVXL_V4SI, "stvxl_v4si", MEM) + BU_ALTIVEC_X (STVXL_V8HI, "stvxl_v8hi", MEM) + BU_ALTIVEC_X (STVXL_V16QI, "stvxl_v16qi", MEM) BU_ALTIVEC_C (STVLX, "stvlx", MEM) BU_ALTIVEC_C (STVLXL, "stvlxl", MEM) BU_ALTIVEC_C (STVRX, "stvrx", MEM) *************** BU_VSX_3 (XVMSUBDP, "xvmsubdp" *** 904,937 **** --- 1176,1215 ---- BU_VSX_3 (XVNMADDDP, "xvnmadddp", CONST, nfmav2df4) BU_VSX_3 (XVNMSUBDP, "xvnmsubdp", CONST, nfmsv2df4) + BU_VSX_3 (XXSEL_1TI, "xxsel_1ti", CONST, vector_select_v1ti) BU_VSX_3 (XXSEL_2DI, "xxsel_2di", CONST, vector_select_v2di) BU_VSX_3 (XXSEL_2DF, "xxsel_2df", CONST, vector_select_v2df) BU_VSX_3 (XXSEL_4SF, "xxsel_4sf", CONST, vector_select_v4sf) BU_VSX_3 (XXSEL_4SI, "xxsel_4si", CONST, vector_select_v4si) BU_VSX_3 (XXSEL_8HI, "xxsel_8hi", CONST, vector_select_v8hi) BU_VSX_3 (XXSEL_16QI, "xxsel_16qi", CONST, vector_select_v16qi) + BU_VSX_3 (XXSEL_1TI_UNS, "xxsel_1ti_uns", CONST, vector_select_v1ti_uns) BU_VSX_3 (XXSEL_2DI_UNS, "xxsel_2di_uns", CONST, vector_select_v2di_uns) BU_VSX_3 (XXSEL_4SI_UNS, "xxsel_4si_uns", CONST, vector_select_v4si_uns) BU_VSX_3 (XXSEL_8HI_UNS, "xxsel_8hi_uns", CONST, vector_select_v8hi_uns) BU_VSX_3 (XXSEL_16QI_UNS, "xxsel_16qi_uns", CONST, vector_select_v16qi_uns) + BU_VSX_3 (VPERM_1TI, "vperm_1ti", CONST, altivec_vperm_v1ti) BU_VSX_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di) BU_VSX_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df) BU_VSX_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf) BU_VSX_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si) BU_VSX_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi) BU_VSX_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi) + BU_VSX_3 (VPERM_1TI_UNS, "vperm_1ti_uns", CONST, altivec_vperm_v1ti_uns) BU_VSX_3 (VPERM_2DI_UNS, "vperm_2di_uns", CONST, altivec_vperm_v2di_uns) BU_VSX_3 (VPERM_4SI_UNS, "vperm_4si_uns", CONST, altivec_vperm_v4si_uns) BU_VSX_3 (VPERM_8HI_UNS, "vperm_8hi_uns", CONST, altivec_vperm_v8hi_uns) BU_VSX_3 (VPERM_16QI_UNS, "vperm_16qi_uns", CONST, altivec_vperm_v16qi_uns) + BU_VSX_3 (XXPERMDI_1TI, "xxpermdi_1ti", CONST, vsx_xxpermdi_v1ti) BU_VSX_3 (XXPERMDI_2DF, "xxpermdi_2df", CONST, vsx_xxpermdi_v2df) BU_VSX_3 (XXPERMDI_2DI, "xxpermdi_2di", CONST, vsx_xxpermdi_v2di) BU_VSX_3 (XXPERMDI_4SF, "xxpermdi_4sf", CONST, vsx_xxpermdi_v4sf) BU_VSX_3 (XXPERMDI_4SI, "xxpermdi_4si", CONST, vsx_xxpermdi_v4si) BU_VSX_3 (XXPERMDI_8HI, "xxpermdi_8hi", CONST, vsx_xxpermdi_v8hi) BU_VSX_3 (XXPERMDI_16QI, "xxpermdi_16qi", CONST, vsx_xxpermdi_v16qi) + BU_VSX_3 (SET_1TI, "set_1ti", CONST, vsx_set_v1ti) BU_VSX_3 (SET_2DF, "set_2df", CONST, vsx_set_v2df) BU_VSX_3 (SET_2DI, "set_2di", CONST, vsx_set_v2di) BU_VSX_3 (XXSLDWI_2DI, "xxsldwi_2di", CONST, vsx_xxsldwi_v2di) *************** BU_VSX_1 (XVTSQRTSP_FG, "xvtsqrtsp *** 1012,1018 **** BU_VSX_1 (XVRESP, "xvresp", CONST, vsx_frev4sf2) BU_VSX_1 (XSCVDPSP, "xscvdpsp", CONST, vsx_xscvdpsp) ! BU_VSX_1 (XSCVSPDP, "xscvspdp", CONST, vsx_xscvdpsp) BU_VSX_1 (XVCVDPSP, "xvcvdpsp", CONST, vsx_xvcvdpsp) BU_VSX_1 (XVCVSPDP, "xvcvspdp", CONST, vsx_xvcvspdp) BU_VSX_1 (XSTSQRTDP_FE, "xstsqrtdp_fe", CONST, vsx_tsqrtdf2_fe) --- 1290,1296 ---- BU_VSX_1 (XVRESP, "xvresp", CONST, vsx_frev4sf2) BU_VSX_1 (XSCVDPSP, "xscvdpsp", CONST, vsx_xscvdpsp) ! BU_VSX_1 (XSCVSPDP, "xscvspdp", CONST, vsx_xscvspdp) BU_VSX_1 (XVCVDPSP, "xvcvdpsp", CONST, vsx_xvcvdpsp) BU_VSX_1 (XVCVSPDP, "xvcvspdp", CONST, vsx_xvcvspdp) BU_VSX_1 (XSTSQRTDP_FE, "xstsqrtdp_fe", CONST, vsx_tsqrtdf2_fe) *************** BU_VSX_1 (XVRSPIZ, "xvrspiz", CONS *** 1052,1060 **** BU_VSX_1 (XSRDPI, "xsrdpi", CONST, vsx_xsrdpi) BU_VSX_1 (XSRDPIC, "xsrdpic", CONST, vsx_xsrdpic) ! BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, vsx_floordf2) ! BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, vsx_ceildf2) ! BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, vsx_btruncdf2) /* VSX predicate functions. */ BU_VSX_P (XVCMPEQSP_P, "xvcmpeqsp_p", CONST, vector_eq_v4sf_p) --- 1330,1338 ---- BU_VSX_1 (XSRDPI, "xsrdpi", CONST, vsx_xsrdpi) BU_VSX_1 (XSRDPIC, "xsrdpic", CONST, vsx_xsrdpic) ! BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, floordf2) ! BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, ceildf2) ! BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, btruncdf2) /* VSX predicate functions. */ BU_VSX_P (XVCMPEQSP_P, "xvcmpeqsp_p", CONST, vector_eq_v4sf_p) *************** BU_VSX_P (XVCMPGTDP_P, "xvcmpgtdp_ *** 1066,1071 **** --- 1344,1350 ---- /* VSX builtins that are handled as special cases. */ BU_VSX_X (LXSDX, "lxsdx", MEM) + BU_VSX_X (LXVD2X_V1TI, "lxvd2x_v1ti", MEM) BU_VSX_X (LXVD2X_V2DF, "lxvd2x_v2df", MEM) BU_VSX_X (LXVD2X_V2DI, "lxvd2x_v2di", MEM) BU_VSX_X (LXVDSX, "lxvdsx", MEM) *************** BU_VSX_X (LXVW4X_V4SI, "lxvw4x_v4 *** 1074,1079 **** --- 1353,1359 ---- BU_VSX_X (LXVW4X_V8HI, "lxvw4x_v8hi", MEM) BU_VSX_X (LXVW4X_V16QI, "lxvw4x_v16qi", MEM) BU_VSX_X (STXSDX, "stxsdx", MEM) + BU_VSX_X (STXVD2X_V1TI, "stxsdx_v1ti", MEM) BU_VSX_X (STXVD2X_V2DF, "stxsdx_v2df", MEM) BU_VSX_X (STXVD2X_V2DI, "stxsdx_v2di", MEM) BU_VSX_X (STXVW4X_V4SF, "stxsdx_v4sf", MEM) *************** BU_VSX_X (XSNMADDMDP, "xsnmaddmdp" *** 1104,1113 **** --- 1384,1396 ---- BU_VSX_X (XSNMSUBADP, "xsnmsubadp", FP) BU_VSX_X (XSNMSUBMDP, "xsnmsubmdp", FP) BU_VSX_X (XSSUBDP, "xssubdp", FP) + BU_VSX_X (VEC_INIT_V1TI, "vec_init_v1ti", CONST) BU_VSX_X (VEC_INIT_V2DF, "vec_init_v2df", CONST) BU_VSX_X (VEC_INIT_V2DI, "vec_init_v2di", CONST) + BU_VSX_X (VEC_SET_V1TI, "vec_set_v1ti", CONST) BU_VSX_X (VEC_SET_V2DF, "vec_set_v2df", CONST) BU_VSX_X (VEC_SET_V2DI, "vec_set_v2di", CONST) + BU_VSX_X (VEC_EXT_V1TI, "vec_ext_v1ti", CONST) BU_VSX_X (VEC_EXT_V2DF, "vec_ext_v2df", CONST) BU_VSX_X (VEC_EXT_V2DI, "vec_ext_v2di", CONST) *************** BU_VSX_OVERLOAD_2 (XXSPLTW, "xxspltw") *** 1132,1137 **** --- 1415,1663 ---- BU_VSX_OVERLOAD_X (LD, "ld") BU_VSX_OVERLOAD_X (ST, "st") + /* 1 argument VSX instructions added in ISA 2.07. */ + BU_P8V_VSX_1 (XSCVSPDPN, "xscvspdpn", CONST, vsx_xscvspdpn) + BU_P8V_VSX_1 (XSCVDPSPN, "xscvdpspn", CONST, vsx_xscvdpspn) + + /* 1 argument altivec instructions added in ISA 2.07. */ + BU_P8V_AV_1 (ABS_V2DI, "abs_v2di", CONST, absv2di2) + BU_P8V_AV_1 (VUPKHSW, "vupkhsw", CONST, altivec_vupkhsw) + BU_P8V_AV_1 (VUPKLSW, "vupklsw", CONST, altivec_vupklsw) + BU_P8V_AV_1 (VCLZB, "vclzb", CONST, clzv16qi2) + BU_P8V_AV_1 (VCLZH, "vclzh", CONST, clzv8hi2) + BU_P8V_AV_1 (VCLZW, "vclzw", CONST, clzv4si2) + BU_P8V_AV_1 (VCLZD, "vclzd", CONST, clzv2di2) + BU_P8V_AV_1 (VPOPCNTB, "vpopcntb", CONST, popcountv16qi2) + BU_P8V_AV_1 (VPOPCNTH, "vpopcnth", CONST, popcountv8hi2) + BU_P8V_AV_1 (VPOPCNTW, "vpopcntw", CONST, popcountv4si2) + BU_P8V_AV_1 (VPOPCNTD, "vpopcntd", CONST, popcountv2di2) + BU_P8V_AV_1 (VGBBD, "vgbbd", CONST, p8v_vgbbd) + + /* 2 argument altivec instructions added in ISA 2.07. */ + BU_P8V_AV_2 (VADDCUQ, "vaddcuq", CONST, altivec_vaddcuq) + BU_P8V_AV_2 (VADDUDM, "vaddudm", CONST, addv2di3) + BU_P8V_AV_2 (VADDUQM, "vadduqm", CONST, altivec_vadduqm) + BU_P8V_AV_2 (VMINSD, "vminsd", CONST, sminv2di3) + BU_P8V_AV_2 (VMAXSD, "vmaxsd", CONST, smaxv2di3) + BU_P8V_AV_2 (VMINUD, "vminud", CONST, uminv2di3) + BU_P8V_AV_2 (VMAXUD, "vmaxud", CONST, umaxv2di3) + BU_P8V_AV_2 (VMRGEW, "vmrgew", CONST, p8_vmrgew) + BU_P8V_AV_2 (VMRGOW, "vmrgow", CONST, p8_vmrgow) + BU_P8V_AV_2 (VBPERMQ, "vbpermq", CONST, altivec_vbpermq) + BU_P8V_AV_2 (VPKUDUM, "vpkudum", CONST, altivec_vpkudum) + BU_P8V_AV_2 (VPKSDSS, "vpksdss", CONST, altivec_vpksdss) + BU_P8V_AV_2 (VPKUDUS, "vpkudus", CONST, altivec_vpkudus) + BU_P8V_AV_2 (VPKSDUS, "vpksdus", CONST, altivec_vpksdus) + BU_P8V_AV_2 (VRLD, "vrld", CONST, vrotlv2di3) + BU_P8V_AV_2 (VSLD, "vsld", CONST, vashlv2di3) + BU_P8V_AV_2 (VSRD, "vsrd", CONST, vlshrv2di3) + BU_P8V_AV_2 (VSRAD, "vsrad", CONST, vashrv2di3) + BU_P8V_AV_2 (VSUBCUQ, "vsubcuq", CONST, altivec_vsubcuq) + BU_P8V_AV_2 (VSUBUDM, "vsubudm", CONST, subv2di3) + BU_P8V_AV_2 (VSUBUQM, "vsubuqm", CONST, altivec_vsubuqm) + + BU_P8V_AV_2 (EQV_V16QI, "eqv_v16qi", CONST, eqvv16qi3) + BU_P8V_AV_2 (EQV_V8HI, "eqv_v8hi", CONST, eqvv8hi3) + BU_P8V_AV_2 (EQV_V4SI, "eqv_v4si", CONST, eqvv4si3) + BU_P8V_AV_2 (EQV_V2DI, "eqv_v2di", CONST, eqvv2di3) + BU_P8V_AV_2 (EQV_V1TI, "eqv_v1ti", CONST, eqvv1ti3) + BU_P8V_AV_2 (EQV_V4SF, "eqv_v4sf", CONST, eqvv4sf3) + BU_P8V_AV_2 (EQV_V2DF, "eqv_v2df", CONST, eqvv2df3) + + BU_P8V_AV_2 (NAND_V16QI, "nand_v16qi", CONST, nandv16qi3) + BU_P8V_AV_2 (NAND_V8HI, "nand_v8hi", CONST, nandv8hi3) + BU_P8V_AV_2 (NAND_V4SI, "nand_v4si", CONST, nandv4si3) + BU_P8V_AV_2 (NAND_V2DI, "nand_v2di", CONST, nandv2di3) + BU_P8V_AV_2 (NAND_V1TI, "nand_v1ti", CONST, nandv1ti3) + BU_P8V_AV_2 (NAND_V4SF, "nand_v4sf", CONST, nandv4sf3) + BU_P8V_AV_2 (NAND_V2DF, "nand_v2df", CONST, nandv2df3) + + BU_P8V_AV_2 (ORC_V16QI, "orc_v16qi", CONST, orcv16qi3) + BU_P8V_AV_2 (ORC_V8HI, "orc_v8hi", CONST, orcv8hi3) + BU_P8V_AV_2 (ORC_V4SI, "orc_v4si", CONST, orcv4si3) + BU_P8V_AV_2 (ORC_V2DI, "orc_v2di", CONST, orcv2di3) + BU_P8V_AV_2 (ORC_V1TI, "orc_v1ti", CONST, orcv1ti3) + BU_P8V_AV_2 (ORC_V4SF, "orc_v4sf", CONST, orcv4sf3) + BU_P8V_AV_2 (ORC_V2DF, "orc_v2df", CONST, orcv2df3) + + /* 3 argument altivec instructions added in ISA 2.07. */ + BU_P8V_AV_3 (VADDEUQM, "vaddeuqm", CONST, altivec_vaddeuqm) + BU_P8V_AV_3 (VADDECUQ, "vaddecuq", CONST, altivec_vaddecuq) + BU_P8V_AV_3 (VSUBEUQM, "vsubeuqm", CONST, altivec_vsubeuqm) + BU_P8V_AV_3 (VSUBECUQ, "vsubecuq", CONST, altivec_vsubecuq) + + /* Vector comparison instructions added in ISA 2.07. */ + BU_P8V_AV_2 (VCMPEQUD, "vcmpequd", CONST, vector_eqv2di) + BU_P8V_AV_2 (VCMPGTSD, "vcmpgtsd", CONST, vector_gtv2di) + BU_P8V_AV_2 (VCMPGTUD, "vcmpgtud", CONST, vector_gtuv2di) + + /* Vector comparison predicate instructions added in ISA 2.07. */ + BU_P8V_AV_P (VCMPEQUD_P, "vcmpequd_p", CONST, vector_eq_v2di_p) + BU_P8V_AV_P (VCMPGTSD_P, "vcmpgtsd_p", CONST, vector_gt_v2di_p) + BU_P8V_AV_P (VCMPGTUD_P, "vcmpgtud_p", CONST, vector_gtu_v2di_p) + + /* ISA 2.07 vector overloaded 1 argument functions. */ + BU_P8V_OVERLOAD_1 (VUPKHSW, "vupkhsw") + BU_P8V_OVERLOAD_1 (VUPKLSW, "vupklsw") + BU_P8V_OVERLOAD_1 (VCLZ, "vclz") + BU_P8V_OVERLOAD_1 (VCLZB, "vclzb") + BU_P8V_OVERLOAD_1 (VCLZH, "vclzh") + BU_P8V_OVERLOAD_1 (VCLZW, "vclzw") + BU_P8V_OVERLOAD_1 (VCLZD, "vclzd") + BU_P8V_OVERLOAD_1 (VPOPCNT, "vpopcnt") + BU_P8V_OVERLOAD_1 (VPOPCNTB, "vpopcntb") + BU_P8V_OVERLOAD_1 (VPOPCNTH, "vpopcnth") + BU_P8V_OVERLOAD_1 (VPOPCNTW, "vpopcntw") + BU_P8V_OVERLOAD_1 (VPOPCNTD, "vpopcntd") + BU_P8V_OVERLOAD_1 (VGBBD, "vgbbd") + + /* ISA 2.07 vector overloaded 2 argument functions. */ + BU_P8V_OVERLOAD_2 (EQV, "eqv") + BU_P8V_OVERLOAD_2 (NAND, "nand") + BU_P8V_OVERLOAD_2 (ORC, "orc") + BU_P8V_OVERLOAD_2 (VADDCUQ, "vaddcuq") + BU_P8V_OVERLOAD_2 (VADDUDM, "vaddudm") + BU_P8V_OVERLOAD_2 (VADDUQM, "vadduqm") + BU_P8V_OVERLOAD_2 (VBPERMQ, "vbpermq") + BU_P8V_OVERLOAD_2 (VMAXSD, "vmaxsd") + BU_P8V_OVERLOAD_2 (VMAXUD, "vmaxud") + BU_P8V_OVERLOAD_2 (VMINSD, "vminsd") + BU_P8V_OVERLOAD_2 (VMINUD, "vminud") + BU_P8V_OVERLOAD_2 (VMRGEW, "vmrgew") + BU_P8V_OVERLOAD_2 (VMRGOW, "vmrgow") + BU_P8V_OVERLOAD_2 (VPKSDSS, "vpksdss") + BU_P8V_OVERLOAD_2 (VPKSDUS, "vpksdus") + BU_P8V_OVERLOAD_2 (VPKUDUM, "vpkudum") + BU_P8V_OVERLOAD_2 (VPKUDUS, "vpkudus") + BU_P8V_OVERLOAD_2 (VRLD, "vrld") + BU_P8V_OVERLOAD_2 (VSLD, "vsld") + BU_P8V_OVERLOAD_2 (VSRAD, "vsrad") + BU_P8V_OVERLOAD_2 (VSRD, "vsrd") + BU_P8V_OVERLOAD_2 (VSUBCUQ, "vsubcuq") + BU_P8V_OVERLOAD_2 (VSUBUDM, "vsubudm") + BU_P8V_OVERLOAD_2 (VSUBUQM, "vsubuqm") + + /* ISA 2.07 vector overloaded 3 argument functions. */ + BU_P8V_OVERLOAD_3 (VADDECUQ, "vaddecuq") + BU_P8V_OVERLOAD_3 (VADDEUQM, "vaddeuqm") + BU_P8V_OVERLOAD_3 (VSUBECUQ, "vsubecuq") + BU_P8V_OVERLOAD_3 (VSUBEUQM, "vsubeuqm") + + + /* 2 argument extended divide functions added in ISA 2.06. */ + BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si) + BU_P7_MISC_2 (DIVWEO, "divweo", CONST, diveo_si) + BU_P7_MISC_2 (DIVWEU, "divweu", CONST, diveu_si) + BU_P7_MISC_2 (DIVWEUO, "divweuo", CONST, diveuo_si) + BU_P7_MISC_2 (DIVDE, "divde", CONST, dive_di) + BU_P7_MISC_2 (DIVDEO, "divdeo", CONST, diveo_di) + BU_P7_MISC_2 (DIVDEU, "divdeu", CONST, diveu_di) + BU_P7_MISC_2 (DIVDEUO, "divdeuo", CONST, diveuo_di) + + /* 1 argument DFP (decimal floating point) functions added in ISA 2.05. */ + BU_DFP_MISC_1 (DXEX, "dxex", CONST, dfp_dxex_dd) + BU_DFP_MISC_1 (DXEXQ, "dxexq", CONST, dfp_dxex_td) + + /* 2 argument DFP (decimal floating point) functions added in ISA 2.05. */ + BU_DFP_MISC_2 (DDEDPD, "ddedpd", CONST, dfp_ddedpd_dd) + BU_DFP_MISC_2 (DDEDPDQ, "ddedpdq", CONST, dfp_ddedpd_td) + BU_DFP_MISC_2 (DENBCD, "denbcd", CONST, dfp_denbcd_dd) + BU_DFP_MISC_2 (DENBCDQ, "denbcdq", CONST, dfp_denbcd_td) + BU_DFP_MISC_2 (DIEX, "diex", CONST, dfp_diex_dd) + BU_DFP_MISC_2 (DIEXQ, "diexq", CONST, dfp_diex_td) + BU_DFP_MISC_2 (DSCLI, "dscli", CONST, dfp_dscli_dd) + BU_DFP_MISC_2 (DSCLIQ, "dscliq", CONST, dfp_dscli_td) + BU_DFP_MISC_2 (DSCRI, "dscri", CONST, dfp_dscri_dd) + BU_DFP_MISC_2 (DSCRIQ, "dscriq", CONST, dfp_dscri_td) + + /* 1 argument BCD functions added in ISA 2.06. */ + BU_P7_MISC_1 (CDTBCD, "cdtbcd", CONST, cdtbcd) + BU_P7_MISC_1 (CBCDTD, "cbcdtd", CONST, cbcdtd) + + /* 2 argument BCD functions added in ISA 2.06. */ + BU_P7_MISC_2 (ADDG6S, "addg6s", CONST, addg6s) + + /* 3 argument BCD functions added in ISA 2.07. */ + BU_P8V_MISC_3 (BCDADD, "bcdadd", CONST, bcdadd) + BU_P8V_MISC_3 (BCDADD_LT, "bcdadd_lt", CONST, bcdadd_lt) + BU_P8V_MISC_3 (BCDADD_EQ, "bcdadd_eq", CONST, bcdadd_eq) + BU_P8V_MISC_3 (BCDADD_GT, "bcdadd_gt", CONST, bcdadd_gt) + BU_P8V_MISC_3 (BCDADD_OV, "bcdadd_ov", CONST, bcdadd_unordered) + BU_P8V_MISC_3 (BCDSUB, "bcdsub", CONST, bcdsub) + BU_P8V_MISC_3 (BCDSUB_LT, "bcdsub_lt", CONST, bcdsub_lt) + BU_P8V_MISC_3 (BCDSUB_EQ, "bcdsub_eq", CONST, bcdsub_eq) + BU_P8V_MISC_3 (BCDSUB_GT, "bcdsub_gt", CONST, bcdsub_gt) + BU_P8V_MISC_3 (BCDSUB_OV, "bcdsub_ov", CONST, bcdsub_unordered) + + /* 2 argument pack/unpack 128-bit floating point types. */ + BU_DFP_MISC_2 (PACK_TD, "pack_dec128", CONST, packtd) + BU_DFP_MISC_2 (UNPACK_TD, "unpack_dec128", CONST, unpacktd) + + BU_MISC_2 (PACK_TF, "pack_longdouble", CONST, packtf) + BU_MISC_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf) + BU_MISC_1 (UNPACK_TF_0, "longdouble_dw0", CONST, unpacktf_0) + BU_MISC_1 (UNPACK_TF_1, "longdouble_dw1", CONST, unpacktf_1) + + BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti) + BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti) + + + /* 1 argument crypto functions. */ + BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox) + + /* 2 argument crypto functions. */ + BU_CRYPTO_2 (VCIPHER, "vcipher", CONST, crypto_vcipher) + BU_CRYPTO_2 (VCIPHERLAST, "vcipherlast", CONST, crypto_vcipherlast) + BU_CRYPTO_2 (VNCIPHER, "vncipher", CONST, crypto_vncipher) + BU_CRYPTO_2 (VNCIPHERLAST, "vncipherlast", CONST, crypto_vncipherlast) + BU_CRYPTO_2 (VPMSUMB, "vpmsumb", CONST, crypto_vpmsumb) + BU_CRYPTO_2 (VPMSUMH, "vpmsumh", CONST, crypto_vpmsumh) + BU_CRYPTO_2 (VPMSUMW, "vpmsumw", CONST, crypto_vpmsumw) + BU_CRYPTO_2 (VPMSUMD, "vpmsumd", CONST, crypto_vpmsumd) + + /* 3 argument crypto functions. */ + BU_CRYPTO_3 (VPERMXOR_V2DI, "vpermxor_v2di", CONST, crypto_vpermxor_v2di) + BU_CRYPTO_3 (VPERMXOR_V4SI, "vpermxor_v4si", CONST, crypto_vpermxor_v4si) + BU_CRYPTO_3 (VPERMXOR_V8HI, "vpermxor_v8hi", CONST, crypto_vpermxor_v8hi) + BU_CRYPTO_3 (VPERMXOR_V16QI, "vpermxor_v16qi", CONST, crypto_vpermxor_v16qi) + BU_CRYPTO_3 (VSHASIGMAW, "vshasigmaw", CONST, crypto_vshasigmaw) + BU_CRYPTO_3 (VSHASIGMAD, "vshasigmad", CONST, crypto_vshasigmad) + + /* 2 argument crypto overloaded functions. */ + BU_CRYPTO_OVERLOAD_2 (VPMSUM, "vpmsum") + + /* 3 argument crypto overloaded functions. */ + BU_CRYPTO_OVERLOAD_3 (VPERMXOR, "vpermxor") + BU_CRYPTO_OVERLOAD_3 (VSHASIGMA, "vshasigma") + + + /* HTM functions. */ + BU_HTM_1 (TABORT, "tabort", MISC, tabort) + BU_HTM_3 (TABORTDC, "tabortdc", MISC, tabortdc) + BU_HTM_3 (TABORTDCI, "tabortdci", MISC, tabortdci) + BU_HTM_3 (TABORTWC, "tabortwc", MISC, tabortwc) + BU_HTM_3 (TABORTWCI, "tabortwci", MISC, tabortwci) + BU_HTM_1 (TBEGIN, "tbegin", MISC, tbegin) + BU_HTM_1 (TCHECK, "tcheck", MISC, tcheck) + BU_HTM_1 (TEND, "tend", MISC, tend) + BU_HTM_0 (TENDALL, "tendall", MISC, tend) + BU_HTM_0 (TRECHKPT, "trechkpt", MISC, trechkpt) + BU_HTM_1 (TRECLAIM, "treclaim", MISC, treclaim) + BU_HTM_0 (TRESUME, "tresume", MISC, tsr) + BU_HTM_0 (TSUSPEND, "tsuspend", MISC, tsr) + BU_HTM_1 (TSR, "tsr", MISC, tsr) + BU_HTM_0 (TTEST, "ttest", MISC, ttest) + + BU_HTM_SPR0 (GET_TFHAR, "get_tfhar", MISC, nothing) + BU_HTM_SPR1 (SET_TFHAR, "set_tfhar", MISC, nothing) + BU_HTM_SPR0 (GET_TFIAR, "get_tfiar", MISC, nothing) + BU_HTM_SPR1 (SET_TFIAR, "set_tfiar", MISC, nothing) + BU_HTM_SPR0 (GET_TEXASR, "get_texasr", MISC, nothing) + BU_HTM_SPR1 (SET_TEXASR, "set_texasr", MISC, nothing) + BU_HTM_SPR0 (GET_TEXASRU, "get_texasru", MISC, nothing) + BU_HTM_SPR1 (SET_TEXASRU, "set_texasru", MISC, nothing) + + /* 3 argument paired floating point builtins. */ BU_PAIRED_3 (MSUB, "msub", FP, fmsv2sf4) BU_PAIRED_3 (MADD, "madd", FP, fmav2sf4) *************** BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__ *** 1430,1439 **** RS6000_BTC_FP) BU_SPECIAL_X (RS6000_BUILTIN_GET_TB, "__builtin_ppc_get_timebase", ! RS6000_BTM_ALWAYS, RS6000_BTC_MISC) BU_SPECIAL_X (RS6000_BUILTIN_MFTB, "__builtin_ppc_mftb", ! RS6000_BTM_ALWAYS, RS6000_BTC_MISC) /* Darwin CfString builtin. */ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS, --- 1956,1965 ---- RS6000_BTC_FP) BU_SPECIAL_X (RS6000_BUILTIN_GET_TB, "__builtin_ppc_get_timebase", ! RS6000_BTM_ALWAYS, RS6000_BTC_MISC) BU_SPECIAL_X (RS6000_BUILTIN_MFTB, "__builtin_ppc_mftb", ! RS6000_BTM_ALWAYS, RS6000_BTC_MISC) /* Darwin CfString builtin. */ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS, diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/rs6000-c.c gcc-4.8.3/gcc/config/rs6000/rs6000-c.c *** gcc-4.8.2/gcc/config/rs6000/rs6000-c.c Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/rs6000/rs6000-c.c Wed Apr 23 23:16:05 2014 *************** static GTY(()) tree pixel_keyword; *** 90,95 **** --- 90,97 ---- static GTY(()) tree __bool_keyword; static GTY(()) tree bool_keyword; static GTY(()) tree _Bool_keyword; + static GTY(()) tree __int128_type; + static GTY(()) tree __uint128_type; /* Preserved across calls. */ static tree expand_bool_pixel; *************** altivec_categorize_keyword (const cpp_to *** 122,130 **** static void init_vector_keywords (void) { ! /* Keywords without two leading underscores are context-sensitive, ! and hence implemented as conditional macros, controlled by the ! rs6000_macro_to_expand() function below. */ __vector_keyword = get_identifier ("__vector"); C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL; --- 124,133 ---- static void init_vector_keywords (void) { ! /* Keywords without two leading underscores are context-sensitive, and hence ! implemented as conditional macros, controlled by the ! rs6000_macro_to_expand() function below. If we have ISA 2.07 64-bit ! support, record the __int128_t and __uint128_t types. */ __vector_keyword = get_identifier ("__vector"); C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL; *************** init_vector_keywords (void) *** 146,151 **** --- 149,160 ---- _Bool_keyword = get_identifier ("_Bool"); C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL; + + if (TARGET_VADDUQM) + { + __int128_type = get_identifier ("__int128_t"); + __uint128_type = get_identifier ("__uint128_t"); + } } /* Called to decide whether a conditional macro should be expanded. *************** rs6000_macro_to_expand (cpp_reader *pfil *** 221,227 **** || rid_code == RID_SHORT || rid_code == RID_SIGNED || rid_code == RID_INT || rid_code == RID_CHAR || rid_code == RID_FLOAT ! || (rid_code == RID_DOUBLE && TARGET_VSX)) { expand_this = C_CPP_HASHNODE (__vector_keyword); /* If the next keyword is bool or pixel, it --- 230,237 ---- || rid_code == RID_SHORT || rid_code == RID_SIGNED || rid_code == RID_INT || rid_code == RID_CHAR || rid_code == RID_FLOAT ! || (rid_code == RID_DOUBLE && TARGET_VSX) ! || (rid_code == RID_INT128 && TARGET_VADDUQM)) { expand_this = C_CPP_HASHNODE (__vector_keyword); /* If the next keyword is bool or pixel, it *************** rs6000_macro_to_expand (cpp_reader *pfil *** 248,253 **** --- 258,270 ---- expand_bool_pixel = __bool_keyword; } } + + /* Support vector __int128_t, but we don't need to worry about bool + or pixel on this type. */ + else if (TARGET_VADDUQM + && (ident == C_CPP_HASHNODE (__int128_type) + || ident == C_CPP_HASHNODE (__uint128_type))) + expand_this = C_CPP_HASHNODE (__vector_keyword); } } else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword)) *************** rs6000_target_modify_macros (bool define *** 315,320 **** --- 332,339 ---- rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); if ((flags & OPTION_MASK_POPCNTD) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); + if ((flags & OPTION_MASK_DIRECT_MOVE) != 0) + rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) *************** rs6000_target_modify_macros (bool define *** 331,336 **** --- 350,365 ---- } if ((flags & OPTION_MASK_VSX) != 0) rs6000_define_or_undefine_macro (define_p, "__VSX__"); + if ((flags & OPTION_MASK_HTM) != 0) + rs6000_define_or_undefine_macro (define_p, "__HTM__"); + if ((flags & OPTION_MASK_P8_VECTOR) != 0) + rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__"); + if ((flags & OPTION_MASK_QUAD_MEMORY) != 0) + rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__"); + if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0) + rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__"); + if ((flags & OPTION_MASK_CRYPTO) != 0) + rs6000_define_or_undefine_macro (define_p, "__CRYPTO__"); /* options from the builtin masks. */ if ((bu_mask & RS6000_BTM_SPE) != 0) *************** rs6000_cpu_cpp_builtins (cpp_reader *pfi *** 453,458 **** --- 482,491 ---- case ABI_AIX: builtin_define ("_CALL_AIXDESC"); builtin_define ("_CALL_AIX"); + builtin_define ("_CALL_ELF=1"); + break; + case ABI_ELFv2: + builtin_define ("_CALL_ELF=2"); break; case ABI_DARWIN: builtin_define ("_CALL_DARWIN"); *************** rs6000_cpu_cpp_builtins (cpp_reader *pfi *** 465,470 **** --- 498,510 ---- if (TARGET_SOFT_FLOAT || !TARGET_FPRS) builtin_define ("__NO_FPRS__"); + /* Whether aggregates passed by value are aligned to a 16 byte boundary + if their alignment is 16 bytes or larger. */ + if ((TARGET_MACHO && rs6000_darwin64_abi) + || DEFAULT_ABI == ABI_ELFv2 + || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)) + builtin_define ("__STRUCT_PARM_ALIGN__=16"); + /* Generate defines for Xilinx FPU. */ if (rs6000_xilinx_fpu) { *************** const struct altivec_builtin_types altiv *** 505,510 **** --- 545,552 ---- RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP, *************** const struct altivec_builtin_types altiv *** 577,588 **** --- 619,638 ---- RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, *************** const struct altivec_builtin_types altiv *** 601,606 **** --- 651,660 ---- RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, *************** const struct altivec_builtin_types altiv *** 651,660 **** --- 705,731 ---- RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, *************** const struct altivec_builtin_types altiv *** 937,942 **** --- 1008,1017 ---- RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, + RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, + RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP, *************** const struct altivec_builtin_types altiv *** 975,980 **** --- 1050,1059 ---- RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD, + RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD, + RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP, *************** const struct altivec_builtin_types altiv *** 1021,1026 **** --- 1100,1109 ---- RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD, + RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD, + RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP, *************** const struct altivec_builtin_types altiv *** 1045,1098 **** RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V2DI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, --- 1128,1181 ---- RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V2DI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, *************** const struct altivec_builtin_types altiv *** 1130,1184 **** RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V2DI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, --- 1213,1267 ---- RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V2DI, 0 }, ! { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, *************** const struct altivec_builtin_types altiv *** 1418,1423 **** --- 1501,1518 ---- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP, *************** const struct altivec_builtin_types altiv *** 1604,1609 **** --- 1699,1716 ---- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP, *************** const struct altivec_builtin_types altiv *** 1786,1791 **** --- 1893,1904 ---- RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, *************** const struct altivec_builtin_types altiv *** 1812,1817 **** --- 1925,1934 ---- RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS, + RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS, RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS, *************** const struct altivec_builtin_types altiv *** 1824,1829 **** --- 1941,1948 ---- RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS, *************** const struct altivec_builtin_types altiv *** 1844,1849 **** --- 1963,1972 ---- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, *************** const struct altivec_builtin_types altiv *** 1868,1873 **** --- 1991,2000 ---- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP, *************** const struct altivec_builtin_types altiv *** 2032,2037 **** --- 2159,2168 ---- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, *************** const struct altivec_builtin_types altiv *** 2056,2061 **** --- 2187,2196 ---- RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, *************** const struct altivec_builtin_types altiv *** 2196,2205 **** --- 2331,2357 ---- RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, 0 }, { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, *************** const struct altivec_builtin_types altiv *** 2730,2792 **** RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V2DI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, --- 2882,2944 ---- RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V2DI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF, RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF, RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, ! { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, *************** const struct altivec_builtin_types altiv *** 2858,2921 **** RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V2DI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI }, { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, --- 3010,3073 ---- RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF, RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF, RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V2DI }, ! { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI }, { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, *************** const struct altivec_builtin_types altiv *** 3327,3332 **** --- 3479,3498 ---- RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI }, { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P, *************** const struct altivec_builtin_types altiv *** 3372,3382 **** --- 3538,4046 ---- RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, + /* Power8 vector overloaded functions. */ + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_bool_V16QI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_bool_V8HI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_bool_V4SI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_bool_V16QI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_bool_V8HI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_bool_V4SI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_bool_V16QI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_bool_V8HI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_bool_V4SI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + + { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, + { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, 0 }, + + { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, + { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, 0 }, + + { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, + RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + + { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + + { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + + { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + + { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + + { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + + { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, + { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, + + { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, + { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, + + { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, + { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, + + { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, + { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, + + { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + + { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + + { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + + { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + + { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + + { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + + { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS, + RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, + { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, 0 }, + + { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, + { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, 0 }, + + { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, + + { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, + + { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, + RS6000_BTI_V16QI, 0, 0, 0 }, + { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, + RS6000_BTI_unsigned_V16QI, 0, 0, 0 }, + + /* Crypto builtins. */ + { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, + { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, + { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, + { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + + { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + + { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_INTSI, RS6000_BTI_INTSI }, + { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_INTSI, RS6000_BTI_INTSI }, + { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 } }; *************** altivec_resolve_overloaded_builtin (loca *** 3560,3565 **** --- 4224,4233 ---- unsigned_p = TYPE_UNSIGNED (type); switch (TYPE_MODE (type)) { + case TImode: + type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node); + size = 1; + break; case DImode: type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node); size = 2; *************** altivec_resolve_overloaded_builtin (loca *** 3591,3597 **** return build_constructor (type, vec); } ! /* For now use pointer tricks to do the extaction, unless we are on VSX extracting a double from a constant offset. */ if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT) { --- 4259,4265 ---- return build_constructor (type, vec); } ! /* For now use pointer tricks to do the extraction, unless we are on VSX extracting a double from a constant offset. */ if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT) { *************** altivec_resolve_overloaded_builtin (loca *** 3619,3624 **** --- 4287,4303 ---- if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2))) goto bad; + /* If we are targeting little-endian, but -maltivec=be has been + specified to override the element order, adjust the element + number accordingly. */ + if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2) + { + unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1; + arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2), + build_int_cstu (TREE_TYPE (arg2), last_elem), + arg2); + } + /* If we can use the VSX xxpermdi instruction, use that for extract. */ mode = TYPE_MODE (arg1_type); if ((mode == V2DFmode || mode == V2DImode) && VECTOR_MEM_VSX_P (mode) *************** altivec_resolve_overloaded_builtin (loca *** 3636,3641 **** --- 4315,4328 ---- if (call) return build_call_expr (call, 2, arg1, arg2); } + else if (mode == V1TImode && VECTOR_MEM_VSX_P (mode) + && TREE_CODE (arg2) == INTEGER_CST + && TREE_INT_CST_HIGH (arg2) == 0 + && TREE_INT_CST_LOW (arg2) == 0) + { + tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI]; + return build_call_expr (call, 2, arg1, arg2); + } /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */ arg1_inner_type = TREE_TYPE (arg1_type); *************** altivec_resolve_overloaded_builtin (loca *** 3666,3672 **** return stmt; } ! /* For now use pointer tricks to do the insertation, unless we are on VSX inserting a double to a constant offset.. */ if (fcode == ALTIVEC_BUILTIN_VEC_INSERT) { --- 4353,4359 ---- return stmt; } ! /* For now use pointer tricks to do the insertion, unless we are on VSX inserting a double to a constant offset.. */ if (fcode == ALTIVEC_BUILTIN_VEC_INSERT) { *************** altivec_resolve_overloaded_builtin (loca *** 3696,3701 **** --- 4383,4399 ---- if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2))) goto bad; + /* If we are targeting little-endian, but -maltivec=be has been + specified to override the element order, adjust the element + number accordingly. */ + if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2) + { + unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1; + arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2), + build_int_cstu (TREE_TYPE (arg2), last_elem), + arg2); + } + /* If we can use the VSX xxpermdi instruction, use that for insert. */ mode = TYPE_MODE (arg1_type); if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode) *************** altivec_resolve_overloaded_builtin (loca *** 3715,3720 **** --- 4413,4429 ---- if (call) return build_call_expr (call, 3, arg1, arg0, arg2); } + else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode) + && TREE_CODE (arg2) == INTEGER_CST + && TREE_INT_CST_HIGH (arg2) == 0 + && TREE_INT_CST_LOW (arg2) == 0) + { + tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI]; + + /* Note, __builtin_vec_insert_ has vector and scalar types + reversed. */ + return build_call_expr (call, 3, arg1, arg0, arg2); + } /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */ arg1_inner_type = TREE_TYPE (arg1_type); *************** altivec_resolve_overloaded_builtin (loca *** 3824,3830 **** && (desc->op2 == RS6000_BTI_NOT_OPAQUE || rs6000_builtin_type_compatible (types[1], desc->op2)) && (desc->op3 == RS6000_BTI_NOT_OPAQUE ! || rs6000_builtin_type_compatible (types[2], desc->op3))) return altivec_build_resolved_builtin (args, n, desc); bad: --- 4533,4540 ---- && (desc->op2 == RS6000_BTI_NOT_OPAQUE || rs6000_builtin_type_compatible (types[1], desc->op2)) && (desc->op3 == RS6000_BTI_NOT_OPAQUE ! || rs6000_builtin_type_compatible (types[2], desc->op3)) ! && rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE) return altivec_build_resolved_builtin (args, n, desc); bad: diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/rs6000-cpus.def gcc-4.8.3/gcc/config/rs6000/rs6000-cpus.def *** gcc-4.8.2/gcc/config/rs6000/rs6000-cpus.def Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/rs6000/rs6000-cpus.def Fri Apr 4 14:42:18 2014 *************** *** 28,34 **** ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented as optional. Group masks by server and embedded. */ ! #define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \ | OPTION_MASK_CMPB \ | OPTION_MASK_RECIP_PRECISION \ | OPTION_MASK_PPC_GFXOPT \ --- 28,34 ---- ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented as optional. Group masks by server and embedded. */ ! #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \ | OPTION_MASK_CMPB \ | OPTION_MASK_RECIP_PRECISION \ | OPTION_MASK_PPC_GFXOPT \ *************** *** 38,49 **** --- 38,61 ---- /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but altivec is a win so enable it. */ + /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until + PR 58587 is fixed. */ #define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD) #define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \ | OPTION_MASK_POPCNTD \ | OPTION_MASK_ALTIVEC \ | OPTION_MASK_VSX) + /* For now, don't provide an embedded version of ISA 2.07. */ + #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \ + | OPTION_MASK_P8_FUSION \ + | OPTION_MASK_P8_VECTOR \ + | OPTION_MASK_CRYPTO \ + | OPTION_MASK_DIRECT_MOVE \ + | OPTION_MASK_HTM \ + | OPTION_MASK_QUAD_MEMORY \ + | OPTION_MASK_QUAD_MEMORY_ATOMIC) + #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) /* Deal with ports that do not have -mstrict-align. */ *************** *** 60,82 **** /* Mask of all options to set the default isa flags based on -mcpu=. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ | OPTION_MASK_CMPB \ | OPTION_MASK_DFP \ | OPTION_MASK_DLMZB \ | OPTION_MASK_FPRND \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ | OPTION_MASK_MFPGPR \ | OPTION_MASK_MULHW \ | OPTION_MASK_NO_UPDATE \ | OPTION_MASK_POPCNTB \ | OPTION_MASK_POPCNTD \ | OPTION_MASK_POWERPC64 \ | OPTION_MASK_PPC_GFXOPT \ | OPTION_MASK_PPC_GPOPT \ | OPTION_MASK_RECIP_PRECISION \ | OPTION_MASK_SOFT_FLOAT \ | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ ! | OPTION_MASK_VSX) #endif --- 72,101 ---- /* Mask of all options to set the default isa flags based on -mcpu=. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ | OPTION_MASK_CMPB \ + | OPTION_MASK_CRYPTO \ | OPTION_MASK_DFP \ + | OPTION_MASK_DIRECT_MOVE \ | OPTION_MASK_DLMZB \ | OPTION_MASK_FPRND \ + | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ | OPTION_MASK_MFPGPR \ | OPTION_MASK_MULHW \ | OPTION_MASK_NO_UPDATE \ + | OPTION_MASK_P8_FUSION \ + | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_POPCNTB \ | OPTION_MASK_POPCNTD \ | OPTION_MASK_POWERPC64 \ | OPTION_MASK_PPC_GFXOPT \ | OPTION_MASK_PPC_GPOPT \ + | OPTION_MASK_QUAD_MEMORY \ | OPTION_MASK_RECIP_PRECISION \ | OPTION_MASK_SOFT_FLOAT \ | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ ! | OPTION_MASK_VSX \ ! | OPTION_MASK_VSX_TIMODE) #endif *************** RS6000_CPU ("power7", PROCESSOR_POWER7, *** 166,175 **** POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD | MASK_VSX | MASK_RECIP_PRECISION) ! RS6000_CPU ("power8", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */ ! POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF ! | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD ! | MASK_VSX | MASK_RECIP_PRECISION) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) --- 185,191 ---- POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD | MASK_VSX | MASK_RECIP_PRECISION) ! RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/rs6000-modes.def gcc-4.8.3/gcc/config/rs6000/rs6000-modes.def *** gcc-4.8.2/gcc/config/rs6000/rs6000-modes.def Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/rs6000/rs6000-modes.def Fri Apr 4 15:08:45 2014 *************** VECTOR_MODES (INT, 8); /* V *** 38,43 **** --- 38,49 ---- VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ VECTOR_MODE (INT, DI, 1); + VECTOR_MODE (INT, TI, 1); VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ + + /* Replacement for TImode that only is allowed in GPRs. We also use PTImode + for quad memory atomic operations to force getting an even/odd register + combination. */ + PARTIAL_INT_MODE (TI); diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/rs6000-opts.h gcc-4.8.3/gcc/config/rs6000/rs6000-opts.h *** gcc-4.8.2/gcc/config/rs6000/rs6000-opts.h Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/rs6000/rs6000-opts.h Fri Apr 4 14:17:55 2014 *************** enum processor_type *** 59,65 **** PROCESSOR_POWER7, PROCESSOR_CELL, PROCESSOR_PPCA2, ! PROCESSOR_TITAN }; /* FP processor type. */ --- 59,66 ---- PROCESSOR_POWER7, PROCESSOR_CELL, PROCESSOR_PPCA2, ! PROCESSOR_TITAN, ! PROCESSOR_POWER8 }; /* FP processor type. */ *************** enum group_termination *** 100,106 **** /* Enumeration to give which calling sequence to use. */ enum rs6000_abi { ABI_NONE, ! ABI_AIX, /* IBM's AIX */ ABI_V4, /* System V.4/eabi */ ABI_DARWIN /* Apple's Darwin (OS X kernel) */ }; --- 101,108 ---- /* Enumeration to give which calling sequence to use. */ enum rs6000_abi { ABI_NONE, ! ABI_AIX, /* IBM's AIX, or Linux ELFv1 */ ! ABI_ELFv2, /* Linux ELFv2 ABI */ ABI_V4, /* System V.4/eabi */ ABI_DARWIN /* Apple's Darwin (OS X kernel) */ }; *************** enum rs6000_cmodel { *** 131,141 **** CMODEL_LARGE }; ! /* Describe which vector unit to use for a given machine mode. */ enum rs6000_vector { VECTOR_NONE, /* Type is not a vector or not supported */ VECTOR_ALTIVEC, /* Use altivec for vector processing */ VECTOR_VSX, /* Use VSX for vector processing */ VECTOR_PAIRED, /* Use paired floating point for vectors */ VECTOR_SPE, /* Use SPE for vector processing */ VECTOR_OTHER /* Some other vector unit */ --- 133,146 ---- CMODEL_LARGE }; ! /* Describe which vector unit to use for a given machine mode. The ! VECTOR_MEM_* and VECTOR_UNIT_* macros assume that Altivec, VSX, and ! P8_VECTOR are contiguous. */ enum rs6000_vector { VECTOR_NONE, /* Type is not a vector or not supported */ VECTOR_ALTIVEC, /* Use altivec for vector processing */ VECTOR_VSX, /* Use VSX for vector processing */ + VECTOR_P8_VECTOR, /* Use ISA 2.07 VSX for vector processing */ VECTOR_PAIRED, /* Use paired floating point for vectors */ VECTOR_SPE, /* Use SPE for vector processing */ VECTOR_OTHER /* Some other vector unit */ diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/rs6000-protos.h gcc-4.8.3/gcc/config/rs6000/rs6000-protos.h *** gcc-4.8.2/gcc/config/rs6000/rs6000-protos.h Thu Jan 10 20:38:27 2013 --- gcc-4.8.3/gcc/config/rs6000/rs6000-protos.h Fri Apr 4 15:10:24 2014 *************** extern rtx rs6000_got_register (rtx); *** 50,61 **** --- 50,68 ---- extern rtx find_addr_reg (rtx); extern rtx gen_easy_altivec_constant (rtx); extern const char *output_vec_const_move (rtx *); + extern const char *rs6000_output_move_128bit (rtx *); + extern bool rs6000_move_128bit_ok_p (rtx []); + extern bool rs6000_split_128bit_ok_p (rtx []); extern void rs6000_expand_vector_init (rtx, rtx); extern void paired_expand_vector_init (rtx, rtx); extern void rs6000_expand_vector_set (rtx, rtx, int); extern void rs6000_expand_vector_extract (rtx, rtx, int); extern bool altivec_expand_vec_perm_const (rtx op[4]); + extern void altivec_expand_vec_perm_le (rtx op[4]); extern bool rs6000_expand_vec_perm_const (rtx op[4]); + extern void altivec_expand_lvx_be (rtx, rtx, enum machine_mode, unsigned); + extern void altivec_expand_stvx_be (rtx, rtx, enum machine_mode, unsigned); + extern void altivec_expand_stvex_be (rtx, rtx, enum machine_mode, unsigned); extern void rs6000_expand_extract_even (rtx, rtx, rtx); extern void rs6000_expand_interleave (rtx, rtx, rtx, bool); extern void build_mask64_2_operands (rtx, rtx *); *************** extern int insvdi_rshift_rlwimi_p (rtx, *** 70,75 **** --- 77,87 ---- extern int registers_ok_for_quad_peep (rtx, rtx); extern int mems_ok_for_quad_peep (rtx, rtx); extern bool gpr_or_gpr_p (rtx, rtx); + extern bool direct_move_p (rtx, rtx); + extern bool quad_load_store_p (rtx, rtx); + extern bool fusion_gpr_load_p (rtx *, bool); + extern void expand_fusion_gpr_load (rtx *); + extern const char *emit_fusion_gpr_load (rtx *); extern enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class); extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class, *************** extern rtx rs6000_longcall_ref (rtx); *** 116,121 **** --- 128,134 ---- extern void rs6000_fatal_bad_address (rtx); extern rtx create_TOC_reference (rtx, rtx); extern void rs6000_split_multireg_move (rtx, rtx); + extern void rs6000_emit_le_vsx_move (rtx, rtx, enum machine_mode); extern void rs6000_emit_move (rtx, rtx, enum machine_mode); extern rtx rs6000_secondary_memory_needed_rtx (enum machine_mode); extern rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode, *************** extern rtx rs6000_address_for_fpconvert *** 135,143 **** --- 148,158 ---- extern rtx rs6000_address_for_altivec (rtx); extern rtx rs6000_allocate_stack_temp (enum machine_mode, bool, bool); extern int rs6000_loop_align (rtx); + extern void rs6000_split_logical (rtx [], enum rtx_code, bool, bool, bool, rtx); #endif /* RTX_CODE */ #ifdef TREE_CODE + extern unsigned int rs6000_data_alignment (tree, unsigned int, enum data_align); extern unsigned int rs6000_special_round_type_align (tree, unsigned int, unsigned int); extern unsigned int darwin_rs6000_special_round_type_align (tree, unsigned int, *************** extern tree altivec_resolve_overloaded_b *** 146,151 **** --- 161,167 ---- extern rtx rs6000_libcall_value (enum machine_mode); extern rtx rs6000_va_arg (tree, tree); extern int function_ok_for_sibcall (tree); + extern int rs6000_reg_parm_stack_space (tree); extern void rs6000_elf_declare_function_name (FILE *, const char *, tree); extern bool rs6000_elf_in_small_data_p (const_tree); #ifdef ARGS_SIZE_RTX *************** extern unsigned int rs6000_dbx_register_ *** 170,176 **** extern void rs6000_emit_epilogue (int); extern void rs6000_emit_eh_reg_restore (rtx, rtx); extern const char * output_isel (rtx *); ! extern void rs6000_call_indirect_aix (rtx, rtx, rtx); extern void rs6000_aix_asm_output_dwarf_table_ref (char *); extern void get_ppc476_thunk_name (char name[32]); extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins); --- 186,193 ---- extern void rs6000_emit_epilogue (int); extern void rs6000_emit_eh_reg_restore (rtx, rtx); extern const char * output_isel (rtx *); ! extern void rs6000_call_aix (rtx, rtx, rtx, rtx); ! extern void rs6000_sibcall_aix (rtx, rtx, rtx, rtx); extern void rs6000_aix_asm_output_dwarf_table_ref (char *); extern void get_ppc476_thunk_name (char name[32]); extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins); diff -Nrcpad gcc-4.8.2/gcc/config/rs6000/rs6000.c gcc-4.8.3/gcc/config/rs6000/rs6000.c *** gcc-4.8.2/gcc/config/rs6000/rs6000.c Mon Sep 23 14:19:31 2013 --- gcc-4.8.3/gcc/config/rs6000/rs6000.c Mon May 5 02:18:35 2014 *************** *** 1,5 **** /* Subroutines used for code generation on IBM RS/6000. ! Copyright (C) 1991-2013 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. --- 1,5 ---- /* Subroutines used for code generation on IBM RS/6000. ! Copyright (C) 1991-2014 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. *************** *** 56,61 **** --- 56,62 ---- #include "intl.h" #include "params.h" #include "tm-constrs.h" + #include "ira.h" #include "opts.h" #include "tree-vectorizer.h" #include "dumpfile.h" *************** typedef struct rs6000_stack { *** 96,101 **** --- 97,103 ---- int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ int varargs_save_offset; /* offset to save the varargs registers */ int ehrd_offset; /* offset to EH return data */ + int ehcr_offset; /* offset to EH CR field data */ int reg_size; /* register size (4 or 8) */ HOST_WIDE_INT vars_size; /* variable save area size */ int parm_size; /* outgoing parameter size */ *************** typedef struct GTY(()) machine_function *** 139,144 **** --- 141,148 ---- 64-bits wide and is allocated early enough so that the offset does not overflow the 16-bit load/store offset field. */ rtx sdmode_stack_slot; + /* Flag if r2 setup is needed with ELFv2 ABI. */ + bool r2_setup_needed; } machine_function; /* Support targetm.vectorize.builtin_mask_for_load. */ *************** unsigned char rs6000_hard_regno_nregs[NU *** 189,197 **** /* Map register number to register class. */ enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; - /* Reload functions based on the type and the vector unit. */ - static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2]; - static int dbg_cost_ctrl; /* Built in types. */ --- 193,198 ---- *************** static struct *** 289,294 **** --- 290,394 ---- don't link in rs6000-c.c, so we can't call it directly. */ void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT); + /* Simplfy register classes into simpler classifications. We assume + GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range + check for standard register classes (gpr/floating/altivec/vsx) and + floating/vector classes (float/altivec/vsx). */ + + enum rs6000_reg_type { + NO_REG_TYPE, + PSEUDO_REG_TYPE, + GPR_REG_TYPE, + VSX_REG_TYPE, + ALTIVEC_REG_TYPE, + FPR_REG_TYPE, + SPR_REG_TYPE, + CR_REG_TYPE, + SPE_ACC_TYPE, + SPEFSCR_REG_TYPE + }; + + /* Map register class to register type. */ + static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES]; + + /* First/last register type for the 'normal' register types (i.e. general + purpose, floating point, altivec, and VSX registers). */ + #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE) + + #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE) + + + /* Register classes we care about in secondary reload or go if legitimate + address. We only need to worry about GPR, FPR, and Altivec registers here, + along an ANY field that is the OR of the 3 register classes. */ + + enum rs6000_reload_reg_type { + RELOAD_REG_GPR, /* General purpose registers. */ + RELOAD_REG_FPR, /* Traditional floating point regs. */ + RELOAD_REG_VMX, /* Altivec (VMX) registers. */ + RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */ + N_RELOAD_REG + }; + + /* For setting up register classes, loop through the 3 register classes mapping + into real registers, and skip the ANY class, which is just an OR of the + bits. */ + #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR + #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX + + /* Map reload register type to a register in the register class. */ + struct reload_reg_map_type { + const char *name; /* Register class name. */ + int reg; /* Register in the register class. */ + }; + + static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = { + { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */ + { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */ + { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */ + { "Any", -1 }, /* RELOAD_REG_ANY. */ + }; + + /* Mask bits for each register class, indexed per mode. Historically the + compiler has been more restrictive which types can do PRE_MODIFY instead of + PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */ + typedef unsigned char addr_mask_type; + + #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */ + #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */ + #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */ + #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */ + #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ + #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ + + /* Register type masks based on the type, of valid addressing modes. */ + struct rs6000_reg_addr { + enum insn_code reload_load; /* INSN to reload for loading. */ + enum insn_code reload_store; /* INSN to reload for storing. */ + enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */ + enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */ + enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */ + addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */ + }; + + static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES]; + + /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */ + static inline bool + mode_supports_pre_incdec_p (enum machine_mode mode) + { + return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) + != 0); + } + + /* Helper function to say whether a mode supports PRE_MODIFY. */ + static inline bool + mode_supports_pre_modify_p (enum machine_mode mode) + { + return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) + != 0); + } + /* Target cpu costs. */ *************** struct processor_costs power7_cost = { *** 828,833 **** --- 928,952 ---- 12, /* prefetch streams */ }; + /* Instruction costs on POWER8 processors. */ + static const + struct processor_costs power8_cost = { + COSTS_N_INSNS (3), /* mulsi */ + COSTS_N_INSNS (3), /* mulsi_const */ + COSTS_N_INSNS (3), /* mulsi_const9 */ + COSTS_N_INSNS (3), /* muldi */ + COSTS_N_INSNS (19), /* divsi */ + COSTS_N_INSNS (35), /* divdi */ + COSTS_N_INSNS (3), /* fp */ + COSTS_N_INSNS (3), /* dmul */ + COSTS_N_INSNS (14), /* sdiv */ + COSTS_N_INSNS (17), /* ddiv */ + 128, /* cache line size */ + 32, /* l1 cache */ + 256, /* l2 cache */ + 12, /* prefetch streams */ + }; + /* Instruction costs on POWER A2 processors. */ static const struct processor_costs ppca2_cost = { *************** struct processor_costs ppca2_cost = { *** 855,860 **** --- 974,980 ---- #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E + #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S *************** struct processor_costs ppca2_cost = { *** 878,883 **** --- 998,1006 ---- #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \ { NAME, ICODE, MASK, ATTR }, + #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \ + { NAME, ICODE, MASK, ATTR }, + #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \ { NAME, ICODE, MASK, ATTR }, *************** static const struct rs6000_builtin_info_ *** 908,913 **** --- 1031,1037 ---- #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E + #undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S *************** static void rs6000_common_init_builtins *** 948,953 **** --- 1072,1078 ---- static void paired_init_builtins (void); static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx); static void spe_init_builtins (void); + static void htm_init_builtins (void); static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); *************** static void rs6000_print_isa_options (FI *** 1020,1025 **** --- 1145,1157 ---- static void rs6000_print_builtin_options (FILE *, int, const char *, HOST_WIDE_INT); + static enum rs6000_reg_type register_to_reg_type (rtx, bool *); + static bool rs6000_secondary_reload_move (enum rs6000_reg_type, + enum rs6000_reg_type, + enum machine_mode, + secondary_reload_info *, + bool); + /* Hash table stuff for keeping track of TOC entries. */ struct GTY(()) toc_hash_struct *************** char rs6000_reg_names[][8] = *** 1068,1074 **** /* SPE registers. */ "spe_acc", "spefscr", /* Soft frame pointer. */ ! "sfp" }; #ifdef TARGET_REGNAMES --- 1200,1208 ---- /* SPE registers. */ "spe_acc", "spefscr", /* Soft frame pointer. */ ! "sfp", ! /* HTM SPR registers. */ ! "tfhar", "tfiar", "texasr" }; #ifdef TARGET_REGNAMES *************** static const char alt_reg_names[][8] = *** 1094,1100 **** /* SPE registers. */ "spe_acc", "spefscr", /* Soft frame pointer. */ ! "sfp" }; #endif --- 1228,1236 ---- /* SPE registers. */ "spe_acc", "spefscr", /* Soft frame pointer. */ ! "sfp", ! /* HTM SPR registers. */ ! "tfhar", "tfiar", "texasr" }; #endif *************** static const struct attribute_spec rs600 *** 1316,1321 **** --- 1452,1460 ---- #undef TARGET_RETURN_IN_MEMORY #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory + #undef TARGET_RETURN_IN_MSB + #define TARGET_RETURN_IN_MSB rs6000_return_in_msb + #undef TARGET_SETUP_INCOMING_VARARGS #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs *************** static const struct attribute_spec rs600 *** 1425,1430 **** --- 1564,1572 ---- #undef TARGET_MODE_DEPENDENT_ADDRESS_P #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p + #undef TARGET_LRA_P + #define TARGET_LRA_P rs6000_lra_p + #undef TARGET_CAN_ELIMINATE #define TARGET_CAN_ELIMINATE rs6000_can_eliminate *************** rs6000_hard_regno_nregs_internal (int re *** 1513,1520 **** { unsigned HOST_WIDE_INT reg_size; if (FP_REGNO_P (regno)) ! reg_size = (VECTOR_MEM_VSX_P (mode) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD); --- 1655,1663 ---- { unsigned HOST_WIDE_INT reg_size; + /* TF/TD modes are special in that they always take 2 registers. */ if (FP_REGNO_P (regno)) ! reg_size = ((VECTOR_MEM_VSX_P (mode) && mode != TDmode && mode != TFmode) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD); *************** rs6000_hard_regno_mode_ok (int regno, en *** 1546,1561 **** { int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1; /* VSX registers that overlap the FPR registers are larger than for non-VSX implementations. Don't allow an item to be split between a FP register ! and an Altivec register. */ ! if (VECTOR_MEM_VSX_P (mode)) { if (FP_REGNO_P (regno)) return FP_REGNO_P (last_regno); if (ALTIVEC_REGNO_P (regno)) ! return ALTIVEC_REGNO_P (last_regno); } /* The GPRs can hold any mode, but values bigger than one register --- 1689,1727 ---- { int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1; + /* PTImode can only go in GPRs. Quad word memory operations require even/odd + register combinations, and use PTImode where we need to deal with quad + word memory operations. Don't allow quad words in the argument or frame + pointer registers, just registers 0..31. */ + if (mode == PTImode) + return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO) + && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO) + && ((regno & 1) == 0)); + /* VSX registers that overlap the FPR registers are larger than for non-VSX implementations. Don't allow an item to be split between a FP register ! and an Altivec register. Allow TImode in all VSX registers if the user ! asked for it. */ ! if (TARGET_VSX && VSX_REGNO_P (regno) ! && (VECTOR_MEM_VSX_P (mode) ! || (TARGET_VSX_SCALAR_FLOAT && mode == SFmode) ! || (TARGET_VSX_SCALAR_DOUBLE && (mode == DFmode || mode == DImode)) ! || (TARGET_VSX_TIMODE && mode == TImode) ! || (TARGET_VADDUQM && mode == V1TImode))) { if (FP_REGNO_P (regno)) return FP_REGNO_P (last_regno); if (ALTIVEC_REGNO_P (regno)) ! { ! if (mode == SFmode && !TARGET_UPPER_REGS_SF) ! return 0; ! ! if ((mode == DFmode || mode == DImode) && !TARGET_UPPER_REGS_DF) ! return 0; ! ! return ALTIVEC_REGNO_P (last_regno); ! } } /* The GPRs can hold any mode, but values bigger than one register *************** rs6000_hard_regno_mode_ok (int regno, en *** 1564,1571 **** return INT_REGNO_P (last_regno); /* The float registers (except for VSX vector modes) can only hold floating ! modes and DImode. This excludes the 32-bit decimal float mode for ! now. */ if (FP_REGNO_P (regno)) { if (SCALAR_FLOAT_MODE_P (mode) --- 1730,1736 ---- return INT_REGNO_P (last_regno); /* The float registers (except for VSX vector modes) can only hold floating ! modes and DImode. */ if (FP_REGNO_P (regno)) { if (SCALAR_FLOAT_MODE_P (mode) *************** rs6000_hard_regno_mode_ok (int regno, en *** 1593,1607 **** /* AltiVec only in AldyVec registers. */ if (ALTIVEC_REGNO_P (regno)) ! return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode); /* ...but GPRs can hold SIMD data on the SPE in one register. */ if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) return 1; ! /* We cannot put TImode anywhere except general register and it must be able ! to fit within the register set. In the future, allow TImode in the ! Altivec or VSX registers. */ return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; } --- 1758,1772 ---- /* AltiVec only in AldyVec registers. */ if (ALTIVEC_REGNO_P (regno)) ! return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) ! || mode == V1TImode); /* ...but GPRs can hold SIMD data on the SPE in one register. */ if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) return 1; ! /* We cannot put non-VSX TImode or PTImode anywhere except general register ! and it must be able to fit within the register set. */ return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; } *************** rs6000_debug_reg_print (int first_regno, *** 1674,1683 **** --- 1839,1915 ---- comma = ""; } + len += fprintf (stderr, "%sreg-class = %s", comma, + reg_class_names[(int)rs6000_regno_regclass[r]]); + comma = ", "; + + if (len > 70) + { + fprintf (stderr, ",\n\t"); + comma = ""; + } + fprintf (stderr, "%sregno = %d\n", comma, r); } } + static const char * + rs6000_debug_vector_unit (enum rs6000_vector v) + { + const char *ret; + + switch (v) + { + case VECTOR_NONE: ret = "none"; break; + case VECTOR_ALTIVEC: ret = "altivec"; break; + case VECTOR_VSX: ret = "vsx"; break; + case VECTOR_P8_VECTOR: ret = "p8_vector"; break; + case VECTOR_PAIRED: ret = "paired"; break; + case VECTOR_SPE: ret = "spe"; break; + case VECTOR_OTHER: ret = "other"; break; + default: ret = "unknown"; break; + } + + return ret; + } + + /* Print the address masks in a human readble fashion. */ + DEBUG_FUNCTION void + rs6000_debug_print_mode (ssize_t m) + { + ssize_t rc; + + fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m)); + for (rc = 0; rc < N_RELOAD_REG; rc++) + { + addr_mask_type mask = reg_addr[m].addr_mask[rc]; + fprintf (stderr, + " %s: %c%c%c%c%c%c", + reload_reg_map[rc].name, + (mask & RELOAD_REG_VALID) != 0 ? 'v' : ' ', + (mask & RELOAD_REG_MULTIPLE) != 0 ? 'm' : ' ', + (mask & RELOAD_REG_INDEXED) != 0 ? 'i' : ' ', + (mask & RELOAD_REG_OFFSET) != 0 ? 'o' : ' ', + (mask & RELOAD_REG_PRE_INCDEC) != 0 ? '+' : ' ', + (mask & RELOAD_REG_PRE_MODIFY) != 0 ? '+' : ' '); + } + + if (rs6000_vector_unit[m] != VECTOR_NONE + || rs6000_vector_mem[m] != VECTOR_NONE + || (reg_addr[m].reload_store != CODE_FOR_nothing) + || (reg_addr[m].reload_load != CODE_FOR_nothing)) + { + fprintf (stderr, + " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c", + rs6000_debug_vector_unit (rs6000_vector_unit[m]), + rs6000_debug_vector_unit (rs6000_vector_mem[m]), + (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*', + (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*'); + } + + fputs ("\n", stderr); + } + #define DEBUG_FMT_ID "%-32s= " #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n" #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: " *************** rs6000_debug_reg_global (void) *** 1690,1695 **** --- 1922,1928 ---- static const char *const tf[2] = { "false", "true" }; const char *nl = (const char *)0; int m; + size_t m1, m2, v; char costly_num[20]; char nop_num[20]; char flags_buffer[40]; *************** rs6000_debug_reg_global (void) *** 1700,1719 **** const char *cmodel_str; struct cl_target_option cl_opts; ! /* Map enum rs6000_vector to string. */ ! static const char *rs6000_debug_vector_unit[] = { ! "none", ! "altivec", ! "vsx", ! "paired", ! "spe", ! "other" }; ! fprintf (stderr, "Register information: (last virtual reg = %d)\n", ! LAST_VIRTUAL_REGISTER); ! rs6000_debug_reg_print (0, 31, "gr"); ! rs6000_debug_reg_print (32, 63, "fp"); rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO, "vs"); --- 1933,2001 ---- const char *cmodel_str; struct cl_target_option cl_opts; ! /* Modes we want tieable information on. */ ! static const enum machine_mode print_tieable_modes[] = { ! QImode, ! HImode, ! SImode, ! DImode, ! TImode, ! PTImode, ! SFmode, ! DFmode, ! TFmode, ! SDmode, ! DDmode, ! TDmode, ! V8QImode, ! V4HImode, ! V2SImode, ! V16QImode, ! V8HImode, ! V4SImode, ! V2DImode, ! V1TImode, ! V32QImode, ! V16HImode, ! V8SImode, ! V4DImode, ! V2TImode, ! V2SFmode, ! V4SFmode, ! V2DFmode, ! V8SFmode, ! V4DFmode, ! CCmode, ! CCUNSmode, ! CCEQmode, }; ! /* Virtual regs we are interested in. */ ! const static struct { ! int regno; /* register number. */ ! const char *name; /* register name. */ ! } virtual_regs[] = { ! { STACK_POINTER_REGNUM, "stack pointer:" }, ! { TOC_REGNUM, "toc: " }, ! { STATIC_CHAIN_REGNUM, "static chain: " }, ! { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " }, ! { HARD_FRAME_POINTER_REGNUM, "hard frame: " }, ! { ARG_POINTER_REGNUM, "arg pointer: " }, ! { FRAME_POINTER_REGNUM, "frame pointer:" }, ! { FIRST_PSEUDO_REGISTER, "first pseudo: " }, ! { FIRST_VIRTUAL_REGISTER, "first virtual:" }, ! { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" }, ! { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " }, ! { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" }, ! { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" }, ! { VIRTUAL_CFA_REGNUM, "cfa (frame): " }, ! { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" }, ! { LAST_VIRTUAL_REGISTER, "last virtual: " }, ! }; ! ! fputs ("\nHard register information:\n", stderr); ! rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr"); ! rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp"); rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO, "vs"); *************** rs6000_debug_reg_global (void) *** 1726,1731 **** --- 2008,2017 ---- rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a"); rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f"); + fputs ("\nVirtual/stack/frame registers:\n", stderr); + for (v = 0; v < ARRAY_SIZE (virtual_regs); v++) + fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno); + fprintf (stderr, "\n" "d reg_class = %s\n" *************** rs6000_debug_reg_global (void) *** 1734,1757 **** "wa reg_class = %s\n" "wd reg_class = %s\n" "wf reg_class = %s\n" ! "ws reg_class = %s\n\n", reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], ! reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]); for (m = 0; m < NUM_MACHINE_MODES; ++m) ! if (rs6000_vector_unit[m] || rs6000_vector_mem[m]) ! { ! nl = "\n"; ! fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n", ! GET_MODE_NAME (m), ! rs6000_debug_vector_unit[ rs6000_vector_unit[m] ], ! rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]); ! } if (nl) fputs (nl, stderr); --- 2020,2088 ---- "wa reg_class = %s\n" "wd reg_class = %s\n" "wf reg_class = %s\n" ! "wg reg_class = %s\n" ! "wl reg_class = %s\n" ! "wm reg_class = %s\n" ! "wr reg_class = %s\n" ! "ws reg_class = %s\n" ! "wt reg_class = %s\n" ! "wu reg_class = %s\n" ! "wv reg_class = %s\n" ! "ww reg_class = %s\n" ! "wx reg_class = %s\n" ! "wy reg_class = %s\n" ! "wz reg_class = %s\n" ! "\n", reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], ! reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]], ! reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]], ! reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]], ! reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]], ! reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]], ! reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]], ! reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]], ! reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]], ! reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]], ! reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]], ! reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]], ! reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]]); + nl = "\n"; for (m = 0; m < NUM_MACHINE_MODES; ++m) ! rs6000_debug_print_mode (m); ! ! fputs ("\n", stderr); ! ! for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++) ! { ! enum machine_mode mode1 = print_tieable_modes[m1]; ! bool first_time = true; ! ! nl = (const char *)0; ! for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++) ! { ! enum machine_mode mode2 = print_tieable_modes[m2]; ! if (mode1 != mode2 && MODES_TIEABLE_P (mode1, mode2)) ! { ! if (first_time) ! { ! fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1)); ! nl = "\n"; ! first_time = false; ! } ! ! fprintf (stderr, " %s", GET_MODE_NAME (mode2)); ! } ! } ! ! if (!first_time) ! fputs ("\n", stderr); ! } if (nl) fputs (nl, stderr); *************** rs6000_debug_reg_global (void) *** 1913,1918 **** --- 2244,2250 ---- { case ABI_NONE: abi_str = "none"; break; case ABI_AIX: abi_str = "aix"; break; + case ABI_ELFv2: abi_str = "ELFv2"; break; case ABI_V4: abi_str = "V4"; break; case ABI_DARWIN: abi_str = "darwin"; break; default: abi_str = "unknown"; break; *************** rs6000_debug_reg_global (void) *** 1932,1940 **** --- 2264,2297 ---- if (rs6000_float_gprs) fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true"); + fprintf (stderr, DEBUG_FMT_S, "fprs", + (TARGET_FPRS ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "single_float", + (TARGET_SINGLE_FLOAT ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "double_float", + (TARGET_DOUBLE_FLOAT ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "soft_float", + (TARGET_SOFT_FLOAT ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "e500_single", + (TARGET_E500_SINGLE ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "e500_double", + (TARGET_E500_DOUBLE ? "true" : "false")); + if (TARGET_LINK_STACK) fprintf (stderr, DEBUG_FMT_S, "link_stack", "true"); + if (targetm.lra_p ()) + fprintf (stderr, DEBUG_FMT_S, "lra", "true"); + + if (TARGET_P8_FUSION) + fprintf (stderr, DEBUG_FMT_S, "p8 fusion", + (TARGET_P8_FUSION_SIGN) ? "zero+sign" : "zero"); + fprintf (stderr, DEBUG_FMT_S, "plt-format", TARGET_SECURE_PLT ? "secure" : "bss"); fprintf (stderr, DEBUG_FMT_S, "struct-return", *************** rs6000_debug_reg_global (void) *** 1954,1964 **** (int)RS6000_BUILTIN_COUNT); } /* Initialize the various global tables that are based on register size. */ static void rs6000_init_hard_regno_mode_ok (bool global_init_p) { ! int r, m, c; int align64; int align32; --- 2311,2416 ---- (int)RS6000_BUILTIN_COUNT); } + + /* Update the addr mask bits in reg_addr to help secondary reload and go if + legitimate address support to figure out the appropriate addressing to + use. */ + + static void + rs6000_setup_reg_addr_masks (void) + { + ssize_t rc, reg, m, nregs; + addr_mask_type any_addr_mask, addr_mask; + + for (m = 0; m < NUM_MACHINE_MODES; ++m) + { + /* SDmode is special in that we want to access it only via REG+REG + addressing on power7 and above, since we want to use the LFIWZX and + STFIWZX instructions to load it. */ + bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK); + + any_addr_mask = 0; + for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++) + { + addr_mask = 0; + reg = reload_reg_map[rc].reg; + + /* Can mode values go in the GPR/FPR/Altivec registers? */ + if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg]) + { + nregs = rs6000_hard_regno_nregs[m][reg]; + addr_mask |= RELOAD_REG_VALID; + + /* Indicate if the mode takes more than 1 physical register. If + it takes a single register, indicate it can do REG+REG + addressing. */ + if (nregs > 1 || m == BLKmode) + addr_mask |= RELOAD_REG_MULTIPLE; + else + addr_mask |= RELOAD_REG_INDEXED; + + /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY + addressing. Restrict addressing on SPE for 64-bit types + because of the SUBREG hackery used to address 64-bit floats in + '32-bit' GPRs. To simplify secondary reload, don't allow + update forms on scalar floating point types that can go in the + upper registers. */ + + if (TARGET_UPDATE + && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) + && GET_MODE_SIZE (m) <= 8 + && !VECTOR_MODE_P (m) + && !COMPLEX_MODE_P (m) + && !indexed_only_p + && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m) == 8) + && !(m == DFmode && TARGET_UPPER_REGS_DF) + && !(m == SFmode && TARGET_UPPER_REGS_SF)) + { + addr_mask |= RELOAD_REG_PRE_INCDEC; + + /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that + we don't allow PRE_MODIFY for some multi-register + operations. */ + switch (m) + { + default: + addr_mask |= RELOAD_REG_PRE_MODIFY; + break; + + case DImode: + if (TARGET_POWERPC64) + addr_mask |= RELOAD_REG_PRE_MODIFY; + break; + + case DFmode: + case DDmode: + if (TARGET_DF_INSN) + addr_mask |= RELOAD_REG_PRE_MODIFY; + break; + } + } + } + + /* GPR and FPR registers can do REG+OFFSET addressing, except + possibly for SDmode. */ + if ((addr_mask != 0) && !indexed_only_p + && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)) + addr_mask |= RELOAD_REG_OFFSET; + + reg_addr[m].addr_mask[rc] = addr_mask; + any_addr_mask |= addr_mask; + } + + reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask; + } + } + + /* Initialize the various global tables that are based on register size. */ static void rs6000_init_hard_regno_mode_ok (bool global_init_p) { ! ssize_t r, m, c; int align64; int align32; *************** rs6000_init_hard_regno_mode_ok (bool glo *** 1987,2006 **** rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS; rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS; rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS; rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS; rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS; ! /* Precalculate vector information, this must be set up before the ! rs6000_hard_regno_nregs_internal below. */ ! for (m = 0; m < NUM_MACHINE_MODES; ++m) { ! rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE; ! rs6000_vector_reload[m][0] = CODE_FOR_nothing; ! rs6000_vector_reload[m][1] = CODE_FOR_nothing; } ! for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++) ! rs6000_constraints[c] = NO_REGS; /* The VSX hardware allows native alignment for vectors, but control whether the compiler believes it can use native alignment or still uses 128-bit alignment. */ --- 2439,2492 ---- rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS; rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS; rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS; + rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS; + rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS; + rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS; rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS; rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS; ! /* Precalculate register class to simpler reload register class. We don't ! need all of the register classes that are combinations of different ! classes, just the simple ones that have constraint letters. */ ! for (c = 0; c < N_REG_CLASSES; c++) ! reg_class_to_reg_type[c] = NO_REG_TYPE; ! ! reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE; ! reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE; ! reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE; ! reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE; ! reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE; ! reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE; ! reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE; ! reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE; ! reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE; ! reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE; ! reg_class_to_reg_type[(int)SPE_ACC_REGS] = SPE_ACC_TYPE; ! reg_class_to_reg_type[(int)SPEFSCR_REGS] = SPEFSCR_REG_TYPE; ! ! if (TARGET_VSX) { ! reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE; ! reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE; ! } ! else ! { ! reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE; ! reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE; } ! /* Precalculate the valid memory formats as well as the vector information, ! this must be set up before the rs6000_hard_regno_nregs_internal calls ! below. */ ! gcc_assert ((int)VECTOR_NONE == 0); ! memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit)); ! memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit)); ! ! gcc_assert ((int)CODE_FOR_nothing == 0); ! memset ((void *) ®_addr[0], '\0', sizeof (reg_addr)); ! ! gcc_assert ((int)NO_REGS == 0); ! memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints)); /* The VSX hardware allows native alignment for vectors, but control whether the compiler believes it can use native alignment or still uses 128-bit alignment. */ *************** rs6000_init_hard_regno_mode_ok (bool glo *** 2062,2074 **** } } ! /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract. ! Altivec doesn't have 64-bit support. */ if (TARGET_VSX) { rs6000_vector_mem[V2DImode] = VECTOR_VSX; ! rs6000_vector_unit[V2DImode] = VECTOR_NONE; rs6000_vector_align[V2DImode] = align64; } /* DFmode, see if we want to use the VSX unit. */ --- 2548,2566 ---- } } ! /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to ! do insert/splat/extract. Altivec doesn't have 64-bit integer support. */ if (TARGET_VSX) { rs6000_vector_mem[V2DImode] = VECTOR_VSX; ! rs6000_vector_unit[V2DImode] ! = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE; rs6000_vector_align[V2DImode] = align64; + + rs6000_vector_mem[V1TImode] = VECTOR_VSX; + rs6000_vector_unit[V1TImode] + = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE; + rs6000_vector_align[V1TImode] = 128; } /* DFmode, see if we want to use the VSX unit. */ *************** rs6000_init_hard_regno_mode_ok (bool glo *** 2076,2089 **** { rs6000_vector_unit[DFmode] = VECTOR_VSX; rs6000_vector_mem[DFmode] ! = (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE); rs6000_vector_align[DFmode] = align64; } /* TODO add SPE and paired floating point vector support. */ /* Register class constraints for the constraints that depend on compile ! switches. */ if (TARGET_HARD_FLOAT && TARGET_FPRS) rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; --- 2568,2615 ---- { rs6000_vector_unit[DFmode] = VECTOR_VSX; rs6000_vector_mem[DFmode] ! = (TARGET_UPPER_REGS_DF ? VECTOR_VSX : VECTOR_NONE); rs6000_vector_align[DFmode] = align64; } + /* Allow TImode in VSX register and set the VSX memory macros. */ + if (TARGET_VSX && TARGET_VSX_TIMODE) + { + rs6000_vector_mem[TImode] = VECTOR_VSX; + rs6000_vector_align[TImode] = align64; + } + /* TODO add SPE and paired floating point vector support. */ /* Register class constraints for the constraints that depend on compile ! switches. When the VSX code was added, different constraints were added ! based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all ! of the VSX registers are used. The register classes for scalar floating ! point types is set, based on whether we allow that type into the upper ! (Altivec) registers. GCC has register classes to target the Altivec ! registers for load/store operations, to select using a VSX memory ! operation instead of the traditional floating point operation. The ! constraints are: ! ! d - Register class to use with traditional DFmode instructions. ! f - Register class to use with traditional SFmode instructions. ! v - Altivec register. ! wa - Any VSX register. ! wd - Preferred register class for V2DFmode. ! wf - Preferred register class for V4SFmode. ! wg - Float register for power6x move insns. ! wl - Float register if we can do 32-bit signed int loads. ! wm - VSX register for ISA 2.07 direct move operations. ! wr - GPR if 64-bit mode is permitted. ! ws - Register class to do ISA 2.06 DF operations. ! wu - Altivec register for ISA 2.07 VSX SF/SI load/stores. ! wv - Altivec register for ISA 2.06 VSX DF/DI load/stores. ! wt - VSX register for TImode in VSX registers. ! ww - Register class to do SF conversions in with VSX operations. ! wx - Float register if we can do 32-bit int stores. ! wy - Register class to do ISA 2.07 SF operations. ! wz - Float register if we can do 32-bit unsigned int loads. */ ! if (TARGET_HARD_FLOAT && TARGET_FPRS) rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; *************** rs6000_init_hard_regno_mode_ok (bool glo *** 2092,2154 **** if (TARGET_VSX) { - /* At present, we just use VSX_REGS, but we have different constraints - based on the use, in case we want to fine tune the default register - class used. wa = any VSX register, wf = register class to use for - V4SF, wd = register class to use for V2DF, and ws = register classs to - use for DF scalars. */ rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS; - rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; ! rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY ! ? VSX_REGS ! : FLOAT_REGS); } if (TARGET_ALTIVEC) rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS; ! /* Set up the reload helper functions. */ if (TARGET_VSX || TARGET_ALTIVEC) { if (TARGET_64BIT) { ! rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store; ! rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load; ! rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_di_store; ! rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_di_load; ! rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_di_store; ! rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_di_load; ! rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_di_store; ! rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_di_load; ! rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_di_store; ! rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_di_load; ! rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store; ! rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load; ! if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY) { ! rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_di_store; ! rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_di_load; } } else { ! rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store; ! rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load; ! rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_si_store; ! rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_si_load; ! rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_si_store; ! rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_si_load; ! rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_si_store; ! rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_si_load; ! rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_si_store; ! rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_si_load; ! rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_si_store; ! rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_si_load; ! if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY) { ! rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_si_store; ! rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_si_load; } } } --- 2618,2780 ---- if (TARGET_VSX) { rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS; rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; ! rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; ! ! if (TARGET_VSX_TIMODE) ! rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; ! ! if (TARGET_UPPER_REGS_DF) ! { ! rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; ! rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; ! } ! else ! rs6000_constraints[RS6000_CONSTRAINT_ws] = FLOAT_REGS; } + /* Add conditional constraints based on various options, to allow us to + collapse multiple insn patterns. */ if (TARGET_ALTIVEC) rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS; ! if (TARGET_MFPGPR) ! rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS; ! ! if (TARGET_LFIWAX) ! rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; ! ! if (TARGET_DIRECT_MOVE) ! rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS; ! ! if (TARGET_POWERPC64) ! rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS; ! ! if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) ! { ! rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS; ! rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS; ! rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS; ! } ! else if (TARGET_P8_VECTOR) ! { ! rs6000_constraints[RS6000_CONSTRAINT_wy] = FLOAT_REGS; ! rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS; ! } ! else if (TARGET_VSX) ! rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS; ! ! if (TARGET_STFIWX) ! rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; ! ! if (TARGET_LFIWZX) ! rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; ! ! /* Set up the reload helper and direct move functions. */ if (TARGET_VSX || TARGET_ALTIVEC) { if (TARGET_64BIT) { ! reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store; ! reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load; ! reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store; ! reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load; ! reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store; ! reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load; ! reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store; ! reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load; ! reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store; ! reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load; ! reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store; ! reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load; ! reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store; ! reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load; ! if (TARGET_VSX && TARGET_UPPER_REGS_DF) { ! reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store; ! reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load; ! reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store; ! reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load; ! } ! if (TARGET_P8_VECTOR) ! { ! reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store; ! reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load; ! reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store; ! reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load; ! } ! if (TARGET_VSX_TIMODE) ! { ! reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store; ! reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load; ! } ! if (TARGET_DIRECT_MOVE) ! { ! if (TARGET_POWERPC64) ! { ! reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti; ! reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti; ! reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df; ! reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di; ! reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf; ! reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si; ! reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi; ! reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi; ! reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf; ! ! reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti; ! reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti; ! reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df; ! reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di; ! reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf; ! reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si; ! reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi; ! reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi; ! reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf; ! } ! else ! { ! reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi; ! reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd; ! reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf; ! } } } else { ! reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store; ! reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load; ! reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store; ! reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load; ! reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store; ! reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load; ! reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store; ! reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load; ! reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store; ! reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load; ! reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store; ! reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load; ! reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store; ! reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load; ! if (TARGET_VSX && TARGET_UPPER_REGS_DF) { ! reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store; ! reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load; ! reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store; ! reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load; ! } ! if (TARGET_P8_VECTOR) ! { ! reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store; ! reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load; ! reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store; ! reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load; ! } ! if (TARGET_VSX_TIMODE) ! { ! reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store; ! reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load; } } } *************** rs6000_init_hard_regno_mode_ok (bool glo *** 2267,2272 **** --- 2893,2903 ---- } } + /* Update the addr mask bits in reg_addr to help secondary reload and go if + legitimate address support to figure out the appropriate addressing to + use. */ + rs6000_setup_reg_addr_masks (); + if (global_init_p || TARGET_DEBUG_TARGET) { if (TARGET_DEBUG_REG) *************** darwin_rs6000_override_options (void) *** 2369,2384 **** HOST_WIDE_INT rs6000_builtin_mask_calculate (void) { ! return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) ! | ((TARGET_VSX) ? RS6000_BTM_VSX : 0) ! | ((TARGET_SPE) ? RS6000_BTM_SPE : 0) ! | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0) ! | ((TARGET_FRE) ? RS6000_BTM_FRE : 0) ! | ((TARGET_FRES) ? RS6000_BTM_FRES : 0) ! | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0) ! | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0) ! | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0) ! | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)); } /* Override command line options. Mostly we process the processor type and --- 3000,3020 ---- HOST_WIDE_INT rs6000_builtin_mask_calculate (void) { ! return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) ! | ((TARGET_VSX) ? RS6000_BTM_VSX : 0) ! | ((TARGET_SPE) ? RS6000_BTM_SPE : 0) ! | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0) ! | ((TARGET_FRE) ? RS6000_BTM_FRE : 0) ! | ((TARGET_FRES) ? RS6000_BTM_FRES : 0) ! | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0) ! | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0) ! | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0) ! | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0) ! | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0) ! | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0) ! | ((TARGET_HTM) ? RS6000_BTM_HTM : 0) ! | ((TARGET_DFP) ? RS6000_BTM_DFP : 0) ! | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)); } /* Override command line options. Mostly we process the processor type and *************** rs6000_option_override_internal (bool gl *** 2415,2421 **** calculation works better for RTL loop invariant motion on targets with enough (>= 32) registers. It is an expensive optimization. So it is on only for peak performance. */ ! if (optimize >= 3 && global_init_p) flag_ira_loop_pressure = 1; /* Set the pointer size. */ --- 3051,3058 ---- calculation works better for RTL loop invariant motion on targets with enough (>= 32) registers. It is an expensive optimization. So it is on only for peak performance. */ ! if (optimize >= 3 && global_init_p ! && !global_options_set.x_flag_ira_loop_pressure) flag_ira_loop_pressure = 1; /* Set the pointer size. */ *************** rs6000_option_override_internal (bool gl *** 2609,2614 **** --- 3246,3269 ---- } } + /* If little-endian, default to -mstrict-align on older processors. + Testing for htm matches power8 and later. */ + if (!BYTES_BIG_ENDIAN + && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM)) + rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; + + /* -maltivec={le,be} implies -maltivec. */ + if (rs6000_altivec_element_order != 0) + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; + + /* Disallow -maltivec=le in big endian mode for now. This is not + known to be useful for anyone. */ + if (BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 1) + { + warning (0, N_("-maltivec=le not allowed for big-endian targets")); + rs6000_altivec_element_order = 0; + } + /* Add some warnings for VSX. */ if (TARGET_VSX) { *************** rs6000_option_override_internal (bool gl *** 2619,2633 **** if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx requires hardware floating point"); else ! rs6000_isa_flags &= ~ OPTION_MASK_VSX; } else if (TARGET_PAIRED_FLOAT) msg = N_("-mvsx and -mpaired are incompatible"); - /* The hardware will allow VSX and little endian, but until we make sure - things like vector select, etc. work don't allow VSX on little endian - systems at this point. */ - else if (!BYTES_BIG_ENDIAN) - msg = N_("-mvsx used with little endian code"); else if (TARGET_AVOID_XFORM > 0) msg = N_("-mvsx needs indexed addressing"); else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit --- 3274,3286 ---- if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx requires hardware floating point"); else ! { ! rs6000_isa_flags &= ~ OPTION_MASK_VSX; ! rs6000_isa_flags_explicit |= OPTION_MASK_VSX; ! } } else if (TARGET_PAIRED_FLOAT) msg = N_("-mvsx and -mpaired are incompatible"); else if (TARGET_AVOID_XFORM > 0) msg = N_("-mvsx needs indexed addressing"); else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit *************** rs6000_option_override_internal (bool gl *** 2647,2655 **** } } /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-