head 1.1; access; symbols; locks; strict; comment @# @; 1.1 date 2006.06.13.00.53.36; author joff; state Exp; branches; next ; commitid 21b4448e0ae24567; desc @@ 1.1 log @Initial import of ts7300_opencore. Quartus II project tree for Technologic Systems TS-7300 FPGA Linux Computer. Contains WISHBONE bridge verilog as well as pin locks, timing constraints, and various other Quartus II project metadata. Also included is a sample implementation of the open-ethernet core as well as a stub WISHBONE slave demonstrating a 32-bit register in the address space of the ARM9 CPU running Linux. @ text @////////////////////////////////////////////////////////////////////// //// //// //// eth_register.v //// //// //// //// This file is part of the Ethernet IP core project //// //// http://www.opencores.org/projects/ethmac/ //// //// //// //// Author(s): //// //// - Igor Mohor (igorM@@opencores.org) //// //// //// //// All additional information is avaliable in the Readme.txt //// //// file. //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2001, 2002 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: eth_register.v,v $ // Revision 1.6 2002/08/16 22:10:12 mohor // Synchronous reset added. // // Revision 1.5 2002/08/16 12:33:27 mohor // Parameter ResetValue changed to capital letters. // // Revision 1.4 2002/02/26 16:18:08 mohor // Reset values are passed to registers through parameters // // Revision 1.3 2002/01/23 10:28:16 mohor // Link in the header changed. // // Revision 1.2 2001/10/19 08:43:51 mohor // eth_timescale.v changed to timescale.v This is done because of the // simulation of the few cores in a one joined project. // // Revision 1.1 2001/08/06 14:44:29 mohor // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). // Include files fixed to contain no path. // File names and module names changed ta have a eth_ prologue in the name. // File eth_timescale.v is used to define timescale // All pin names on the top module are changed to contain _I, _O or _OE at the end. // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O // and Mdo_OE. The bidirectional signal must be created on the top level. This // is done due to the ASIC tools. // // // // // // // `include "timescale.v" module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset); parameter WIDTH = 8; // default parameter of the register width parameter RESET_VALUE = 0; input [WIDTH-1:0] DataIn; input Write; input Clk; input Reset; input SyncReset; output [WIDTH-1:0] DataOut; reg [WIDTH-1:0] DataOut; always @@ (posedge Clk or posedge Reset) begin if(Reset) DataOut<=#1 RESET_VALUE; else if(SyncReset) DataOut<=#1 RESET_VALUE; else if(Write) // write DataOut<=#1 DataIn; end endmodule // Register @