head 1.1; access; symbols; locks; strict; comment @# @; 1.1 date 2006.06.13.00.53.36; author joff; state Exp; branches; next ; commitid 21b4448e0ae24567; desc @@ 1.1 log @Initial import of ts7300_opencore. Quartus II project tree for Technologic Systems TS-7300 FPGA Linux Computer. Contains WISHBONE bridge verilog as well as pin locks, timing constraints, and various other Quartus II project metadata. Also included is a sample implementation of the open-ethernet core as well as a stub WISHBONE slave demonstrating a 32-bit register in the address space of the ARM9 CPU running Linux. @ text @////////////////////////////////////////////////////////////////////// //// //// //// TODO //// //// //// //// This file is part of the Ethernet IP core project //// //// http://www.opencores.org/projects/ethmac/ //// //// //// //// Author(s): //// //// - Igor Mohor (igorM@@opencores.org) //// //// //// //// All additional information is available in the Readme.txt //// //// file. //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2001, 2002 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: TODO,v $ // Revision 1.3 2003/01/23 09:14:12 mohor // Fix MTxErr or prevent sending too big frames. // // Revision 1.2 2002/11/21 00:33:32 mohor // In loopback rx_clk is not looped back. Possible CRC error. Consider if usage // of additional logic is necessery (FIFO for looping the data). // // Revision 1.1 2002/09/10 10:42:06 mohor // HASH improvement needed. // - Add logic for easier use of the HASH table: First write MAC address to some register. Then issue a command. CRC is calculated from this MAC and appropriate bit written to the HASH register. - In loopback rx_clk is not looped back. Possible CRC error. Consider if usage of additional logic is necessery (FIFO for looping the data). - When sending frames bigger than MaxFL, MaxFL is sent, BD marked as finished, TxB_IRQ interrupt is set and MTxErr is set for a short period. Fix MTxErr or prevent sending too big frames or set TxE_IRQ instead. @