head 1.2; access; symbols V01:1.1.1.1 GNU:1.1.1; locks; strict; comment @# @; 1.2 date 2007.06.22.14.57.47; author johanneshau; state Exp; branches; next 1.1; commitid dcf467be3694567; 1.1 date 2006.11.21.13.34.45; author johanneshau; state Exp; branches 1.1.1.1; next ; commitid 48c1456300744567; 1.1.1.1 date 2006.11.21.13.34.45; author johanneshau; state Exp; branches; next ; commitid 48c1456300744567; desc @@ 1.2 log @add high address register changed clocking scheme to fully synchronous @ text @ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test_spi_ctrl is end test_spi_ctrl; architecture test of test_spi_ctrl is signal rst, clk, sel, rd, wr : std_logic; signal addr : std_logic_vector (2 downto 0); signal spi_clk, spi_cs, spi_din, spi_dout : std_logic; signal d_in, d_out, stat, data : std_logic_vector (7 downto 0); -- FLASH commands constant NOP : std_logic_vector (7 downto 0) := x"FF"; -- no cmd to execute constant WREN : std_logic_vector (7 downto 0) := x"06"; -- write enable constant WRDI : std_logic_vector (7 downto 0) := x"04"; -- write disable constant RDSR : std_logic_vector (7 downto 0) := x"05"; -- read status reg constant WRSR : std_logic_vector (7 downto 0) := x"01"; -- write stat. reg constant RDCMD: std_logic_vector (7 downto 0) := x"03"; -- read data constant F_RD : std_logic_vector (7 downto 0) := x"0B"; -- fast read data constant PP : std_logic_vector (7 downto 0) := x"02"; -- page program constant SE : std_logic_vector (7 downto 0) := x"D8"; -- sector erase constant BE : std_logic_vector (7 downto 0) := x"C7"; -- bulk erase constant DP : std_logic_vector (7 downto 0) := x"B9"; -- deep power down constant RES : std_logic_vector (7 downto 0) := x"AB"; -- read signature -- status register bit masks constant STAT_BUSY : std_logic_vector (7 downto 0) := x"01"; constant STAT_TXE : std_logic_vector (7 downto 0) := x"02"; constant STAT_RXR : std_logic_vector (7 downto 0) := x"04"; constant STAT_WDAT : std_logic_vector (7 downto 0) := x"08"; begin dut : entity work.spi_ctrl port map ( clk_in => clk, rst => rst, spi_clk => spi_clk, spi_cs => spi_cs, spi_din => spi_din, spi_dout => spi_dout, sel => sel, wr => wr, addr => addr, d_in => d_in, d_out => d_out ); process is begin clk <= '0'; wait for 20 ns; clk <= '1'; wait for 20 ns; end process; process is begin rst <= '0'; wait for 50 ns; rst <= '1'; wait for 120 ns; rst <= '0'; wait; end process; process begin -- initial condition sel <= '0'; addr <= "000"; rd <= '0'; wr <= '0'; d_in <= x"FF"; wait for 1420 ns; -- write command WREN sel <= '1'; addr <= "001"; d_in <= WREN; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 2 us; -- write command WRDI sel <= '1'; addr <= "001"; d_in <= WRDI; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 2 us; -- write command WRSR: data sel <= '1'; addr <= "000"; d_in <= x"55"; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 10 ns; -- the command sel <= '1'; addr <= "001"; d_in <= WRSR; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 4 us; -- write command SE: -- address low sel <= '1'; addr <= "010"; d_in <= x"AB"; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 10 ns; --address mid sel <= '1'; addr <= "011"; d_in <= x"CD"; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 10 ns; -- address high sel <= '1'; addr <= "100"; d_in <= x"EF"; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 10 ns; -- the command sel <= '1'; addr <= "001"; d_in <= SE; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 6.5 us; -- write command PP: -- address low sel <= '1'; addr <= "010"; d_in <= x"45"; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 10 ns; -- address mid sel <= '1'; addr <= "011"; d_in <= x"67"; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 10 ns; -- address high sel <= '1'; addr <= "100"; d_in <= x"89"; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 10 ns; -- the command sel <= '1'; addr <= "001"; d_in <= PP; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 100 ns; -- some data for i in 0 to 20 loop -- wait for tx_empty stat <= x"00"; wait for 10 ns; while (stat and STAT_WDAT) /= STAT_WDAT loop sel <= '1'; addr <= "001"; wait for 5 ns; rd <= '1'; wait for 100 ns; stat <= d_out; rd <= '0'; wait for 5 ns; sel <= '0'; wait for 1 us; end loop; -- write new data sel <= '1'; addr <= "000"; d_in <= std_logic_vector(TO_UNSIGNED(i, d_in'Length)); wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 1 us; end loop; -- send one more byte wait for 10 us; sel <= '1'; addr <= "000"; d_in <= x"AA"; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 1 us; -- write the NOP command to terminate sel <= '1'; addr <= "001"; d_in <= NOP; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 100 ns; wait for 40 us; -- now receive something, cmd RDSR sel <= '1'; addr <= "001"; d_in <= RDSR; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; -- poll for rx_ready stat <= x"00"; wait for 10 ns; while (stat and STAT_RXR) /= STAT_RXR loop wait for 200 ns; sel <= '1'; addr <= "001"; wait for 5 ns; rd <= '1'; wait for 100 ns; stat <= d_out; rd <= '0'; wait for 5 ns; sel <= '0'; end loop; wait for 100 ns; -- read the data sel <= '1'; addr <= "000"; wait for 5 ns; rd <= '1'; wait for 100 ns; data <= d_out; rd <= '0'; wait for 5 ns; sel <= '0'; wait for 1.5 us; -- RES command sel <= '1'; addr <= "001"; d_in <= RES; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; -- poll for rx_ready stat <= x"00"; wait for 10 ns; while (stat and STAT_RXR) /= STAT_RXR loop wait for 200 ns; sel <= '1'; addr <= "001"; wait for 5 ns; rd <= '1'; wait for 100 ns; stat <= d_out; rd <= '0'; wait for 5 ns; sel <= '0'; end loop; wait for 100 ns; -- read the data sel <= '1'; addr <= "000"; wait for 5 ns; rd <= '1'; wait for 100 ns; data <= d_out; rd <= '0'; wait for 5 ns; sel <= '0'; wait for 1.5 us; -- READ command -- address low sel <= '1'; addr <= "010"; d_in <= x"12"; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 10 ns; -- address mid sel <= '1'; addr <= "011"; d_in <= x"34"; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 10 ns; -- address high sel <= '1'; addr <= "100"; d_in <= x"56"; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait for 10 ns; -- the command sel <= '1'; addr <= "001"; d_in <= RDCMD; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; -- read data for i in 1 to 10 loop -- poll for rx_ready stat <= x"00"; wait for 10 ns; while (stat and STAT_RXR) /= STAT_RXR loop wait for 200 ns; sel <= '1'; addr <= "001"; wait for 5 ns; rd <= '1'; wait for 100 ns; stat <= d_out; rd <= '0'; wait for 5 ns; sel <= '0'; end loop; wait for 100 ns; -- read the data sel <= '1'; addr <= "000"; wait for 5 ns; rd <= '1'; wait for 100 ns; data <= d_out; rd <= '0'; wait for 5 ns; sel <= '0'; end loop; wait for 1 us; -- write the NOP command to terminate sel <= '1'; addr <= "001"; d_in <= NOP; wait for 5 ns; wr <= '1'; wait for 100 ns; wr <= '0'; wait for 5 ns; sel <= '0'; d_in <= x"FF"; wait; end process; process begin spi_din <= '1'; wait for 144.880 us; -- input data for RDSR cmd 0x54 spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 7.68 us; ------------------------------- -- input data for RES cmd 0xAB spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '1'; wait for 8.0 us; ------------------------------- -- input data for RD cmd 0x01 spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '1'; wait for 480 ns; -- input data for RD cmd 0x02 spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 480 ns; -- input data for RD cmd 0x03 spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '1'; wait for 480 ns; -- input data for RD cmd 0x04 spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 480 ns; -- input data for RD cmd 0x05 spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '1'; wait for 480 ns; -- input data for RD cmd 0x06 spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 640 ns; -- input data for RD cmd 0x07 spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '1'; wait for 480 ns; -- input data for RD cmd 0x08 spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 480 ns; -- input data for RD cmd 0x09 spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '1'; wait for 480 ns; -- input data for RD cmd 0x0A spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait for 160 ns; spi_din <= '0'; wait for 160 ns; spi_din <= '1'; wait; end process; end test; @ 1.1 log @Initial revision @ text @d10 2 a11 2 signal rst, clk, sel, nRD, nWR : std_logic; signal addr : std_logic_vector (1 downto 0); d20 1 a20 1 constant RD : std_logic_vector (7 downto 0) := x"03"; -- read data d35 1 a36 1 clk => clk, d42 1 a42 2 nWR => nWR, nRD => nRD, d50 2 a51 2 clk <= '0'; wait for 80 ns; clk <= '1'; wait for 80 ns; d53 1 a53 1 d65 1 a65 1 sel <= '0'; addr <= "00"; nRD <= '1'; nWR <= '1'; d_in <= x"FF"; d69 3 a71 3 sel <= '1'; addr <= "01"; d_in <= WREN; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d75 3 a77 3 sel <= '1'; addr <= "01"; d_in <= WRDI; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d81 3 a83 3 sel <= '1'; addr <= "00"; d_in <= x"55"; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d86 3 a88 3 sel <= '1'; addr <= "01"; d_in <= WRSR; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d91 5 a95 4 -- write command SE: address mid sel <= '1'; addr <= "10"; d_in <= x"AB"; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d97 9 a105 4 -- address low sel <= '1'; addr <= "11"; d_in <= x"CD"; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d108 3 a110 3 sel <= '1'; addr <= "01"; d_in <= SE; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d113 5 a117 4 -- write command PP: address mid sel <= '1'; addr <= "10"; d_in <= x"67"; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d119 9 a127 4 -- address low sel <= '1'; addr <= "11"; d_in <= x"89"; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d130 3 a132 3 sel <= '1'; addr <= "01"; d_in <= PP; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d139 3 a141 3 sel <= '1'; addr <= "01"; wait for 5 ns; nRD <= '0'; wait for 100 ns; stat <= d_out; nRD <= '1'; wait for 5 ns; d145 1 a145 1 sel <= '1'; addr <= "00"; d147 2 a148 2 nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d153 3 a155 3 sel <= '1'; addr <= "00"; d_in <= x"AA"; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d158 3 a160 3 sel <= '1'; addr <= "01"; d_in <= NOP; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d166 3 a168 3 sel <= '1'; addr <= "01"; d_in <= RDSR; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d174 3 a176 3 sel <= '1'; addr <= "01"; wait for 5 ns; nRD <= '0'; wait for 100 ns; stat <= d_out; nRD <= '1'; wait for 5 ns; d181 3 a183 3 sel <= '1'; addr <= "00"; wait for 5 ns; nRD <= '0'; wait for 100 ns; data <= d_out; nRD <= '1'; wait for 5 ns; d187 3 a189 3 sel <= '1'; addr <= "01"; d_in <= RES; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d195 3 a197 3 sel <= '1'; addr <= "01"; wait for 5 ns; nRD <= '0'; wait for 100 ns; stat <= d_out; nRD <= '1'; wait for 5 ns; d202 3 a204 3 sel <= '1'; addr <= "00"; wait for 5 ns; nRD <= '0'; wait for 100 ns; data <= d_out; nRD <= '1'; wait for 5 ns; d208 4 a211 3 sel <= '1'; addr <= "10"; d_in <= x"12"; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d213 9 a221 4 -- address low sel <= '1'; addr <= "11"; d_in <= x"34"; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d224 3 a226 3 sel <= '1'; addr <= "01"; d_in <= RD; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d234 3 a236 3 sel <= '1'; addr <= "01"; wait for 5 ns; nRD <= '0'; wait for 100 ns; stat <= d_out; nRD <= '1'; wait for 5 ns; d241 3 a243 3 sel <= '1'; addr <= "00"; wait for 5 ns; nRD <= '0'; wait for 100 ns; data <= d_out; nRD <= '1'; wait for 5 ns; d248 3 a250 3 sel <= '1'; addr <= "01"; d_in <= NOP; wait for 5 ns; nWR <= '0'; wait for 100 ns; nWR <= '1'; wait for 5 ns; d258 1 a258 1 spi_din <= '1'; wait for 144.8 us; d270 1 a270 1 spi_din <= '1'; wait for 8 us; d284 1 a284 1 spi_din <= '1'; wait for 8.160 us; d298 1 a298 1 spi_din <= '1'; wait for 640 ns; d334 1 a334 1 spi_din <= '1'; wait for 640 ns; d346 1 a346 1 spi_din <= '1'; wait for 800 ns; d358 1 a358 1 spi_din <= '1'; wait for 800 ns; d370 1 a370 1 spi_din <= '1'; wait for 800 ns; d382 1 a382 1 spi_din <= '1'; wait for 800 ns; d394 1 a394 1 spi_din <= '1'; wait for 800 ns; a410 3 @ 1.1.1.1 log @no message @ text @@