head 1.1; access; symbols; locks; strict; comment @# @; 1.1 date 2007.02.07.08.06.26; author jcarr; state Exp; branches; next ; commitid 39c245c988604567; desc @@ 1.1 log @initial import. This is only halfway converted from vhdl to verilog @ text @verilog work "source/sync.v" verilog work "source/disp_dec.v" verilog work "source/wb_7seg.v" verilog work "source/pcidec.v" verilog work "source/pcidmux.v" verilog work "source/pciwbsequ.v" verilog work "source/pcipargen.v" vhdl work "source/pciwbsequ.vhd" vhdl work "source/pfs.vhd" vhdl work "source/new_pciregs.vhd" vhdl work "source/pcipargen.vhd" vhdl work "source/new_pci32tlite.vhd" vhdl work "source/vga_main.vhd" vhdl work "source/top_pci_7seg.vhd" @