head 1.2;
access;
symbols
initial_import:1.1.1.1 pci_blue_interface:1.1.1;
locks; strict;
comment @# @;
1.2
date 2001.07.06.10.50.59; author bbeaver; state Exp;
branches;
next 1.1;
1.1
date 2001.02.21.15.27.29; author bbeaver; state Exp;
branches
1.1.1.1;
next ;
1.1.1.1
date 2001.02.21.15.27.29; author bbeaver; state Exp;
branches;
next ;
desc
@@
1.2
log
@Massive edit to start changing many `defines into Parameters.
This MIGHT (?) make it possible to have more than 1 PCI interface,
but with different bus sizes.
On the other hand, it might be an idiotic change in style.
@
text
@
pci_blue_submodule_test\test_pci_fifos.v
pci_blue_fifos\pci_blue_fifos.v
pci_blue_fifos\pci_blue_fifo_flags.v
pci_vendor_lib\pci_vendor_lib.v
C:\SYNAPTICAD.7.4\
C:\SYNAPTICAD\
C:\VLOGGER\
pci_blue_include\
C:\free_ip\pci_blue_interface\
C:\SYNAPTICAD.7.4\lib\verilog\
C:\SYNAPTICAD\lib\verilog\
C:\VLOGGER\lib\verilog\
.v
.vo
.vh
VerboseSamples
VerboseSequenceVerification
VerboseDelays
VerboseFileInput
SampleIf
SampleThen
SampleElse
SignalDirection
GenerateSampleHdlCode
GenerateMarkerHdlCode
GenerateDelayHdlCode
ExecuteFromTopLevel
CycleClock
CycleClockEdge
VerilogTimeOutLength
VhdlTimeOutLength
SystemCTimeOutLength
VeraTimeOutLength
VerilogIncludeDelayTime
VhdlIncludeDelayTime
SystemCIncludeDelayTime
VeraIncludeDelayTime
VerilogSignalType
VhdlSignalType
SystemCSignalType
VhdlGenerateAbortCode
SystemCGenerateAbortCode
@
1.1
log
@Initial revision
@
text
@d2 7
a8 1
d10 1
d14 1
a15 6
pci_blue_fifos\test_pci_fifos.v
pci_blue_fifos\pci_blue_fifos.v
pci_blue_fifos\pci_blue_fifo_flags.v
pci_vendor_lib\pci_vendor_lib.v
d17 1
d26 32
@
1.1.1.1
log
@Initial Import of pci_blue_interface
Only the behaviorial code works
There is no synthesizable code in this initial source import
@
text
@@