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1.1
date 2003.02.10.04.04.49; author doru; state Exp;
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Stall and Flush Unit
The pipeline controls its own stall and flush status, through specific stall and flush-related request signals. These requests are sent to the Stall and Flush Unit (SFU). The output of the SFU is a set of signals that directly control pipeline stages (a stall and flush control signals pair for each stage):
Requests to SFU
stall requests
The SFU stalls all younger stages. However, by stalling-only, the current instruction is spawned into 2 instances. One of them must be killed (flushed). The the younger instance is killed (the previous stage is flushed).
Thus, a nop is introduced in the pipeline before the instruction wavefront.
If more than one stage request a stall at the same time, the older one has priority (the younger one will be stalled along with the others). Only after that, the younger one will be ackowledged its stall by means of appropriate stall and flush control signals.
Stall requests:
pavr_s3_stall_rq
pavr_s5_stall_rq
pavr_s6_stall_rq
flush requests
The SFU simply flushes that stage.
More than one flush could be acknolewdged at the same time, without competition. However, all flush requests happen to request to flush the same pipeline stage, s2.
Flush requests:
pavr_s3_flush_s2_rq
pavr_s4_flush_s2_rq
pavr_s4_ret_flush_s2_rq
pavr_s5_ret_flush_s2_rq
pavr_s51_ret_flush_s2_rq
pavr_s52_ret_flush_s2_rq
pavr_s53_ret_flush_s2_rq
pavr_s54_ret_flush_s2_rq
pavr_s55_ret_flush_s2_rq
branch requests
The SFU flushes stages s2...s5, because the corresponding instructions were already uselessly fetched, and requests the PC to be loaded with the branch relative jump address.
Branch requests:
pavr_s6_branch_rq
skip requests
The SFU treats skips as branches that have the relative jump address equal to 0, 1 or 2, depending on the skip condition and on next instruction's length (16/32 bits).
Skip requests:
pavr_s6_skip_rq
pavr_s61_skip_rq
nop requests
The SFU stalls all younger instructions. The current instruction is spawned into 2 instances. The older instance is killed (the very same stage that requested the nop stage is flushed).
Thus, a nop is introduced in the pipeline after the instruction wavefront.
In order to do that, a micro-state machine is needed outside the pipeline, because otherwise that stage would undefinitely stall itself.
Nop requests:
pavr_s4_nop_rq
SFU control signals
Each main pipeline stage (s1-s6) has 2 kinds of control signals, that are generated by the SFU:
stall control
All registers in this stage are instructed to remain unchanged All possible requests to hardware resources (such as RF, IOF, BPU, DACU, SREG, etc) are reseted (to 0).
flush control
All registers in this stage are reseted (to 0), to a most "benign" state (a nop). Also, all requests to hardware resources are reseted.
Each main pipeline stage has an associated flag that determines whether or not that stage has the right to access hardware resources. These flags are also managed by the SFU.
Hardware resources enabling flags:
pavr_s1_hwrq_en
pavr_s2_hwrq_en
pavr_s3_hwrq_en
pavr_s4_hwrq_en
pavr_s5_hwrq_en
pavr_s6_hwrq_en
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by
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