head 1.1; branch 1.1.1; access ; symbols noReleaseTag:1.1.1.1 noVendorName:1.1.1; locks ; strict; comment @# @; 1.1 date 2003.02.10.04.04.59; author doru; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2003.02.10.04.04.59; author doru; state Exp; branches ; next ; desc @@ 1.1 log @Initial revision @ text @ External interrupt 0
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External interrupt 0
[Peripherals]

Features
External interrupt 0 is physically mapped on the line 0 (bit 0) of port A.

Its associated interrupt flag resides into the IO File register GIFR (General Interrupt Flags Register):

pavr_hwres_iof_perif_int0_01.gif

External interrupt 0 is enabled/disabled by setting/clearing bit 6 in GIMSK (General Interrupt Mask) register:

pavr_hwres_iof_perif_int0_02.gif

If enabled, it can trigger an interrupt on high-to-low transition, low-to-high transition, or on a low level of the interrupt 0 input. This behavior is defined by 2 bits in the MCUCR (Microcontroller Control) register:

pavr_hwres_iof_perif_int0_03.gif

Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by doxygen1.2.16
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