head 1.2; access; symbols arelease:1.1.1.1 avendor:1.1.1; locks; strict; comment @# @; 1.2 date 2006.04.19.09.57.06; author tmsiqueira; state dead; branches; next 1.1; commitid 3ebb444609704567; 1.1 date 2006.04.19.09.25.23; author tmsiqueira; state Exp; branches 1.1.1.1; next ; commitid 3033444601ff4567; 1.1.1.1 date 2006.04.19.09.25.23; author tmsiqueira; state Exp; branches; next ; commitid 3033444601ff4567; desc @@ 1.2 log @no message @ text @JDF G // Created by Project Navigator ver 1.0 PROJECT ofdm DESIGN ofdm DEVFAM spartan2 DEVFAMTIME 1145426085 DEVICE xc2s200 DEVICETIME 1145426085 DEVPKG pq208 DEVPKGTIME 1145425004 DEVSPEED -5 DEVSPEEDTIME 1145426085 DEVTOPLEVELMODULETYPE HDL TOPLEVELMODULETYPETIME 0 DEVSYNTHESISTOOL XST (VHDL/Verilog) SYNTHESISTOOLTIME 0 DEVSIMULATOR Other SIMULATORTIME 0 DEVGENERATEDSIMULATIONMODEL VHDL GENERATEDSIMULATIONMODELTIME 0 SOURCE modem.vhd SOURCE ram.vhd SOURCE mux.vhd SOURCE rxmodem.vhd SOURCE cfft.vhd SOURCE input.vhd SOURCE p2r_CordicPipe.vhd SOURCE txmodem.vhd SOURCE blockdram.vhd SOURCE conj.vhd SOURCE ofdm.vhd SOURCE mulfactor.vhd SOURCE counter.vhd SOURCE div4limit.vhd SOURCE cfft4.vhd SOURCE inv_control.vhd SOURCE ram_control.vhd SOURCE rofactor.vhd SOURCE mux_control.vhd SOURCE starts.vhd SOURCE txrx.vhd SOURCE cfft_control.vhd SOURCE io_control.vhd SOURCE output.vhd SOURCE p2r_cordic.vhd SOURCE sc_corproc.vhd [Normal] p_xstVerilog2001=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, True _SynthOptEffort=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, Normal _SynthResSharing=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, True [STRATEGY-LIST] Normal=True @ 1.1 log @Initial revision @ text @@ 1.1.1.1 log @no message @ text @@