head 1.6; access; symbols V3_0:1.5 Version_1_0:1.2 arelease:1.1.1.1 avendor:1.1.1; locks; strict; comment @# @; 1.6 date 2006.03.06.05.10.47; author rhoads; state dead; branches; next 1.5; commitid 2c39440bc44c4567; 1.5 date 2002.06.25.03.43.33; author rhoads; state Exp; branches; next 1.4; 1.4 date 2002.02.06.21.34.09; author rhoads; state Exp; branches; next 1.3; 1.3 date 2002.01.16.04.00.25; author rhoads; state Exp; branches; next 1.2; 1.2 date 2001.05.17.22.23.20; author rhoads; state Exp; branches; next 1.1; 1.1 date 2001.05.17.21.22.50; author rhoads; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2001.05.17.21.22.50; author rhoads; state Exp; branches; next ; desc @@ 1.6 log @Major changes -- updated to Plasma Version 3 @ text @removed from CVS @ 1.5 log @removed content @ text @@ 1.4 log @Changed name to M-lite to avoid trademark issues. @ text @d1 1 a1 480 OPENCORES project: M-lite CPU core -- executes MIPS I(tm) opcodes
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    Overview | Wishlist

    Project: M-lite CPU core -- executes MIPS I(tm) opcodes

    Details

    Category: Microprocessor
    Last updated: 6/2/2002
    Created: 25/9/2001
    Wishbone compliant core: No
    Stage: Production/Stable
    Mailing list: Cores

    Description

    M-lite is a "clean room" VHDL implementation of a CPU. It supports the MIPS I(tm) instruction set with a two-stage pipeline. Interrupts and User Mode instructions are supported.

    MIPS I(tm) is a registered trademark of MIPS Technologies. MIPS Technologies does not endorse and is not associated with this project.

    Block diagram

    Example Instruction

    As an example, an ADD instruction would take the following steps:

      1.The "pc_next" entity would pass the program counter (PC) to the "mem_ctrl" entity. [First Stage of Pipeline]
      2."Mem_ctrl" passes the opcode to the "control" entity.
      3."Control" converts the 32-bit opcode to a 60-bit VLWI opcode and sends control signals to the other entities.
      4.Based on the rs_index and rt_index control signals, "reg_bank" sends the 32-bit reg_source and reg_target to "bus_mux".
      5.Based on the a_source and b_source control signals, "bus_mux" multiplexes reg_source onto a_bus and reg_target onto b_bus.
      6.Based on the alu_func control signals, "alu" adds the values from a_bus and b_bus and places the result on c_bus.
      7.Based on the c_source control signals, "bus_bux" multiplexes c_bus onto reg_dest.
      8.Based on the rd_index control signal, "reg_bank" saves reg_dest into the correct register.

    Features

    The CPU is implemented as a two-stage pipeline with step #1 in the first stage and steps #2-8 occurring the second stage. Most instructions take one clock cycle. Interrupts are supported. A four cycle memory write is also supported for non-clocked memories.

    There are several control lines not shown in the diagram. A pause (wait-state) line will cause the pipeline to pause if the multiplication results are accessed before the multiplication is complete.

    Supporting Documentation

    The implementation is based on information found in:

    • "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich and
    • "The Designer's Guide to VHDL" by Peter J. Ashenden
    In addition, the MIPS I(tm) instruction set can be found by going to http://www.mips.com/ and then following the links to "Documentation", "Architecture Programming Publications for MIPS32(tm)", and "MIPS32(TM) Architecture for Programmers Volume II: The MIPS32(TM) Instruction Set".

    Tools

    The tools used include VHDL Synopsys, ModelTech, the free VHDL simulator from Symphony, and the GCC compiler (121 KB for Windows PC host, MIPS(tm) target; optimization -O doesn't work).

    Registers

    All of the registers are clocked by the single master clock. The registers used in the design are grouped by entity and listed below: 

     

                mem_ctrl

                ===========================================

                |    Register Name    |   Type    | Width |

                ===========================================

                |   next_opcode_reg   | Flip-flop |  32   |

                |   opcode_reg        | Flip-flop |  32   |

                |   setup_done_reg    | Flip-flop |   1   |

                ===========================================

    

                mlite_cpu

                ===========================================

                |    Register Name    |   Type    | Width |

                ===========================================

                |   intr_signal       | Flip-flop |   1   |

                |   reset_reg         | Flip-flop |   1   |

                ===========================================

                            

                mult

                ===========================================

                |    Register Name    |   Type    | Width |

                ===========================================

                |   answer_reg        | Flip-flop |  32   |

                |    count_reg        | Flip-flop |   6   |

                |   do_div_reg        | Flip-flop |   1   |

                |  do_signed_reg      | Flip-flop |   1   |

                |      reg_a          | Flip-flop |  32   |

                |      reg_b          | Flip-flop |  64   |

                ===========================================

                            

                pc_next

                ===========================================

                |    Register Name    |   Type    | Width |

                ===========================================

                |     pc_reg          | Flip-flop |  30   |

                ===========================================

                        

                reg_bank (configured to optionally used dual port memory)

                ===========================================

                |    Register Name    |   Type    | Width |

                ===========================================

                |      reg00_reg      | Flip-flop |  32   |

                |         ...                             |

                |      reg31_reg      | Flip-flop |  32   |

                |   reg_status_reg    | Flip-flop |   1   |

                ===========================================

    Preliminary Synthesis

    The CPU core was synthesized for 0.13 um line widths with a predicted area less than 0.2 millimeters squared. The predicted maximum latency was less than 6 ns for a maximum clock speed of 150 MHz.

    A preliminary synthesis yields the following cells and die area. If one assumes that a standard cell is composed of three gates, then this is approximately a 20K gate design. It is interesting to note that the register bank requires over 60% of the area. 


            Block    ports   nets  cells cell_area   ~%   delay(ns)

            ------   -----   ----  ----- ---------  ---   ---------

            alu        101    919    850      7503   12        1.11

            bus_mux    283    672    486      4906    8        0.35

            control     93    296    263      2250    4        0.29

            mem_ctrl   271    455    318      3299    5        0.95

            mult       101   1111   1043      9342   15        0.72

            pc_next     94    277    215      1756    3        0.15

            reg_bank   116   2650   2599     39477   62        1.02

            shifter     71    423    384      3026    5        1.51

            mlite_cpu  201    555     45     63888  100        5.61

                    

            total     1331   7358   6203

    List of Files

      FILE PURPOSE
      makefile Makefile for the PC based VHDL simulator
      code.txt Input opcodes for the test bench -- test.exe "converted"
      alu.vhd Arithmetic Logic Unit
      bus_mux.vhd BUS Multiplex Unit
      control.vhd Opcode Decoder
      mem_ctrl.vhd Memory Controller
      mlite_cpu.vhd Top Level VHDL for M-lite CPU
      mlite_pack.vhd Constants and Functions Package
      mult.vhd Multiplication and Division Unit
      pc_next.vhd Program Counter Unit
      ram.vhd RAM for the Test Bench
      reg_bank.vhd Register Bank for 32, 32-bit Registers
      shifter.vhd Shifter Unit
      tbench.vhd Test Bench that uses mlite_vpu.vhd and ram.vhd
      makefile Makefile for the PC for creating "code.txt"
      boot.asm Initializes $gp and $sp, clears .bss
      opcodes.asm Tests all the MIPS I(tm) opcodes
      convert.c Converts test.exe to code.txt
      mlite.c Simulates the CPU in software
      test.c Test program (opcodes) for the M-lite CPU
      pi.c Calculates the first 16 digits of PI
      count.c Test program that counts using words
      output.txt Output from the test bench
      index.shtml Old copy of this help file
      cpu.gif Block Diagram

    Downloads

    DateDescriptionLink
    6/2/2002Entire M-lite project (~50 KB)
    		mips

    Convert

    The program "convert" changes the file "test.exe" into the HEX file "code.txt". The register $gp is initialized, and the .bss segment is cleared.

    Big/Little Endian

    The M-lite CPU operates in Big Endian mode by default. To operate in Little Endian mode, change "little_endian" from "00" to "11" in the file mem_ctrl.vhd.

    Legal Notice

    MIPS(tm) and MIPS I(tm) are registered trademarks of MIPS Technologies, Inc. MIPS Technologies does not endorse and is not associated with this project. If you use this core you are responsible for all legal issues. This "clean room" implementation of a CPU which executes MIPS(tm) opcodes does not negate MIPS Technologies, Inc. of their trademark, copyrights, or patents....

    Free for commercial and non-commercial use as long as the author and warning notices are maintained.

    This software is provided by Steve Rhoads "as is" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed. In no event shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or consequential damages (including, but not limited to, procurement of substitute goods or services; loss of use, data, or profits; or business interruption) however caused and on any theory of liability, whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way out of the use of this software, even if advised of the possibility of such damage.

    Bus Interface

    All signals are active high. Writing to memory normally takes four cycles to meet address hold times. Addresses with mem_address(31)='1' take two cycles (assumed to be clocked). Below are the signals for writing a character to address 0xffff: 


            entity mlite_cpu is

               port(clk         : in std_logic;

                    reset_in    : in std_logic;

                    intr_in     : in std_logic;

            

                    mem_address : out std_logic_vector(31 downto 0);

                    mem_data_w  : out std_logic_vector(31 downto 0);

                    mem_data_r  : in std_logic_vector(31 downto 0);

                    mem_byte_sel: out std_logic_vector(3 downto 0);

                    mem_write   : out std_logic;

                    mem_pause   : in std_logic);

            end; --entity mlite_cpu

    

    

          mem_write

        interrupt                     mem_byte_sel

          reset                        mem_pause

           ns    mem_address m_data_w m_data_r

       ===========================================

         6700 0 0 0 000002A4 ZZZZZZZZ A0AE0000 0 0  (  fetch write opcode)

         6800 0 0 0 000002B0 ZZZZZZZZ 0443FFF6 0 0  (1 fetch NEXT opcode)

         6900 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 0  (2 address hold)

         7000 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 1  (3 write the low byte)

         7100 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 0  (4 address hold)

         7200 0 0 0 000002B4 ZZZZZZZZ 00441806 0 0  (  execute NEXT opcode)

    Status

    • All MIPS I(tm) instructions are implemented and tested with the following limitations (exceptions not supported; all 32-bit memory accesses must be long word aligned)
    • See "opcodes.asm" for regression test.
    • Tested with several C programs: Calculating PI; Prime Numbers; Showing Numbers Using Words.
    • Supports Interrupts
    • Runs in a Xilinx FPGA

    Maintainers

                                                                                                                                        


    		 
    webmaster
    		  
    Administrative contact: administration@@opencores.org
    Copyright ©1999-2001 OPENCORES.ORG. All rights reserved.
    @ 1.3 log @Updated from opencores.org @ text @d45 1 a45 1 project: MIPS-lite core d129 1 d207 1 a207 1 d214 1 a214 1 Overview d223 4 a226 4 Project: MIPS-lite core

    Details

    Category: Microprocessor
    Last updated: 16/1/2002
    Created: 25/9/2001
    Wishbone compliant core: No
    Stage: Production/Stable
    Mailing list: Cores

    Description

    MIPS-lite is a "clean room" VHDL implementation of a MIPS CPU. It supports the MIPS I instruction set with a two-stage pipeline. Interrupts and User Mode instructions are supported.

    Block diagram

    Example Instruction

    As an example, an ADD instruction would take the following steps: d236 1 a236 2

    Features

    The CPU is implemented as a two-stage pipeline with step #1 in the first stage and steps #2-8 occurring the second stage. Most instructions take one clock cycle. Interrupts are supported. A four cycle memory write is also supported for non-clocked memories. d238 1 a238 2
    There are several control lines not shown in the diagram. A pause (wait-state) line will cause the pipeline to pause if the multiplication results are accessed before the multiplication is complete.

    Supporting Documentation

    The implementation is based on information found in: d242 3 a244 3

  • MIPS32(TM) Architecture for Programmers Volume II: The MIPS32(TM) Instruction Set

    • Tools

    The tools used include VHDL Synopsys, ModelTech, the free VHDL simulator from Symphony, and the GCC compiler (121 KB for Windows PC host, MIPS target; optimization -O doesn't work). d246 1 a246 2

    Registers

    All of the registers are clocked by the single master clock. The registers used in the design are grouped by entity and listed below: d258 1 a258 1
    mips_cpu d285 1 a285 1
    reg_bank (configured to used dual port memory) d295 1 a295 2

    Preliminary Synthesis

    The CPU core was synthesized for 0.13 um line widths with a predicted area less than 0.2 millimeters squared. The predicted maximum latency was less than 6 ns for a maximum clock speed of 150 MHz. d309 1 a309 1
    mips_cpu 201 555 45 63888 100 5.61 d313 1 a313 2

    List of Files