head 1.8; access; symbols arelease:1.1.1.2 avendor:1.1.1; locks; strict; comment @# @; 1.8 date 2007.11.29.03.50.36; author mcupro; state Exp; branches; next 1.7; commitid 35ad474e33b34567; 1.7 date 2007.11.26.13.50.16; author mcupro; state Exp; branches; next 1.6; commitid 7bd9474ace7e4567; 1.6 date 2007.11.20.03.14.12; author mcupro; state Exp; branches; next 1.5; commitid 1b1f47424ffc4567; 1.5 date 2007.11.18.03.32.08; author mcupro; state Exp; branches; next 1.4; commitid 4838473fb2364567; 1.4 date 2007.11.18.02.26.12; author mcupro; state dead; branches; next 1.3; commitid 3c13473fa2c24567; 1.3 date 2007.11.13.11.16.04; author mcupro; state Exp; branches; next 1.2; commitid 7b32473987714567; 1.2 date 2007.11.05.22.39.26; author mcupro; state Exp; branches; next 1.1; commitid 258472f9b984567; 1.1 date 2007.10.13.08.31.13; author mcupro; state Exp; branches 1.1.1.1; next ; commitid 710f4710817c4567; 1.1.1.1 date 2007.10.13.08.31.13; author mcupro; state Exp; branches; next 1.1.1.2; commitid 710f4710817c4567; 1.1.1.2 date 2007.11.18.02.59.59; author mcupro; state Exp; branches; next ; commitid 42be473faaa14567; desc @@ 1.8 log @no message @ text @#-- Synplicity, Inc. #-- Version Synplify Pro 8.1 #-- Project file F:\MIPS_bak\11_28_update\synplify_prj\mips789.prj #-- Written on Sat Nov 29 00:16:15 2008 #add_file options add_file -verilog "../rtl/verilog/EXEC_stage.v" add_file -verilog "../rtl/verilog/RF_components.v" add_file -verilog "../rtl/verilog/RF_stage.v" add_file -verilog "../rtl/verilog/ctl_fsm.v" add_file -verilog "../rtl/verilog/decode_pipe.v" add_file -verilog "../rtl/verilog/dvc.v" add_file -verilog "../rtl/verilog/forward.v" add_file -verilog "../rtl/verilog/mem_module.v" add_file -verilog "../rtl/verilog/mips_core.v" add_file -verilog "../rtl/verilog/mips_dvc.v" add_file -verilog "../rtl/verilog/mips_sys.v" add_file -verilog "../rtl/verilog/mips_uart.v" add_file -verilog "../rtl/verilog/ulit.v" add_file -verilog "../rtl/verilog/altera/fifo512_cyclone.v" add_file -verilog "../rtl/verilog/mips789_defs.v" add_file -verilog "../rtl/verilog/mips_top.v" add_file -verilog "../rtl/verilog/ram_module.v" add_file -verilog "../rtl/verilog/altera/pll50.v" add_file -verilog "../rtl/verilog/altera/ram2048x8_0.v" add_file -verilog "../rtl/verilog/altera/ram2048x8_1.v" add_file -verilog "../rtl/verilog/altera/ram2048x8_2.v" add_file -verilog "../rtl/verilog/altera/ram2048x8_3.v" #implementation: "rev_1" impl -add rev_1 #device options set_option -technology CYCLONE set_option -part EP1C6 set_option -package QC240 set_option -speed_grade -6 #compilation/mapping options set_option -default_enum_encoding onehot set_option -symbolic_fsm_compiler 1 set_option -resource_sharing 1 set_option -use_fsm_explorer 1 set_option -top_module "mips_top" #map options set_option -frequency auto set_option -run_prop_extract 0 set_option -fanout_limit 30 set_option -disable_io_insertion 0 set_option -verification_mode 0 set_option -pipe 1 set_option -update_models_cp 0 set_option -retiming 1 set_option -fixgatedclocks 0 set_option -no_sequential_opt 0 #simulation options set_option -write_verilog 0 set_option -write_vhdl 0 #VIF options set_option -write_vif 1 #automatic place and route (vendor) options set_option -write_apr_constraint 1 #set result format/file last project -result_file "rev_1/mips_top.vqm" # #implementation attributes set_option -vlog_std v2001 set_option -dup 0 set_option -project_relative_includes 1 #par_1 attributes set_option -job par_1 -add par set_option -job par_1 -option run_backannotation 0 impl -active "rev_1" @ 1.7 log @no message @ text @d3 2 a4 2 #-- Project file F:\mips789\synplify_prj\mips789.prj #-- Written on Tue Nov 25 18:51:24 2008 d44 2 a45 2 set_option -resource_sharing 0 set_option -use_fsm_explorer 0 d56 1 a56 1 set_option -retiming 0 @ 1.6 log @no message @ text @d3 2 a4 2 #-- Project file G:\mips789\synplify_prj\mips789.prj #-- Written on Thu Nov 20 08:57:16 2008 d23 7 d45 2 a46 2 set_option -use_fsm_explorer 1 set_option -top_module "mips_sys" d54 1 a54 1 set_option -pipe 0 d71 1 a71 1 project -result_file "rev_1/mips_sys.vqm" @ 1.5 log @*** empty log message *** @ text @d3 2 a4 2 #-- Project file E:\mips789\synplify_prj\mips789.prj #-- Written on Thu Nov 13 18:11:19 2008 d37 1 a37 1 set_option -resource_sharing 1 d47 1 a47 1 set_option -pipe 1 d49 1 a49 1 set_option -retiming 1 @ 1.4 log @no message @ text @@ 1.3 log @no message @ text @@ 1.2 log @no message @ text @d3 2 a4 2 #-- Project file E:\mips789\mips789\synplify_prj\mips789.prj #-- Written on Mon Nov 03 10:10:18 2008 a13 1 add_file -verilog "../rtl/verilog/fifo.v" a19 2 add_file -verilog "../rtl/verilog/ram_module.v" add_file -verilog "../rtl/verilog/sim_ram.v" d22 1 d42 1 a42 1 set_option -frequency 50.000 @ 1.1 log @Initial revision @ text @d4 1 a4 1 #-- Written on Sun Oct 12 23:56:39 2008 @ 1.1.1.1 log @no message @ text @@ 1.1.1.2 log @no message @ text @d3 2 a4 2 #-- Project file E:\mips789\synplify_prj\mips789.prj #-- Written on Thu Nov 13 18:11:19 2008 d14 1 d21 2 a24 1 add_file -verilog "../rtl/verilog/mips789_defs.v" d44 1 a44 1 set_option -frequency auto @