head 1.7; access; symbols arelease:1.1.1.2 avendor:1.1.1; locks; strict; comment @# @; 1.7 date 2007.11.29.03.50.35; author mcupro; state Exp; branches; next 1.6; commitid 35ad474e33b34567; 1.6 date 2007.11.26.13.42.59; author mcupro; state Exp; branches; next 1.5; commitid 7971474acd584567; 1.5 date 2007.11.18.03.32.44; author mcupro; state Exp; branches; next 1.4; commitid 4860473fb2554567; 1.4 date 2007.11.18.02.32.28; author mcupro; state dead; branches; next 1.3; commitid 3e01473fa43a4567; 1.3 date 2007.11.13.11.09.46; author mcupro; state Exp; branches; next 1.2; commitid 77f9473985f74567; 1.2 date 2007.11.05.22.42.51; author mcupro; state Exp; branches; next 1.1; commitid 329472f9c5b4567; 1.1 date 2007.10.13.08.42.02; author mcupro; state Exp; branches 1.1.1.1; next ; commitid 710f4710817c4567; 1.1.1.1 date 2007.10.13.08.42.02; author mcupro; state Exp; branches; next 1.1.1.2; commitid 710f4710817c4567; 1.1.1.2 date 2007.11.18.03.01.26; author mcupro; state Exp; branches; next ; commitid 42be473faaa14567; desc @@ 1.7 log @no message @ text @# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any other # associated documentation or information provided by Altera or a partner # under Altera's Megafunction Partnership Program may be used only # to program PLD devices (but not masked PLD devices) from Altera. Any # other use of such megafunction design, netlist, support information, # device programming or simulation file, or any other related documentation # or information is prohibited for any other purpose, including, but not # limited to modification, reverse engineering, de-compiling, or use with # any other silicon devices, unless such use is explicitly licensed under # a separate agreement with Altera or a megafunction partner. Title to the # intellectual property, including patents, copyrights, trademarks, trade # secrets, or maskworks, embodied in any such megafunction design, netlist, # support information, device programming or simulation file, or any other # related documentation or information provided by Altera or a megafunction # partner, remains with Altera, the megafunction partner, or their respective # licensors. No other licenses, including any licenses needed under any third # party's intellectual property, are provided herein. # The default values for assignments are stored in the file # mips_top_assignment_defaults.qdf # If this file doesn't exist, and for assignments not listed, see file # assignment_defaults.qdf # Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # Project-Wide Assignments # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.2 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:21:32 NOVEMBER 24, 2008" set_global_assignment -name LAST_QUARTUS_VERSION 4.2 set_global_assignment -name VQM_FILE ../synplify_prj/rev_1/mips_top.vqm # Pin & Location Assignments # ========================== set_location_assignment PIN_28 -to clk set_location_assignment PIN_159 -to rst set_location_assignment PIN_156 -to key1 set_location_assignment PIN_158 -to key2 set_location_assignment PIN_1 -to led1 set_location_assignment PIN_2 -to led2 set_location_assignment PIN_177 -to ser_rxd set_location_assignment PIN_176 -to ser_txd set_location_assignment PIN_135 -to lcd_en set_location_assignment PIN_133 -to lcd_rs set_location_assignment PIN_134 -to lcd_rw set_location_assignment PIN_136 -to lcd_data[0] set_location_assignment PIN_137 -to lcd_data[1] set_location_assignment PIN_138 -to lcd_data[2] set_location_assignment PIN_139 -to lcd_data[3] set_location_assignment PIN_140 -to lcd_data[4] set_location_assignment PIN_141 -to lcd_data[5] set_location_assignment PIN_143 -to lcd_data[6] set_location_assignment PIN_144 -to lcd_data[7] set_location_assignment PIN_169 -to seg7led1[0] set_location_assignment PIN_166 -to seg7led1[1] set_location_assignment PIN_161 -to seg7led1[2] set_location_assignment PIN_160 -to seg7led1[3] set_location_assignment PIN_164 -to seg7led1[4] set_location_assignment PIN_168 -to seg7led1[5] set_location_assignment PIN_167 -to seg7led1[6] set_location_assignment PIN_175 -to seg7led2[0] set_location_assignment PIN_170 -to seg7led2[1] set_location_assignment PIN_163 -to seg7led2[2] set_location_assignment PIN_165 -to seg7led2[3] set_location_assignment PIN_162 -to seg7led2[4] set_location_assignment PIN_174 -to seg7led2[5] set_location_assignment PIN_173 -to seg7led2[6] # Analysis & Synthesis Assignments # ================================ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 set_global_assignment -name FAMILY Cyclone set_global_assignment -name TOP_LEVEL_ENTITY mips_top # Fitter Assignments # ================== set_global_assignment -name DEVICE EP1C6Q240C6 set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" # Assembler Assignments # ===================== set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" # Simulator Assignments # ===================== set_global_assignment -name GLITCH_INTERVAL "1 " # LogicLock Region Assignments # ============================ set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off @ 1.6 log @no message @ text @d39 36 @ 1.5 log @*** empty log message *** @ text @d35 1 a35 1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:48:42 NOVEMBER 13, 2008" d37 1 a37 44 set_global_assignment -name VQM_FILE ../synplify_prj/rev_1/mips_sys.vqm set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera/pll50.v set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera/ram2048x8_0.v set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera/ram2048x8_1.v set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera/ram2048x8_2.v set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera/ram2048x8_3.v set_global_assignment -name VERILOG_FILE ../rtl/verilog/mips_top.v set_global_assignment -name VERILOG_FILE ../rtl/verilog/ram_module.v # Pin & Location Assignments # ========================== set_location_assignment PIN_28 -to clk set_location_assignment PIN_159 -to rst set_location_assignment PIN_156 -to key1 set_location_assignment PIN_158 -to key2 set_location_assignment PIN_1 -to led1 set_location_assignment PIN_2 -to led2 set_location_assignment PIN_177 -to ser_rxd set_location_assignment PIN_176 -to ser_txd set_location_assignment PIN_135 -to lcd_en set_location_assignment PIN_133 -to lcd_rs set_location_assignment PIN_134 -to lcd_rw set_location_assignment PIN_136 -to lcd_data[0] set_location_assignment PIN_137 -to lcd_data[1] set_location_assignment PIN_138 -to lcd_data[2] set_location_assignment PIN_139 -to lcd_data[3] set_location_assignment PIN_140 -to lcd_data[4] set_location_assignment PIN_141 -to lcd_data[5] set_location_assignment PIN_143 -to lcd_data[6] set_location_assignment PIN_144 -to lcd_data[7] set_location_assignment PIN_169 -to seg7led1[0] set_location_assignment PIN_166 -to seg7led1[1] set_location_assignment PIN_161 -to seg7led1[2] set_location_assignment PIN_160 -to seg7led1[3] set_location_assignment PIN_164 -to seg7led1[4] set_location_assignment PIN_168 -to seg7led1[5] set_location_assignment PIN_167 -to seg7led1[6] set_location_assignment PIN_175 -to seg7led2[0] set_location_assignment PIN_170 -to seg7led2[1] set_location_assignment PIN_163 -to seg7led2[2] set_location_assignment PIN_165 -to seg7led2[3] set_location_assignment PIN_162 -to seg7led2[4] set_location_assignment PIN_174 -to seg7led2[5] set_location_assignment PIN_173 -to seg7led2[6] d51 4 d57 1 a57 1 set_global_assignment -name GLITCH_INTERVAL 1 @ 1.4 log @no message @ text @@ 1.3 log @no message @ text @@ 1.2 log @no message @ text @d35 1 a35 1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:12:58 NOVEMBER 03, 2008" a37 4 set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera/mips_top.v set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera/pll25.v set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera/pll40.v set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera/pll45.v a38 1 set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera/pll75.v d43 38 a80 1 set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera/ram_module.v d85 1 d92 1 d96 1 a96 1 set_global_assignment -name GLITCH_INTERVAL "1 " @ 1.1 log @Initial revision @ text @d35 1 a35 1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:53 OCTOBER 12, 2008" a49 117 # Pin & Location Assignments # ========================== set_location_assignment PIN_28 -to clk set_location_assignment PIN_159 -to rst set_location_assignment PIN_156 -to key1 set_location_assignment PIN_158 -to key2 set_location_assignment PIN_1 -to led1 set_location_assignment PIN_2 -to led2 set_location_assignment PIN_177 -to ser_rxd set_location_assignment PIN_176 -to ser_txd set_location_assignment PIN_135 -to lcd_en set_location_assignment PIN_133 -to lcd_rs set_location_assignment PIN_134 -to lcd_rw set_location_assignment PIN_136 -to lcd_data[0] set_location_assignment PIN_137 -to lcd_data[1] set_location_assignment PIN_138 -to lcd_data[2] set_location_assignment PIN_139 -to lcd_data[3] set_location_assignment PIN_140 -to lcd_data[4] set_location_assignment PIN_141 -to lcd_data[5] set_location_assignment PIN_143 -to lcd_data[6] set_location_assignment PIN_144 -to lcd_data[7] set_location_assignment PIN_169 -to seg7led1[0] set_location_assignment PIN_166 -to seg7led1[1] set_location_assignment PIN_161 -to seg7led1[2] set_location_assignment PIN_160 -to seg7led1[3] set_location_assignment PIN_164 -to seg7led1[4] set_location_assignment PIN_168 -to seg7led1[5] set_location_assignment PIN_167 -to seg7led1[6] set_location_assignment PIN_175 -to seg7led2[0] set_location_assignment PIN_170 -to seg7led2[1] set_location_assignment PIN_163 -to seg7led2[2] set_location_assignment PIN_165 -to seg7led2[3] set_location_assignment PIN_162 -to seg7led2[4] set_location_assignment PIN_174 -to seg7led2[5] set_location_assignment PIN_173 -to seg7led2[6] set_location_assignment PIN_128 -to uart_rxd_usb set_location_assignment PIN_131 -to uart_txd_usb set_location_assignment PIN_60 -to sd_data[0] set_location_assignment PIN_59 -to sd_data[1] set_location_assignment PIN_58 -to sd_data[2] set_location_assignment PIN_57 -to sd_data[3] set_location_assignment PIN_56 -to sd_data[4] set_location_assignment PIN_55 -to sd_data[5] set_location_assignment PIN_54 -to sd_data[6] set_location_assignment PIN_53 -to sd_data[7] set_location_assignment PIN_12 -to sd_data[8] set_location_assignment PIN_11 -to sd_data[9] set_location_assignment PIN_8 -to sd_data[10] set_location_assignment PIN_7 -to sd_data[11] set_location_assignment PIN_6 -to sd_data[12] set_location_assignment PIN_5 -to sd_data[13] set_location_assignment PIN_4 -to sd_data[14] set_location_assignment PIN_3 -to sd_data[15] set_location_assignment PIN_42 -to sd_addr[0] set_location_assignment PIN_41 -to sd_addr[1] set_location_assignment PIN_39 -to sd_addr[2] set_location_assignment PIN_38 -to sd_addr[3] set_location_assignment PIN_23 -to sd_addr[4] set_location_assignment PIN_21 -to sd_addr[5] set_location_assignment PIN_20 -to sd_addr[6] set_location_assignment PIN_19 -to sd_addr[7] set_location_assignment PIN_18 -to sd_addr[8] set_location_assignment PIN_17 -to sd_addr[9] set_location_assignment PIN_43 -to sd_addr[10] set_location_assignment PIN_16 -to sd_addr[11] set_location_assignment PIN_45 -to sd_ba[0] set_location_assignment PIN_44 -to sd_ba[1] set_location_assignment PIN_50 -to sd_dqm[0] set_location_assignment PIN_13 -to sd_dqm[1] set_location_assignment PIN_46 -to sd_cs set_location_assignment PIN_47 -to sd_ras set_location_assignment PIN_48 -to sd_cas set_location_assignment PIN_49 -to sd_we set_location_assignment PIN_15 -to sd_cke set_location_assignment PIN_14 -to sd_clk set_location_assignment PIN_208 -to FLASH_CE set_location_assignment PIN_213 -to FLASH_OE set_location_assignment PIN_206 -to FLASH_WE set_location_assignment PIN_196 -to FLASH_RESET set_location_assignment PIN_223 -to FLASH_BYTE set_location_assignment PIN_207 -to FLASH_ADDR[0] set_location_assignment PIN_181 -to FLASH_ADDR[1] set_location_assignment PIN_182 -to FLASH_ADDR[2] set_location_assignment PIN_183 -to FLASH_ADDR[3] set_location_assignment PIN_184 -to FLASH_ADDR[4] set_location_assignment PIN_185 -to FLASH_ADDR[5] set_location_assignment PIN_186 -to FLASH_ADDR[6] set_location_assignment PIN_187 -to FLASH_ADDR[7] set_location_assignment PIN_204 -to FLASH_ADDR[8] set_location_assignment PIN_203 -to FLASH_ADDR[9] set_location_assignment PIN_202 -to FLASH_ADDR[10] set_location_assignment PIN_201 -to FLASH_ADDR[11] set_location_assignment PIN_200 -to FLASH_ADDR[12] set_location_assignment PIN_199 -to FLASH_ADDR[13] set_location_assignment PIN_198 -to FLASH_ADDR[14] set_location_assignment PIN_197 -to FLASH_ADDR[15] set_location_assignment PIN_222 -to FLASH_ADDR[16] set_location_assignment PIN_188 -to FLASH_ADDR[17] set_location_assignment PIN_193 -to FLASH_ADDR[18] set_location_assignment PIN_205 -to FLASH_ADDR[19] set_location_assignment PIN_214 -to FLASH_DQ[0] set_location_assignment PIN_216 -to FLASH_DQ[1] set_location_assignment PIN_218 -to FLASH_DQ[2] set_location_assignment PIN_220 -to FLASH_DQ[3] set_location_assignment PIN_235 -to FLASH_DQ[4] set_location_assignment PIN_233 -to FLASH_DQ[5] set_location_assignment PIN_227 -to FLASH_DQ[6] set_location_assignment PIN_225 -to FLASH_DQ[7] set_location_assignment PIN_215 -to FLASH_DQ[8] set_location_assignment PIN_217 -to FLASH_DQ[9] set_location_assignment PIN_219 -to FLASH_DQ[10] set_location_assignment PIN_221 -to FLASH_DQ[11] set_location_assignment PIN_234 -to FLASH_DQ[12] set_location_assignment PIN_228 -to FLASH_DQ[13] set_location_assignment PIN_226 -to FLASH_DQ[14] set_location_assignment PIN_224 -to FLASH_DQ[15] d52 1 a58 5 set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" # Assembler Assignments # ===================== set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" @ 1.1.1.1 log @no message @ text @@ 1.1.1.2 log @no message @ text @d35 1 a35 1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:48:42 NOVEMBER 13, 2008" d38 4 d43 1 d48 1 a48 2 set_global_assignment -name VERILOG_FILE ../rtl/verilog/mips_top.v set_global_assignment -name VERILOG_FILE ../rtl/verilog/ram_module.v d85 81 a168 2 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 d177 4 d183 1 a183 1 set_global_assignment -name GLITCH_INTERVAL 1 @