head 1.3; access; symbols ver_tag:1.1.1.1 vendor_tag:1.1.1; locks; strict; comment @# @; 1.3 date 2008.07.02.15.12.22; author dimo; state Exp; branches; next 1.2; commitid 2320486b9acf4567; 1.2 date 2008.06.27.17.41.49; author dimo; state Exp; branches; next 1.1; commitid 7a08486526444567; 1.1 date 2008.06.23.19.58.00; author dimo; state Exp; branches 1.1.1.1; next ; commitid 1b3f4860003f4567; 1.1.1.1 date 2008.06.23.19.58.00; author dimo; state Exp; branches; next ; commitid 1b3f4860003f4567; desc @@ 1.3 log @updated @ text @library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; USE work.cpu_types.ALL; entity pc is port( clk, rst : IN std_logic; -- high-active asynch rst addr_in : in d_bus; -- new address control : IN opcode; -- extend the control from the CU pc : OUT d_bus ); end pc; architecture behavioral of pc is begin pc_p: process(clk) VARIABLE pc_int : d_bus; BEGIN IF clk'EVENT AND clk='1' THEN if rst='1' then pc_int := zero_bus; else CASE control IS -- WHEN nop | neg_s | and_s | exor_s | or_s | sra_s | ror_s | add_s | addc_s | sta_1 => pc_int := pc_int + 1; WHEN jmp_2 | jmpc_2 | jmpz_2 => pc_int := addr_in; -- WHEN lda_addr_2 | ldb_addr_2 => null; WHEN jnt => pc_int := std_logic_vector(unsigned(unsigned(pc_int) + to_unsigned(2,d_bus_width))); -- jump not taken WHEN OTHERS => pc_int := std_logic_vector(unsigned(unsigned(pc_int) + to_unsigned(1,d_bus_width))); END CASE; END IF; end if; pc <= pc_int; END process; end behavioral; @ 1.2 log @control unit bus fixed ram_control block improved @ text @d16 5 a20 4 pc_p: process(clk,rst) VARIABLE pc_int : d_bus := zero_bus; BEGIN IF rst='1' THEN d22 1 a22 1 ELSIF clk'EVENT AND clk='1' THEN d31 2 a32 1 pc <= pc_int; @ 1.1 log @Initial revision @ text @d24 3 a26 2 WHEN jmp_1 | jmpc_1 | jmpz_1 => pc_int := addr_in; WHEN lda_addr_1 | ldb_addr_1 => null; @ 1.1.1.1 log @first upload @ text @@