head 1.4; access; symbols ver_tag:1.1.1.1 vendor_tag:1.1.1; locks; strict; comment @# @; 1.4 date 2008.08.10.17.16.08; author dimo; state Exp; branches; next 1.3; commitid 715d489f224e4567; 1.3 date 2008.07.03.16.26.30; author dimo; state Exp; branches; next 1.2; commitid 1524486cfda64567; 1.2 date 2008.06.27.17.41.49; author dimo; state Exp; branches; next 1.1; commitid 7a08486526444567; 1.1 date 2008.06.23.19.58.00; author dimo; state Exp; branches 1.1.1.1; next ; commitid 1b3f4860003f4567; 1.1.1.1 date 2008.06.23.19.58.00; author dimo; state Exp; branches; next ; commitid 1b3f4860003f4567; desc @@ 1.4 log @ . @ text @library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.cpu_types.all; entity control is port( clk, rst : in std_logic; flagc, flagz, carry, carry_new, zero, zero_new : IN std_logic; input : IN d_bus; output, output_nxt : OUT opcode ); end control; architecture behavioral of control is signal pr_state, nxt_state : opcode; begin output <= pr_state; output_nxt <= nxt_state; main_s_p: process(clk) begin if clk'event and clk='1' then IF rst='1' THEN pr_state <= nop; else pr_state <= nxt_state; end if; END if; end process; main_c_p: process(pr_state,input,carry,carry_new,zero,zero_new,flagz,flagc) begin case pr_state is WHEN nop | jnt | neg_s | and_s | exor_s | or_s | sra_s | ror_s | add_s | addc_s | jmp_2 | jmpc_2 | jmpz_2 | lda_const_2 | ldb_const_2 | lda_addr_2 | ldb_addr_2 | sta_2 => CASE input(input'HIGH DOWNTO 5) IS WHEN "000" => nxt_state <= nop; WHEN "001" => case input(3 DOWNTO 0) is WHEN "0100" => nxt_state <= neg_s; WHEN "0101" => nxt_state <= and_s; WHEN "0110" => nxt_state <= exor_s; WHEN "0111" => nxt_state <= or_s; WHEN "1000" => nxt_state <= sra_s; WHEN "1001" => nxt_state <= ror_s; WHEN OTHERS => nxt_state <= nop; END case; WHEN "010" => case input(3 DOWNTO 0) is WHEN "0000" => nxt_state <= add_s; WHEN "0001" => nxt_state <= addc_s; WHEN OTHERS => nxt_state <= nop; END case; WHEN "011" => case input(3 DOWNTO 0) is WHEN "0011" => nxt_state <= jmp_1; WHEN "0010" => IF (carry='1' and flagc='0') or (carry_new='1' and flagc='1') THEN nxt_state <= jmpc_1; ELSE nxt_state <= jnt; END IF; WHEN "0001" => IF (zero='1' and flagz='0') or (zero_new='1' and flagz='1') THEN nxt_state <= jmpz_1; ELSE nxt_state <= jnt; END IF; WHEN OTHERS => nxt_state <= nop; END case; WHEN "100" => CASE input(3 DOWNTO 0) IS WHEN "1101" => nxt_state <= lda_const_1; WHEN "1111" => nxt_state <= ldb_const_1; WHEN OTHERS => nxt_state <= nop; END case; WHEN "101" => case input(3 DOWNTO 0) is WHEN "1101" => nxt_state <= lda_addr_1; WHEN "1111" => nxt_state <= ldb_addr_1; WHEN "1100" => nxt_state <= sta_1; WHEN OTHERS => nxt_state <= nop; END CASE; WHEN OTHERS => nxt_state <= nop; END case; WHEN jmp_1 => nxt_state <= jmp_2; WHEN jmpc_1 => nxt_state <= jmpc_2; WHEN jmpz_1 => nxt_state <= jmpz_2; WHEN lda_const_1 => nxt_state <= lda_const_2; WHEN ldb_const_1 => nxt_state <= ldb_const_2; WHEN lda_addr_1 => nxt_state <= lda_addr_2; WHEN ldb_addr_1 => nxt_state <= ldb_addr_2; WHEN sta_1 => nxt_state <= sta_2; WHEN OTHERS => nxt_state <= nop; END case; END process; END behavioral; @ 1.3 log @testbench havior fixed @ text @d8 1 a8 1 carry, carry_new, zero, zero_new : IN std_logic; d20 1 a20 1 d33 1 a33 1 main_c_p: process(pr_state,input,carry,carry_new,zero,zero_new) d59 1 a59 1 WHEN "0010" => IF carry='1' or carry_new='1' THEN d64 1 a64 1 WHEN "0001" => IF zero='1' or zero_new='1' THEN @ 1.2 log @control unit bus fixed ram_control block improved @ text @d8 1 a8 1 carry, zero : IN std_logic; d33 1 a33 1 main_c_p: process(pr_state,input, carry, zero) d59 1 a59 1 WHEN "0010" => IF carry='1' THEN d64 1 a64 1 WHEN "0001" => IF zero='1' THEN @ 1.1 log @Initial revision @ text @d10 1 a10 1 output : OUT opcode ); d18 2 a19 2 output <= pr_state; -- output <= nxt_state; d37 1 a37 1 WHEN nop | neg_s | and_s | exor_s | or_s | sra_s | ror_s | add_s | addc_s | jmp_2 | jmpc_2 | jmpz_2 | lda_const_2 | ldb_const_2 | lda_addr_3 | ldb_addr_3 | sta_2 => d62 1 a62 1 nxt_state <= nop; d67 1 a67 1 nxt_state <= nop; a91 1 WHEN lda_addr_2 => nxt_state <= lda_addr_3; a92 1 WHEN ldb_addr_2 => nxt_state <= ldb_addr_3; @ 1.1.1.1 log @first upload @ text @@