head 1.11; access; symbols STEP2_2c:1.11 STEP1_2:1.11 STEP2_2b:1.5 Step2_2:1.5 STEP2_1b:1.3 STEP2_1:1.3 STEP1_1:1.2; locks; strict; comment @# @; 1.11 date 2006.11.01.14.24.26; author quickwayne; state Exp; branches; next 1.10; commitid 1e094548ae184567; 1.10 date 2006.11.01.13.21.00; author quickwayne; state Exp; branches; next 1.9; commitid 6b3045489f364567; 1.9 date 2006.11.01.13.17.03; author quickwayne; state dead; branches; next 1.8; commitid 687245489e4d4567; 1.8 date 2006.11.01.13.05.41; author quickwayne; state Exp; branches; next 1.7; commitid 624945489ba24567; 1.7 date 2006.11.01.12.37.12; author quickwayne; state Exp; branches; next 1.6; commitid 5079454894f64567; 1.6 date 2006.11.01.12.17.17; author quickwayne; state dead; branches; next 1.5; commitid 416a4548904b4567; 1.5 date 2006.07.29.00.25.00; author quickwayne; state Exp; branches; next 1.4; commitid 383d44caaacb4567; 1.4 date 2006.07.28.13.47.52; author quickwayne; state Exp; branches; next 1.3; commitid 2de544ca15864567; 1.3 date 2006.07.18.02.14.25; author quickwayne; state Exp; branches; next 1.2; commitid 689644bc43d34567; 1.2 date 2006.06.23.18.55.17; author quickwayne; state Exp; branches; next 1.1; commitid 3193449c39124567; 1.1 date 2006.06.23.17.18.55; author quickwayne; state Exp; branches; next ; commitid 374449c227d4567; desc @@ 1.11 log @*** empty log message *** @ text @# ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1 # Wed Nov 01 18:23:34 2006 # Target Board: Xilinx XUP Virtex-II Pro Development System Rev C # Family: virtex2p # Device: xc2vp30 # Package: ff896 # Speed Grade: -7 # Processor: Microblaze # System clock frequency: 100.000000 MHz # Debug interface: On-Chip HW Debug Module # On Chip Memory : 8 KB # Total Off Chip Memory : 256 MB # - DDR_SDRAM_32Mx64 Single Rank = 256 MB # ############################################################################## PARAMETER VERSION = 2.1.0 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = INPUT PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = OUTPUT PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = INOUT PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = OUTPUT PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = OUTPUT PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = OUTPUT PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = INPUT PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, VEC = [0:2], DIR = OUTPUT PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, VEC = [0:2], DIR = OUTPUT PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, VEC = [0:12], DIR = OUTPUT PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, VEC = [0:1], DIR = OUTPUT PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = OUTPUT PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = OUTPUT PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = OUTPUT PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, VEC = [0:7], DIR = OUTPUT PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, VEC = [0:7], DIR = INOUT PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, VEC = [0:63], DIR = INOUT PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = OUTPUT PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = OUTPUT PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK PORT sys_rst_pin = sys_rst_s, DIR = INPUT BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 4.00.a PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_NUMBER_OF_PC_BRK = 2 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DOPB = mb_opb BUS_INTERFACE IOPB = mb_opb PORT CLK = sys_clk_s PORT DBG_CAPTURE = DBG_CAPTURE_s PORT DBG_CLK = DBG_CLK_s PORT DBG_REG_EN = DBG_REG_EN_s PORT DBG_TDI = DBG_TDI_s PORT DBG_TDO = DBG_TDO_s PORT DBG_UPDATE = DBG_UPDATE_s END BEGIN opb_v20 PARAMETER INSTANCE = mb_opb PARAMETER HW_VER = 1.10.c PARAMETER C_EXT_RESET_HIGH = 0 PORT SYS_Rst = sys_rst_s PORT OPB_Clk = sys_clk_s END BEGIN opb_mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 2.00.a PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0x41400000 PARAMETER C_HIGHADDR = 0x4140ffff BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT DBG_CAPTURE_0 = DBG_CAPTURE_s PORT DBG_CLK_0 = DBG_CLK_s PORT DBG_REG_EN_0 = DBG_REG_EN_s PORT DBG_TDI_0 = DBG_TDI_s PORT DBG_TDO_0 = DBG_TDO_s PORT DBG_UPDATE_0 = DBG_UPDATE_s END BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT SYS_Rst = sys_rst_s PORT LMB_Clk = sys_clk_s END BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT SYS_Rst = sys_rst_s PORT LMB_Clk = sys_clk_s END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000ffff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000ffff BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_port END BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = ilmb_port BUS_INTERFACE PORTB = dlmb_port END BEGIN opb_uartlite PARAMETER INSTANCE = RS232_Uart_1 PARAMETER HW_VER = 1.00.b PARAMETER C_BAUDRATE = 9600 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_CLK_FREQ = 100000000 PARAMETER C_BASEADDR = 0x40600000 PARAMETER C_HIGHADDR = 0x4060ffff BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT RX = fpga_0_RS232_Uart_1_RX PORT TX = fpga_0_RS232_Uart_1_TX END BEGIN opb_sysace PARAMETER INSTANCE = SysACE_CompactFlash PARAMETER HW_VER = 1.00.c PARAMETER C_MEM_WIDTH = 16 PARAMETER C_BASEADDR = 0x41800000 PARAMETER C_HIGHADDR = 0x4180ffff BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ END BEGIN opb_ddr PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5 PARAMETER HW_VER = 2.00.b PARAMETER C_OPB_CLK_PERIOD_PS = 10000 PARAMETER C_NUM_BANKS_MEM = 1 PARAMETER C_NUM_CLK_PAIRS = 4 PARAMETER C_REG_DIMM = 0 PARAMETER C_DDR_TMRD = 20000 PARAMETER C_DDR_TWR = 20000 PARAMETER C_DDR_TRAS = 60000 PARAMETER C_DDR_TRC = 90000 PARAMETER C_DDR_TRFC = 100000 PARAMETER C_DDR_TRCD = 30000 PARAMETER C_DDR_TRRD = 20000 PARAMETER C_DDR_TRP = 30000 PARAMETER C_DDR_TREFC = 70300000 PARAMETER C_DDR_AWIDTH = 13 PARAMETER C_DDR_COL_AWIDTH = 10 PARAMETER C_DDR_BANK_AWIDTH = 2 PARAMETER C_DDR_DWIDTH = 64 PARAMETER C_MEM0_BASEADDR = 0x30000000 PARAMETER C_MEM0_HIGHADDR = 0x3fffffff BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr PORT DDR_BankAddr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0 PORT Device_Clk90_in = clk_90_s PORT Device_Clk90_in_n = clk_90_n_s PORT Device_Clk = sys_clk_s PORT Device_Clk_n = sys_clk_n_s PORT DDR_Clk90_in = ddr_clk_90_s PORT DDR_Clk90_in_n = ddr_clk_90_n_s END BEGIN util_vector_logic PARAMETER INSTANCE = sysclk_inv PARAMETER HW_VER = 1.00.a PARAMETER C_SIZE = 1 PARAMETER C_OPERATION = not PORT Op1 = sys_clk_s PORT Res = sys_clk_n_s END BEGIN util_vector_logic PARAMETER INSTANCE = clk90_inv PARAMETER HW_VER = 1.00.a PARAMETER C_SIZE = 1 PARAMETER C_OPERATION = not PORT Op1 = clk_90_s PORT Res = clk_90_n_s END BEGIN util_vector_logic PARAMETER INSTANCE = ddr_clk90_inv PARAMETER HW_VER = 1.00.a PARAMETER C_SIZE = 1 PARAMETER C_OPERATION = not PORT Op1 = ddr_clk_90_s PORT Res = ddr_clk_90_n_s END BEGIN dcm_module PARAMETER INSTANCE = dcm_0 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLK90_BUF = TRUE PARAMETER C_CLKIN_PERIOD = 10.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_EXT_RESET_HIGH = 1 PORT CLKIN = dcm_clk_s PORT CLK0 = sys_clk_s PORT CLK90 = clk_90_s PORT CLKFB = sys_clk_s PORT RST = net_gnd PORT LOCKED = dcm_0_lock END BEGIN dcm_module PARAMETER INSTANCE = dcm_1 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLK90_BUF = TRUE PARAMETER C_CLKIN_PERIOD = 10.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_PHASE_SHIFT = 60 PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED PARAMETER C_EXT_RESET_HIGH = 0 PORT CLKIN = ddr_feedback_s PORT CLK90 = ddr_clk_90_s PORT CLK0 = dcm_1_FB PORT CLKFB = dcm_1_FB PORT RST = dcm_0_lock PORT LOCKED = dcm_1_lock END @ 1.10 log @*** empty log message *** @ text @a0 1 # a1 1 # a2 1 # a3 1 # a8 1 # d14 1 a14 2 # - DDR_SDRAM_32Mx64 Single Rank = 256 MB # d24 2 a25 2 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = OUTPUT, VEC = [6:0] PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = INOUT, VEC = [15:0] d30 4 a33 4 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, DIR = OUTPUT, VEC = [0:2] PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, DIR = OUTPUT, VEC = [0:2] PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, DIR = OUTPUT, VEC = [0:12] PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, DIR = OUTPUT, VEC = [0:1] d37 3 a39 3 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, DIR = OUTPUT, VEC = [0:7] PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, DIR = INOUT, VEC = [0:7] PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, DIR = INOUT, VEC = [0:63] d114 1 a114 1 PARAMETER C_HIGHADDR = 0x00001fff d123 1 a123 1 PARAMETER C_HIGHADDR = 0x00001fff @ 1.9 log @*** empty log message *** @ text @d1 1 d3 1 d5 3 a7 1 # Wed Nov 01 17:33:15 2006 d13 1 d17 1 a17 1 # On Chip Memory : 64 KB d19 2 a20 1 # - DDR_SDRAM_32Mx64 Single Rank = 256 MB a35 1 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = INOUT, VEC = [0:3] d120 1 a120 1 PARAMETER C_HIGHADDR = 0x0000ffff d129 1 a129 1 PARAMETER C_HIGHADDR = 0x0000ffff a173 14 BEGIN opb_gpio PARAMETER INSTANCE = LEDs_4Bit PARAMETER HW_VER = 3.01.b PARAMETER C_GPIO_WIDTH = 4 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 0 PARAMETER C_ALL_INPUTS = 0 PARAMETER C_BASEADDR = 0x40000000 PARAMETER C_HIGHADDR = 0x4000ffff BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO END d194 2 a195 2 PARAMETER C_MEM0_BASEADDR = 0x70000000 PARAMETER C_MEM0_HIGHADDR = 0x7fffffff @ 1.8 log @*** empty log message *** @ text @@ 1.7 log @*** empty log message *** @ text @a0 1 # a1 1 # a2 1 # a3 1 # a8 1 # d14 1 a14 2 # - DDR_SDRAM_32Mx64 Single Rank = 256 MB # d203 2 a204 2 PARAMETER C_MEM0_BASEADDR = 0x30000000 PARAMETER C_MEM0_HIGHADDR = 0x3fffffff @ 1.6 log @*** empty log message *** @ text @d1 1 d3 1 d5 3 a7 1 # Fri Jun 23 16:02:16 2006 d13 1 d18 3 d27 26 a52 14 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = O PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = IO PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, VEC = [0:3], DIR = IO PORT fpga_0_DIPSWs_4Bit_GPIO_IO_pin = fpga_0_DIPSWs_4Bit_GPIO_IO, VEC = [0:3], DIR = IO PORT fpga_0_PushButtons_5Bit_GPIO_IO_pin = fpga_0_PushButtons_5Bit_GPIO_IO, VEC = [0:4], DIR = IO PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = DCMCLK PORT sys_rst_pin = sys_rst_s, DIR = I d60 2 a61 3 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0 PARAMETER C_FSL_LINKS = 1 a65 2 BUS_INTERFACE MFSL0 = microblaze_0_to_fsl_dct_0 BUS_INTERFACE SFSL0 = fsl_dct_0_to_microblaze_0 d120 2 a121 2 PARAMETER C_BASEADDR = 0x00010000 PARAMETER C_HIGHADDR = 0x00017FFF d130 1 a130 1 PARAMETER C_HIGHADDR = 0x00007FFF d136 1 a136 1 PARAMETER INSTANCE = ilmb_bram d139 1 d182 2 a183 2 PARAMETER C_BASEADDR = 0x40020000 PARAMETER C_HIGHADDR = 0x4002ffff d189 22 a210 9 BEGIN opb_gpio PARAMETER INSTANCE = DIPSWs_4Bit PARAMETER HW_VER = 3.01.b PARAMETER C_GPIO_WIDTH = 4 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 1 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_BASEADDR = 0x40040000 PARAMETER C_HIGHADDR = 0x4004ffff d213 36 a248 1 PORT GPIO_IO = fpga_0_DIPSWs_4Bit_GPIO_IO d251 7 a257 12 BEGIN opb_gpio PARAMETER INSTANCE = PushButtons_5Bit PARAMETER HW_VER = 3.01.b PARAMETER C_GPIO_WIDTH = 5 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 1 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_BASEADDR = 0x40000000 PARAMETER C_HIGHADDR = 0x4000ffff BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT GPIO_IO = fpga_0_PushButtons_5Bit_GPIO_IO d264 1 d270 1 d276 2 a277 2 BEGIN bram_block PARAMETER INSTANCE = data_bram_0 d279 6 a284 23 PARAMETER C_MEMSIZE = 16384 BUS_INTERFACE PORTA = data_bram_0_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = data_bram_if_cntlr_0 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x70000000 PARAMETER C_HIGHADDR = 0x7000ffff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = data_bram_0_port END BEGIN bram_block PARAMETER INSTANCE = dlmb_bram PARAMETER HW_VER = 1.00.a PARAMETER C_MEMSIZE = 16384 BUS_INTERFACE PORTA = dlmb_port END BEGIN fsl_v20 PARAMETER INSTANCE = microblaze_0_to_fsl_dct_0 PARAMETER HW_VER = 2.00.a d286 6 a291 18 PORT FSL_Clk = sys_clk_s PORT SYS_Rst = sys_rst_s END BEGIN fsl_dct PARAMETER INSTANCE = fsl_dct_0 PARAMETER HW_VER = 1.00.a BUS_INTERFACE SFSL = microblaze_0_to_fsl_dct_0 BUS_INTERFACE MFSL = fsl_dct_0_to_microblaze_0 PORT FSL_Clk = sys_clk_s END BEGIN fsl_v20 PARAMETER INSTANCE = fsl_dct_0_to_microblaze_0 PARAMETER HW_VER = 2.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT FSL_Clk = sys_clk_s PORT SYS_Rst = sys_rst_s @ 1.5 log @1. change active project from encoder to bmp2jpg_mb 2. reduce heap size to 0x400, stack size to 0x1000 for bmp2jpg_mb project 3. reduce instruction and data memory size to 32KB respectively 4. elaboate code for memory and platform independance @ text @@ 1.4 log @add bmp2jpg_mb project instead of encoder project add link script for bmp2jpg_mb @ text @d104 1 a104 1 PARAMETER C_HIGHADDR = 0x0001ffff d113 1 a113 1 PARAMETER C_HIGHADDR = 0x0000ffff @ 1.3 log @Modify hardware architecture 1. memory layout: 64KB instruction, 64KB data + 64KB image buffer @ text @d39 4 a42 3 PARAMETER C_NUMBER_OF_PC_BRK = 4 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 d47 2 d236 24 @ 1.2 log @Updated to EDK8.1 @ text @d39 1 a39 1 PARAMETER C_NUMBER_OF_PC_BRK = 2 d100 2 a101 2 PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000ffff d116 1 a116 1 PARAMETER INSTANCE = lmb_bram a118 1 BUS_INTERFACE PORTB = dlmb_port d227 1 a227 1 PARAMETER INSTANCE = data_bram_1 d230 1 a230 10 BUS_INTERFACE PORTA = data_bram_1_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = data_bram_if_cntlr_1 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x70010000 PARAMETER C_HIGHADDR = 0x7001ffff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = data_bram_1_port @ 1.1 log @Microblaze hardware implementation without accelerators. Open with EDK7.1 or higher. @ text @d19 14 a32 14 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = INPUT PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = OUTPUT PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = INOUT PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = OUTPUT PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = OUTPUT PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = OUTPUT PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = INPUT PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, VEC = [0:3], DIR = INOUT PORT fpga_0_DIPSWs_4Bit_GPIO_IO_pin = fpga_0_DIPSWs_4Bit_GPIO_IO, VEC = [0:3], DIR = INOUT PORT fpga_0_PushButtons_5Bit_GPIO_IO_pin = fpga_0_PushButtons_5Bit_GPIO_IO, VEC = [0:4], DIR = INOUT PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK PORT sys_rst_pin = sys_rst_s, DIR = INPUT @