head 1.1; branch 1.1.1; access ; symbols initial:1.1.1.1 diogenes:1.1.1; locks ; strict; comment @# @; 1.1 date 2008.01.28.20.06.10; author fellnhofer; state Exp; branches 1.1.1.1; next ; commitid 122547a751ef4567; 1.1.1.1 date 2008.01.28.20.06.10; author fellnhofer; state Exp; branches ; next ; commitid 122547a751ef4567; desc @@ 1.1 log @Initial revision @ text @Release 9.2i - par J.36 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. Mon Jan 28 21:06:10 2008 All signals are completely routed. @ 1.1.1.1 log @ @ text @@