head 1.1; branch 1.1.1; access ; symbols start:1.1.1.1 vendor:1.1.1; locks ; strict; comment @# @; 1.1 date 2004.04.10.16.05.39; author tarookumichi; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2004.04.10.16.05.39; author tarookumichi; state Exp; branches ; next ; desc @@ 1.1 log @Initial revision @ text @onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -divider -height 30 DCACHE add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/clk add wave -noupdate -divider { } add wave -noupdate -format Literal -label .state -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/r.state add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/hold add wave -noupdate -format Logic -label .hit -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.hit add wave -noupdate -format Logic -label .valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.valid add wave -noupdate -format Logic -label .dirty -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.dirty add wave -noupdate -format Logic -label .req -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.req add wave -noupdate -divider in add wave -noupdate -format Literal -label .addr_re -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/i.addr_re add wave -noupdate -format Literal -label .data_re -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/i.data_re add wave -noupdate -format Logic -label .read -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/i.param_r.read add wave -noupdate -format Literal -label .param_r -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/i.param_r add wave -noupdate -divider out add wave -noupdate -format Literal -label .wr_data -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/o.wr_data add wave -noupdate -divider {Cachemem in} add wave -noupdate -format Literal -label .addr -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/dcmi.addr add wave -noupdate -format Literal -label .tag_line -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/dcmi.tag_line add wave -noupdate -format Literal -label .tag_write -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/dcmi.tag_write add wave -noupdate -format Literal -label .dat_line -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/dcmi.dat_line add wave -noupdate -format Literal -label .dat_write -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/dcmi.dat_write add wave -noupdate -divider {Cachemem out} add wave -noupdate -format Literal -label .tag_line -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/dcmo.tag_line add wave -noupdate -format Literal -label .dat_line -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/dcmo.dat_line add wave -noupdate -divider Writeback add wave -noupdate -format Literal -label r.dirty -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/r.dirty add wave -noupdate -format Literal -label t.linepos -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.linepos add wave -noupdate -format Literal -label t.linepos_lastbit -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.linepos_lastbit add wave -noupdate -format Literal -label si.data -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/si.data add wave -noupdate -format Literal -label so.res -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/so.res add wave -noupdate -format Logic -label r.wbready -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/r.wbready add wave -noupdate -format Logic -label r.wbnext -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/r.wbnext add wave -noupdate -format Literal -label wbi.fifo_entry -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/wbi.fifo_entry add wave -noupdate -format Logic -label wbi.fifo_write -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/wbi.fifo_write add wave -noupdate -format Logic -label wbo.fifo_stored_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/wbo.fifo_stored_v add wave -noupdate -divider SETS add wave -noupdate -format Literal -label t.set -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.set add wave -noupdate -format Literal -label t.setrep -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.setrep add wave -noupdate -format Literal -label r.setrep -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/r.setrep add wave -noupdate -format Literal -label t.sethit -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.sethit add wave -noupdate -format Literal -label t.setvalid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.setvalid add wave -noupdate -format Literal -label t.sr_setfree -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.sr_setfree add wave -noupdate -format Literal -label t.sr_setlock -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.sr_setlock add wave -noupdate -format Logic -label t.sr_useset -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.sr_useset add wave -noupdate -format Logic -label sro.sr_locked -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/sr_locked add wave -noupdate -format Logic -label sro.sr_free -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/sr_free add wave -noupdate -format Literal -label sro.sr_setrep_free -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/sr_setrep_free add wave -noupdate -format Literal -label sro.sr_setrep_repl -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/sr_setrep_repl add wave -noupdate -divider Multiplex add wave -noupdate -format Literal -label .cmaddr_src -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.cmaddr_src add wave -noupdate -format Literal -label .datain_src -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.datain_src add wave -noupdate -format Literal -label .tvalid_src -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.tvalid_src add wave -noupdate -format Literal -label .tdirty_src -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg.dbg.tdirty_src add wave -noupdate -divider { } add wave -noupdate -format Literal -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/i add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/o add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/rst add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/ctrl add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/dcmo add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/dcmi add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/wbi add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/wbo add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/r add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/c add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/rdbg add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/si add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/so add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/sr_setfree add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/sr_setlock add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/sr_useset add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/sr_locked add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/sr_free add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/sr_setrep_free add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/sr_setrep_repl add wave -noupdate -divider -height 50 COUNTER add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cdbg add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cnt0/rst add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cnt0/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cnt0/si add wave -noupdate -format Literal -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cnt0/so add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cnt0/r add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cnt0/c add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cnt0/rdbg add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/dc0/cnt0/cdbg add wave -noupdate -divider -height 50 {WRITE BUFFER} add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/clk add wave -noupdate -divider in add wave -noupdate -format Logic -label .fifo_write -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/i.fifo_write add wave -noupdate -format Literal -label .fifo_entry -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/i.fifo_entry add wave -noupdate -divider AMBA add wave -noupdate -format Logic -label o.req -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/mcwbi.req add wave -noupdate -format Logic -label o.read -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/mcwbi.read add wave -noupdate -format Literal -label o.address -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/mcwbi.address add wave -noupdate -format Logic -label i.ready -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/mcwbo.ready add wave -noupdate -format Logic -label i.grant -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/mcwbo.grant add wave -noupdate -format Literal -label i.data -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/mcwbo.data add wave -noupdate -divider out add wave -noupdate -format Logic -label .fifo_stored_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/o.fifo_stored_v add wave -noupdate -format Logic -label .empty_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/o.empty_v add wave -noupdate -divider { } add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/rst add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/i add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/o add wave -noupdate -format Literal -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/mcwbo add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/mcwbi add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/r add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/c add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/rdbg add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/cdbg add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/wbfifoi add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/wbfifoo add wave -noupdate -divider -height 50 {WB FIFO} add wave -noupdate -format Logic /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/clk add wave -noupdate -divider in add wave -noupdate -format Literal -label .fifo_entry -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/i.fifo_entry add wave -noupdate -format Logic -label .fifo_read -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/i.fifo_read add wave -noupdate -format Logic -label .fifo_write -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/i.fifo_write add wave -noupdate -divider out add wave -noupdate -format Literal -label .fifo_entry -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/o.fifo_entry add wave -noupdate -format Logic -label .fifo_stored_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/o.fifo_stored_v add wave -noupdate -format Logic -label .fifo_empty_r -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/o.fifo_empty_r add wave -noupdate -divider { } add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/rst add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/i add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/o add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/r add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/c add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/rdbg add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/wb0/gfifo0/fifo0/cdbg add wave -noupdate -divider { } TreeUpdate [SetDefaultTree] WaveRestoreCursors {10886 ns} WaveRestoreZoom {10058 ns} {11490 ns} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left configure wave -signalnamewidth 0 configure wave -snapdistance 10 configure wave -datasetprefix 0 @ 1.1.1.1 log @Core library @ text @@