head 1.1; branch 1.1.1; access ; symbols start:1.1.1.1 conte:1.1.1; locks ; strict; comment @# @; 1.1 date 2004.09.02.21.36.52; author conte; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2004.09.02.21.36.52; author conte; state Exp; branches ; next ; desc @@ 1.1 log @Initial revision @ text @////////////////////////////////////////////////////////////////////// //// //// //// Generic Single-Port Synchronous RAM //// //// //// //// This file is part of memory library available from //// //// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// //// //// //// Description //// //// This block is a wrapper with common single-port //// //// synchronous memory interface for different //// //// types of ASIC and FPGA RAMs. Beside universal memory //// //// interface it also provides behavioral model of generic //// //// single-port synchronous RAM. //// //// It should be used in all OPENCORES designs that want to be //// //// portable accross different target technologies and //// //// independent of target memory. //// //// //// //// Supported ASIC RAMs are: //// //// - Artisan Single-Port Sync RAM //// //// - Avant! Two-Port Sync RAM (*) //// //// - Virage Single-Port Sync RAM //// //// - Virtual Silicon Single-Port Sync RAM //// //// //// //// Supported FPGA RAMs are: //// //// - Xilinx Virtex RAMB4_S16 //// //// - Altera LPM //// //// //// //// To Do: //// //// - xilinx rams need external tri-state logic //// //// - fix avant! two-port ram //// //// - add additional RAMs //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: or1200_spram_1024x8.v,v $ // Revision 1.7 2004/04/05 08:29:57 lampret // Merged branch_qmem into main tree. // // Revision 1.3.4.1 2003/12/09 11:46:48 simons // Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. // // Revision 1.3 2003/04/07 01:19:07 lampret // Added Altera LPM RAMs. Changed generic RAM output when OE inactive. // // Revision 1.2 2002/10/17 20:04:40 lampret // Added BIST scan. Special VS RAMs need to be used to implement BIST. // // Revision 1.1 2002/01/03 08:16:15 lampret // New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. // // Revision 1.8 2001/11/02 18:57:14 lampret // Modified virtual silicon instantiations. // // Revision 1.7 2001/10/21 17:57:16 lampret // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. // // Revision 1.6 2001/10/14 13:12:09 lampret // MP3 version. // // Revision 1.1.1.1 2001/10/06 10:18:36 igorm // no message // // Revision 1.1 2001/08/09 13:39:33 lampret // Major clean-up. // // Revision 1.2 2001/07/30 05:38:02 lampret // Adding empty directories required by HDL coding guidelines // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "or1200_defines.v" module or1200_spram_1024x8( `ifdef OR1200_BIST // RAM BIST mbist_si_i, mbist_so_o, mbist_ctrl_i, `endif // Generic synchronous single-port RAM interface clk, rst, ce, we, oe, addr, di, do ); // // Default address and data buses width // parameter aw = 10; parameter dw = 8; `ifdef OR1200_BIST // // RAM BIST // input mbist_si_i; input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; output mbist_so_o; `endif // // Generic synchronous single-port RAM interface // input clk; // Clock input rst; // Reset input ce; // Chip enable input input we; // Write enable input input oe; // Output enable input input [aw-1:0] addr; // address bus inputs input [dw-1:0] di; // input data bus output [dw-1:0] do; // output data bus // // Internal wires and registers // `ifdef OR1200_ARTISAN_SSP `else `ifdef OR1200_VIRTUALSILICON_SSP `else `ifdef OR1200_BIST assign mbist_so_o = mbist_si_i; `endif `endif `endif `ifdef OR1200_ARTISAN_SSP // // Instantiation of ASIC memory: // // Artisan Synchronous Single-Port RAM (ra1sh) // `ifdef UNUSED art_hssp_1024x8 #(dw, 1<