head 1.1; branch 1.1.1; access ; symbols start':1.1.1.1 cd16:1.1.1; locks ; strict; comment @# @; 1.1 date 2003.08.15.17.25.43; author beckert; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2003.08.15.17.25.43; author beckert; state Exp; branches ; next ; desc @@ 1.1 log @Initial revision @ text @-- \ Single port data memory for CD16. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.CD16pkg.all; entity DATAMEM is -- \ Data memory, synchronous read/write port( clk: in std_logic; d_in: in cell; -- ' undef in: d_in \ data from CPU d_out: out cell; -- \ data to CPU da: in cell; -- \ address from CPU wr: in std_logic; -- ' undef in: d_wr \ write enable rd: in std_logic); -- ' undef in: d_rd \ read enable end DATAMEM; architecture behavioral of DATAMEM is -- CREATE DMEM -1 &da 1+ CELLS ALLOT type Rtype is array((2**dawidth)-1 downto 0) of cell; signal RAM: Rtype; -- : 'DMEM ( n -- addr ) &da CELLS DMEM + ; signal da_r: cell; -- r: da_r begin wrt: process(clk) begin -- : clkmem ( -- ) if (clk'event and clk='1') then if wr='1' then -- d_wr IF dy da 'DMEM ! THEN RAM(CONV_INTEGER(da(dawidth-1 downto 0))) <= d_in; end if; if rd='1' then -- d_rd IF da da_r !! THEN da_r <= da; end if; end if; -- clkmem ; end process wrt; -- : d_out ( -- n ) \ data to CPU d_out <= RAM(CONV_INTEGER(da_r(dawidth-1 downto 0))); -- da_r @@@@ 'DMEM @@ &cell ; end behavioral; @ 1.1.1.1 log @Imported sources @ text @@