head 1.1; branch 1.1.1; access; symbols arelease:1.1.1.2 avendor:1.1.1; locks; strict; comment @# @; 1.1 date 2002.03.07.19.05.51; author victor; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2002.03.07.19.05.51; author victor; state Exp; branches; next 1.1.1.2; 1.1.1.2 date 2002.05.16.19.26.33; author victor; state Exp; branches; next ; desc @@ 1.1 log @Initial revision @ text @-- u law codec PACKAGE constants IS constant G711_DATA_HIGH: INTEGER := 13; constant G711_OUT_HIGH: INTEGER := 7; END constants; library ieee; use ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; LIBRARY lpm; USE lpm.lpm_components.all; LIBRARY work; USE work.constants.all; entity G711 is port(PCM_in: in std_logic_vector(G711_DATA_HIGH downto 0);-- linear input G711_in: in std_logic_vector(G711_OUT_HIGH downto 0);-- G711 input PCM_out: out std_logic_vector(G711_DATA_HIGH downto 0);-- linear out G711_out:out std_logic_vector(G711_OUT_HIGH downto 0)--G711 output ); end G711; architecture BEHAVIOR of G711 is signal seg: STD_LOGIC_VECTOR (2 downto 0); signal G711_ins: STD_LOGIC_VECTOR (G711_OUT_HIGH downto 0); signal bias,bias1,sub_wire3:STD_LOGIC_VECTOR(12 downto 0); signal sub_wire0:STD_LOGIC_VECTOR(11 downto 0); SIGNAL sub_wire2 : STD_LOGIC ; COMPONENT shift PORT ( distance : IN STD_LOGIC_VECTOR (2 DOWNTO 0); data : IN STD_LOGIC_VECTOR (11 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_clshift GENERIC ( LPM_SHIFTTYPE : STRING; LPM_WIDTH : NATURAL; LPM_WIDTHDIST : NATURAL ); PORT ( distance : IN STD_LOGIC_VECTOR (2 DOWNTO 0); direction : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (12 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (12 DOWNTO 0) ); END COMPONENT; begin -- encoder -- segment calculation seg(0)<=bias(12) or (not(bias(11)) AND bias(10)) or (not(bias(9)) and not(bias(11)) and bias(8)) or (not(bias(7)) and not(bias(9)) and bias(6) and not(bias(11))); seg(1)<=bias(12) or bias(11) or (not(bias(10)) and not(bias(9)) and (bias(8) or bias(7))); seg(2)<=bias(12) or bias(11) or bias(10) or bias(9); -- to sipmlify encoding adding 33 bias<=PCM_in(12 downto 0)+33; -- shifting lpm_1 : shift PORT MAP ( distance => seg, data => bias(12 downto 1), result => sub_wire0 ); -- make G711 code (inverted) G711_out(3 downto 0)<=not(sub_wire0(3 downto 0)); G711_out(6 downto 4)<=not(seg); G711_out(7)<=not(PCM_in(13)); --decoder sub_wire2 <= '0'; lpm_2 : lpm_clshift GENERIC MAP ( LPM_SHIFTTYPE => "ROTATE", LPM_WIDTH => 13, LPM_WIDTHDIST => 3 ) PORT MAP ( distance => G711_ins(6 downto 4), direction => sub_wire2, data => sub_wire3, result => bias1 ); G711_ins<=not(G711_in); --prepare for shifting sub_wire3(4 downto 1)<=G711_ins(3 downto 0); sub_wire3(5)<='1';-- leadig '1' sub_wire3(12 downto 6)<="00000000"; sub_wire3(0)<='1';-- 1/2 quant step -- make 14 bit PCM linear code PCM_out(12 downto 0)<=bias1-33; PCM_out(13)<=G711_ins(7); end BEHAVIOR; @ 1.1.1.1 log @no message @ text @@ 1.1.1.2 log @no message @ text @d1 1 a1 35 ---- ---- ---- This file is part of the G711 u-law project ---- ---- http://www.opencores.org/cores/G711/ ---- ---- Description: ITU-T G.711 u-law codec, main module ---- Implementation of G711 u-law IP core according to ---- ---- G711 u-law IP core specification document. ---- ---- Author(s): Tokarev Victor ---- e-mail: victor@@opencores.org ---- ---- ---- ---------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2002 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer. ---- ---- ---- ---- This source file is free software; you can redistribute it ---- ---- and/or modify it under the terms of the GNU Lesser General ---- ---- Public License as published by the Free Software Foundation; ---- ---- either version 2.1 of the License, or (at your option) any ---- ---- later version. ---- ---- ---- ---- This source is distributed in the hope that it will be ---- ---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ---- PURPOSE. See the GNU Lesser General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU Lesser General ---- ---- Public License along with this source; if not, download it ---- ---- from http://www.opencores.org/lgpl.shtml ---- ---- ---- ---------------------------------------------------------------------- d30 2 a31 1 signal sub_wire0:STD_LOGIC_VECTOR(3 downto 0); d38 1 a38 1 result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) d43 6 a48 1 COMPONENT shift1 d51 1 d80 7 a86 1 lpm_2 : shift1 d89 1 @