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1.2
date 2005.09.12.08.10.43; author zuofu; state dead;
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date 2005.09.11.10.30.42; author zuofu; state Exp;
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date 2005.09.11.10.30.42; author zuofu; state Exp;
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@cleaned up repository - removed all intermediate ISE files
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Xilinx Implementation Summary
Design Overview for gpuchip
Property | Value |
Project Name: | c:\documents and settings\zuofu cheng\desktop\ece 395\ise\gpu |
Target Device: | xc2s100 |
Report Generated: | Sunday 09/11/05 at 03:57 |
Printable Summary (View as HTML) | gpuchip_summary.html |
Device Utilization Summary
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops: | 222 | 2,400 | 9% | |
Number of 4 input LUTs: | 388 | 2,400 | 16% | |
Logic Distribution: | | | | |
Number of occupied Slices: | 283 | 1,200 | 23% | |
Number of Slices containing only related logic: | 283 | 283 | 100% | |
Number of Slices containing unrelated logic: | 0 | 283 | 0% | |
Total Number 4 input LUTs: | 438 | 2,400 | 18% | |
Number used as logic: | 388 | | | |
Number used as a route-thru: | 50 | | | |
Number of bonded IOBs: | 48 | 92 | 52% | |
Number of GCLKs: | 2 | 4 | 50% | |
Number of GCLKIOBs: | 2 | 4 | 50% | |
Number of DLLs: | 2 | 4 | 50% | |
Performance Summary
Property | Value |
Number of Unrouted Signals: | All signals are completely routed. |
Number of Failing Constraints: | 0 |
Failing Constraints
Constraint(s) | Requested | Actual | Logic Levels |
No Constraints Found | | | |
Detailed Reports
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1.1
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@Initial revision
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1.1.1.1
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@First Checkin!
Using the XESS dual ported RAM controller and the original XSOC (retromicro) VGA driver. Also included a whole bunch of misc stuff....
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