head 1.5; access; symbols r0_0_1:1.1.1.1 uiuc:1.1.1; locks; strict; comment @# @; 1.5 date 2005.10.10.22.52.17; author zuofu; state Exp; branches; next 1.4; commitid 572434af0884567; 1.4 date 2005.09.30.16.10.47; author zuofu; state Exp; branches; next 1.3; commitid f9b433d636a4567; 1.3 date 2005.09.23.01.33.29; author esands; state Exp; branches; next 1.2; commitid 284843335b644567; 1.2 date 2005.09.16.15.46.15; author zuofu; state Exp; branches; next 1.1; commitid 3fb7432ae8c24567; 1.1 date 2005.09.11.10.29.49; author zuofu; state Exp; branches 1.1.1.1; next ; commitid 469e4324071a4567; 1.1.1.1 date 2005.09.11.10.29.49; author zuofu; state Exp; branches; next ; commitid 469e4324071a4567; desc @@ 1.5 log @GPU HDL design mostly done, intro is now completely working with XSA-50/100 + PIC microcontroller. Working on schematic and ARM processor support. @ text @inst sysReset init=S; # initialize internal reset # Flash RAM chip-enable # vga port connection # SDRAM pin connections # address bus # data bus # #NET "pin_cwrite" LOC = "p59" ; #NET "pin_cread" LOC = "p39" ; #NET "pin_cAddr<0>" LOC = "p75" ; #NET "pin_cAddr<10>" LOC = "p38" ; #NET "pin_cAddr<11>" LOC = "p44" ; #NET "pin_cAddr<12>" LOC = "p46" ; #NET "pin_cAddr<13>" LOC = "p49" ; #NET "pin_cAddr<14>" LOC = "p57" ; #NET "pin_cAddr<1>" LOC = "p74" ; #NET "pin_cAddr<2>" LOC = "p30" ; #NET "pin_cAddr<3>" LOC = "p31" ; #NET "pin_cAddr<4>" LOC = "p78" ; #NET "pin_cAddr<5>" LOC = "p42" ; #NET "pin_cAddr<6>" LOC = "p40" ; #NET "pin_cAddr<7>" LOC = "p29" ; #NET "pin_cAddr<8>" LOC = "p28" ; #NET "pin_cAddr<9>" LOC = "p27" ; #NET "pin_cread" LOC = "p39" ; #NET "pin_cwrite" LOC = "p59" ; #NET "pin_cAddr<0>" LOC = "p75" ; #NET "pin_cAddr<10>" LOC = "p38" ; #NET "pin_cAddr<11>" LOC = "p44" ; #NET "pin_cAddr<12>" LOC = "p46" ; #NET "pin_cAddr<13>" LOC = "p49" ; #NET "pin_cAddr<14>" LOC = "p57" ; #NET "pin_cAddr<1>" LOC = "p74" ; #NET "pin_cAddr<2>" LOC = "p30" ; #NET "pin_cAddr<3>" LOC = "p31" ; #NET "pin_cAddr<4>" LOC = "p78" ; #NET "pin_cAddr<5>" LOC = "p42" ; #NET "pin_cAddr<6>" LOC = "p40" ; #NET "pin_cAddr<7>" LOC = "p29" ; #NET "pin_cAddr<8>" LOC = "p28" ; #NET "pin_cAddr<9>" LOC = "p27" ; #NET "pin_cData<0>" LOC = "p80" ; #NET "pin_cData<10>" LOC = "p85" ; #NET "pin_cData<11>" LOC = "p86" ; #NET "pin_cData<12>" LOC = "p87" ; #NET "pin_cData<13>" LOC = "p94" ; #NET "pin_cData<14>" LOC = "p66" ; #NET "pin_cData<15>" LOC = "p64" ; #NET "pin_cData<1>" LOC = "p77" ; #NET "pin_cData<2>" LOC = "p83" ; #NET "pin_cData<3>" LOC = "p79" ; #NET "pin_cData<4>" LOC = "p76" ; #NET "pin_cData<5>" LOC = "p56" ; #NET "pin_cData<6>" LOC = "p54" ; #NET "pin_cData<7>" LOC = "p62" ; #NET "pin_cData<8>" LOC = "p67" ; #NET "pin_cData<9>" LOC = "p84" ; #NET "pin_cData<0>" LOC = "p80" ; #NET "pin_cData<1>" LOC = "p77" ; #NET "pin_cData<2>" LOC = "p83" ; #NET "pin_cData<3>" LOC = "p79" ; #NET "pin_cData<4>" LOC = "p76" ; #NET "pin_cData<5>" LOC = "p56" ; #NET "pin_cData<6>" LOC = "p54" ; #NET "pin_cData<7>" LOC = "p62" ; #NET "pin_SRCce" LOC = "p60" ; #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "pin_ba<0>" LOC = "p134" ; NET "pin_ba<1>" LOC = "p137" ; NET "pin_blue<0>" LOC = "p21" ; NET "pin_blue<1>" LOC = "p22" ; NET "pin_cas_n" LOC = "p126" ; NET "pin_ce_n" LOC = "p41" ; NET "pin_cke" LOC = "p131" ; NET "pin_clkin" LOC = "p88" ; NET "pin_cs_n" LOC = "p132" ; NET "pin_done" LOC = "p30" ; NET "pin_dqmh" LOC = "p124" ; NET "pin_dqml" LOC = "p122" ; NET "pin_green<0>" LOC = "p19" ; NET "pin_green<1>" LOC = "p20" ; NET "pin_hsync_n" LOC = "p23" ; NET "pin_load" LOC = "p59" ; NET "pin_port_addr<0>" LOC = "p74" ; NET "pin_port_addr<1>" LOC = "p75" ; NET "pin_port_addr<2>" LOC = "p60" ; NET "pin_port_addr<3>" LOC = "p62" ; NET "pin_port_in<0>" LOC = "p80" ; NET "pin_port_in<1>" LOC = "p79" ; NET "pin_port_in<2>" LOC = "p76" ; NET "pin_port_in<3>" LOC = "p66" ; NET "pin_port_in<4>" LOC = "p64" ; NET "pin_port_in<5>" LOC = "p63" ; NET "pin_port_in<6>" LOC = "p56" ; NET "pin_port_in<7>" LOC = "p54" ; NET "pin_pushbtn" LOC = "p93" ; NET "pin_ras_n" LOC = "p130" ; NET "pin_red<0>" LOC = "p12" ; NET "pin_red<1>" LOC = "p13" ; NET "pin_sAddr<0>" LOC = "p141" ; NET "pin_sAddr<10>" LOC = "p139" ; NET "pin_sAddr<11>" LOC = "p136" ; NET "pin_sAddr<1>" LOC = "p4" ; NET "pin_sAddr<2>" LOC = "p6" ; NET "pin_sAddr<3>" LOC = "p10" ; NET "pin_sAddr<4>" LOC = "p11" ; NET "pin_sAddr<5>" LOC = "p7" ; NET "pin_sAddr<6>" LOC = "p5" ; NET "pin_sAddr<7>" LOC = "p3" ; NET "pin_sAddr<8>" LOC = "p140" ; NET "pin_sAddr<9>" LOC = "p138" ; NET "pin_sclk" LOC = "p129" ; NET "pin_sclkfb" LOC = "p91" ; NET "pin_sData<0>" LOC = "p95" ; NET "pin_sData<10>" LOC = "p116" ; NET "pin_sData<11>" LOC = "p114" ; NET "pin_sData<12>" LOC = "p112" ; NET "pin_sData<13>" LOC = "p102" ; NET "pin_sData<14>" LOC = "p100" ; NET "pin_sData<15>" LOC = "p96" ; NET "pin_sData<1>" LOC = "p99" ; NET "pin_sData<2>" LOC = "p101" ; NET "pin_sData<3>" LOC = "p103" ; NET "pin_sData<4>" LOC = "p113" ; NET "pin_sData<5>" LOC = "p115" ; NET "pin_sData<6>" LOC = "p117" ; NET "pin_sData<7>" LOC = "p120" ; NET "pin_sData<8>" LOC = "p121" ; NET "pin_sData<9>" LOC = "p118" ; NET "pin_start" LOC = "p31" ; NET "pin_vsync_n" LOC = "p26" ; NET "pin_we_n" LOC = "p123" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE @ 1.4 log @Blitter now mostly works! @ text @d81 1 d87 13 d134 1 @ 1.3 log @Updated GPU core with state machine @ text @d9 60 a75 15 NET "pin_cAddr<0>" LOC = "p75" ; NET "pin_cAddr<10>" LOC = "p38" ; NET "pin_cAddr<11>" LOC = "p44" ; NET "pin_cAddr<12>" LOC = "p46" ; NET "pin_cAddr<13>" LOC = "p49" ; NET "pin_cAddr<14>" LOC = "p57" ; NET "pin_cAddr<1>" LOC = "p74" ; NET "pin_cAddr<2>" LOC = "p30" ; NET "pin_cAddr<3>" LOC = "p31" ; NET "pin_cAddr<4>" LOC = "p78" ; NET "pin_cAddr<5>" LOC = "p42" ; NET "pin_cAddr<6>" LOC = "p40" ; NET "pin_cAddr<7>" LOC = "p29" ; NET "pin_cAddr<8>" LOC = "p28" ; NET "pin_cAddr<9>" LOC = "p27" ; a76 16 NET "pin_cData<0>" LOC = "p80" ; NET "pin_cData<10>" LOC = "p85" ; NET "pin_cData<11>" LOC = "p86" ; NET "pin_cData<12>" LOC = "p87" ; NET "pin_cData<13>" LOC = "p94" ; NET "pin_cData<14>" LOC = "p66" ; NET "pin_cData<15>" LOC = "p64" ; NET "pin_cData<1>" LOC = "p77" ; NET "pin_cData<2>" LOC = "p83" ; NET "pin_cData<3>" LOC = "p79" ; NET "pin_cData<4>" LOC = "p76" ; NET "pin_cData<5>" LOC = "p56" ; NET "pin_cData<6>" LOC = "p54" ; NET "pin_cData<7>" LOC = "p62" ; NET "pin_cData<8>" LOC = "p67" ; NET "pin_cData<9>" LOC = "p84" ; a79 1 NET "pin_cread" LOC = "p39" ; a80 1 NET "pin_cwrite" LOC = "p59" ; d121 1 a121 30 NET "pin_we_n" LOC = "p123" ; NET "pin_cAddr<0>" LOC = "p75" ; NET "pin_cAddr<10>" LOC = "p38" ; NET "pin_cAddr<11>" LOC = "p44" ; NET "pin_cAddr<12>" LOC = "p46" ; NET "pin_cAddr<13>" LOC = "p49" ; NET "pin_cAddr<14>" LOC = "p57" ; NET "pin_cAddr<1>" LOC = "p74" ; NET "pin_cAddr<2>" LOC = "p30" ; NET "pin_cAddr<3>" LOC = "p31" ; NET "pin_cAddr<4>" LOC = "p78" ; NET "pin_cAddr<5>" LOC = "p42" ; NET "pin_cAddr<6>" LOC = "p40" ; NET "pin_cAddr<7>" LOC = "p29" ; NET "pin_cAddr<8>" LOC = "p28" ; NET "pin_cAddr<9>" LOC = "p27" ; NET "pin_cData<0>" LOC = "p80" ; NET "pin_cData<1>" LOC = "p77" ; NET "pin_cData<2>" LOC = "p83" ; NET "pin_cData<3>" LOC = "p79" ; NET "pin_cData<4>" LOC = "p76" ; NET "pin_cData<5>" LOC = "p56" ; NET "pin_cData<6>" LOC = "p54" ; NET "pin_cData<7>" LOC = "p62" ; NET "pin_cread" LOC = "p39" ; NET "pin_cwrite" LOC = "p59" ; NET "pin_SRCce" LOC = "p60" ; @ 1.2 log @added (broken) GPUCore @ text @d94 30 a123 1 NET "pin_we_n" LOC = "p123" ; @ 1.1 log @Initial revision @ text @d16 15 d32 16 d51 1 d53 1 @ 1.1.1.1 log @First Checkin! Using the XESS dual ported RAM controller and the original XSOC (retromicro) VGA driver. Also included a whole bunch of misc stuff.... @ text @@