Wishbone Monitor Controller

Description

Wishbone Monitor Controller is a set of freely available VHDL cores. It contains a central building block containing the basic functionality. It can then be sorrounded by various helper functions to add functionality. The central core comprises of a sync generator, a pixel data generator, a memory interface and a CPU interface. It is specificly designed for slow 8-bit systems (although CPU interface size can be set) with no high needs about a display. It is also designed to be simple and small (cheap). The target is the whole design to be well fit in an Altera ACEX 1k30 device which is available for around 10USD.

Individual module decriptions

Building blocks Sampe configurations

Features

For a fast breafing here are the main design goals and features of the various modules:

Status

ToDo

Download

The first beta version of the Memory Controller can be downloaded from from the CVS repository. You can browse the repository here or use CVSget with module name wb_vga. The design uses the WishboneTK so you will also need that.

Author & Maintainer

Andras Tantos