(See change Log at bottom of page for changes/updates)
 

Description

This is a simple DMA/Bridge IP core. It has two WISHBONE interface. It can perform DMA transfers between the two interfaces or on the same interfaces.

Some of the main features are:

• Up to 31 DMA Channels
• 2, 4 or 8 priority levels
• Linked List Descriptors support
• Circular Buffer support
• FIFO buffer support
• Software & Hardware handshake support
• Automatic Cannel registers Reload support
• Fully configurable

Please see the spec for more details !

Status

• 10/19/2001 Made the core parametarized - No more editing of the wb_dma_defines.v file, just pass the configuration as parameters when you instantiate the core !
• 8/2/2001 Added another feature: Now you can backoff to the beginning of the current transfers (this is useful for things like Etherenet, where you might have to restart in case of collisions or errors).
• New Directory Structure ! We have agreed on a common directory structure at OpenCores.
• PLEASE HELP: I'm looking for people to help me verify the core. Even though I have written a test bench (and checked it in) I would like for somebody else to verify the core as well.
• I will post a message to cores@opencores.org_NOSPAM each time I have an update

Downloading

To get a tared and gziped snapshot from CVS click here, or go to the CVS info page.

The Specification is available here: dma_doc.pdf (about 230K)

Author / Maintainer

I have been doing ASIC design, verification and synthesis for over 15 years. I hope you find this cores useful. Please send me a note if you intend to use it  !

Rudolf Usselmann
rudi@asics.ws_NOSPAM
www.asics.ws

Feel free to send me comments, suggestions and bug reports.

Change Log

10/19/2001 Made the core parameterized
8/2/2001 Added another feature, Directory Structure has changed
6/6/2001 RU Second Release
19/3/2001 RU Released Code
16/3/2001 RU Initial web page