Tools of Alliance package
One of the most important characteristics of Alliance system
is that it provides a common internal data structure to represent the three
basic view of a chip :
Every Alliance tool has been
designed to simply interface with each other, in order to support the proposed
design flow. Some of its tools are :
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asimut. asimut is a VHDL ( Very High Speed Integrated Circuit Hardware Description Language ) logic simulator. The supported VHDL subset allows both structural and behavioral data-flow description ( without timing information ) |
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bop. bop is a logic optimizer and logic synthesis tool. The input file is abehavioral description of the circuit using the same VHDL subset as the logic simulator |
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c4map. c4map is a logic synthesis tool. It has the same functionality than scmap, bit runs without a predefined standard-cell library |
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Dpr. Dpr is a place and route tool for bit slice oriented datapath. This tool allows to mix some glue logic directly within a datapath. |
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druc. druc is a design rule checker. The input
file is a possibly hierarchical-symbolic layout. It checks that a layout is
correct regarding the set of symbolic design rules |
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graal. graal is an hierarchical symbolic layout editor. Graal is used for cell layout design or hierarchical block construction |
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genlib. genlib is a procedural language for
netlist capture and placement description. Genlib provides a consistent set
of C primitives, giving the designers the ability to describe VLSI circuit
netlists in terms of terminals, signals and instances, or circuit topologies
in terms of placement of abutment boxes |
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fpgen. fpgen is a language that has moreless
the same functionalities as genlib, but it is dedicated to datapath
description |
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Lvx. Lvx is a logical versus extracted net-compared tool. The result of a run indicates if the two netlist match together, or if there are different. |
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Lynx. Lynx is a layout extractor. The input is a possibly hierarchical-layout. The layout can be either symbolic or real |
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scmap. scmap is a logic synthesis tool. The output is a netlist of gates. Scmap can map a data-flow description on any standard-cell library, as long as a VHDL data-flow description is provided with each cell |
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scr. scr is a place and route tool for standar-cellls. The output is either an hierarchical or flattened chip core layout without external pads. |
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s2r. s2r is the ultimate tool used in our design flow to perform process mapping. It translates the hierarchical symbolic layout description into physical layout required by a given silicon supplier. |
The VHDL codes generated by Alliance tool is fully compatible with IEEE VHDL standard Ref.1076. This feature allows us to compile or simulate any Alliance VHDL code with commercial design tool such as Altera or Xilinx. Of course, Alliance itself also supports some tools to compile and simulate circuit description, as listed above.
For more detail about Alliance, you may refer to http://www.asim.lip6.fr