------------------------------------------------------------------------------ -- Title : FULL STEP -- Project : ROBOTIC ARM CONTROLLER ------------------------------------------------------------------------------- -- File : full_step.vhd -- Author : R.SATHISH KUMAR -- Created : 25-4-2001 -- Last update : ------------------------------------------------------------------------------- -- Description: -- This vhdl module gives clockwise & anticlockwise control signals for -- fullstep mode. ----------------------------------------------------------------------------- -----full_step library IEEE; use IEEE.std_logic_1164.all; entity full_step is port(CLK : in STD_LOGIC; DIR_SEL : in STD_LOGIC; DIN : in STD_LOGIC_VECTOR(1 downto 0); Y : out STD_LOGIC_VECTOR(3 downto 0)); end full_step; architecture behave of full_step is begin process(CLK,DIN,DIR_SEL) begin if (CLK'event and CLK ='1')then if(DIR_SEL ='1')then if(DIN="00")then Y<="0011"; elsif(DIN="01")then Y<="0110"; elsif(DIN="10")then Y<="1100"; elsif(DIN="11")then Y<="1001"; end if; elsif(DIR_SEL ='0')then if(DIN="00")then Y<="1100"; elsif(DIN="01")then Y<="0110"; elsif(DIN="10")then Y<="0011"; elsif(DIN="11")then Y<="1001"; end if; end if; end if; end process; end behave;